mcimx6ul_eth2_driver.h
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1 /**
2  * @file mcimx6ul_eth2_driver.h
3  * @brief NXP i.MX6UL Ethernet MAC driver (ENET2 instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _MCIMX6UL_ETH2_DRIVER_H
32 #define _MCIMX6UL_ETH2_DRIVER_H
33 
34 //Number of TX buffers
35 #ifndef MCIMX6UL_ETH2_TX_BUFFER_COUNT
36  #define MCIMX6UL_ETH2_TX_BUFFER_COUNT 8
37 #elif (MCIMX6UL_ETH2_TX_BUFFER_COUNT < 1)
38  #error MCIMX6UL_ETH2_TX_BUFFER_COUNT parameter is not valid
39 #endif
40 
41 //TX buffer size
42 #ifndef MCIMX6UL_ETH2_TX_BUFFER_SIZE
43  #define MCIMX6UL_ETH2_TX_BUFFER_SIZE 1536
44 #elif (MCIMX6UL_ETH2_TX_BUFFER_SIZE != 1536)
45  #error MCIMX6UL_ETH2_TX_BUFFER_SIZE parameter is not valid
46 #endif
47 
48 //Number of RX buffers
49 #ifndef MCIMX6UL_ETH2_RX_BUFFER_COUNT
50  #define MCIMX6UL_ETH2_RX_BUFFER_COUNT 8
51 #elif (MCIMX6UL_ETH2_RX_BUFFER_COUNT < 1)
52  #error MCIMX6UL_ETH2_RX_BUFFER_COUNT parameter is not valid
53 #endif
54 
55 //RX buffer size
56 #ifndef MCIMX6UL_ETH2_RX_BUFFER_SIZE
57  #define MCIMX6UL_ETH2_RX_BUFFER_SIZE 1536
58 #elif (MCIMX6UL_ETH2_RX_BUFFER_SIZE != 1536)
59  #error MCIMX6UL_ETH2_RX_BUFFER_SIZE parameter is not valid
60 #endif
61 
62 //Ethernet interrupt priority
63 #ifndef MCIMX6UL_ETH2_IRQ_PRIORITY
64  #define MCIMX6UL_ETH2_IRQ_PRIORITY 21
65 #elif (MCIMX6UL_ETH2_IRQ_PRIORITY < 0)
66  #error MCIMX6UL_ETH2_IRQ_PRIORITY parameter is not valid
67 #endif
68 
69 //Name of the section where to place DMA buffers
70 #ifndef MCIMX6UL_ETH2_RAM_SECTION
71  #define MCIMX6UL_ETH2_RAM_SECTION "NonCacheable"
72 #endif
73 
74 //Enhanced transmit buffer descriptor
75 #define ENET_TBD0_R 0x80000000
76 #define ENET_TBD0_TO1 0x40000000
77 #define ENET_TBD0_W 0x20000000
78 #define ENET_TBD0_TO2 0x10000000
79 #define ENET_TBD0_L 0x08000000
80 #define ENET_TBD0_TC 0x04000000
81 #define ENET_TBD0_DATA_LENGTH 0x0000FFFF
82 #define ENET_TBD1_DATA_POINTER 0xFFFFFFFF
83 #define ENET_TBD2_INT 0x40000000
84 #define ENET_TBD2_TS 0x20000000
85 #define ENET_TBD2_PINS 0x10000000
86 #define ENET_TBD2_IINS 0x08000000
87 #define ENET_TBD2_TXE 0x00008000
88 #define ENET_TBD2_UE 0x00002000
89 #define ENET_TBD2_EE 0x00001000
90 #define ENET_TBD2_FE 0x00000800
91 #define ENET_TBD2_LCE 0x00000400
92 #define ENET_TBD2_OE 0x00000200
93 #define ENET_TBD2_TSE 0x00000100
94 #define ENET_TBD4_BDU 0x80000000
95 #define ENET_TBD5_TIMESTAMP 0xFFFFFFFF
96 
97 //Enhanced receive buffer descriptor
98 #define ENET_RBD0_E 0x80000000
99 #define ENET_RBD0_RO1 0x40000000
100 #define ENET_RBD0_W 0x20000000
101 #define ENET_RBD0_RO2 0x10000000
102 #define ENET_RBD0_L 0x08000000
103 #define ENET_RBD0_M 0x01000000
104 #define ENET_RBD0_BC 0x00800000
105 #define ENET_RBD0_MC 0x00400000
106 #define ENET_RBD0_LG 0x00200000
107 #define ENET_RBD0_NO 0x00100000
108 #define ENET_RBD0_CR 0x00040000
109 #define ENET_RBD0_OV 0x00020000
110 #define ENET_RBD0_TR 0x00010000
111 #define ENET_RBD0_DATA_LENGTH 0x0000FFFF
112 #define ENET_RBD1_DATA_POINTER 0xFFFFFFFF
113 #define ENET_RBD2_ME 0x80000000
114 #define ENET_RBD2_PE 0x04000000
115 #define ENET_RBD2_CE 0x02000000
116 #define ENET_RBD2_UC 0x01000000
117 #define ENET_RBD2_INT 0x00800000
118 #define ENET_RBD2_VPCP 0x0000E000
119 #define ENET_RBD2_ICE 0x00000020
120 #define ENET_RBD2_PCR 0x00000010
121 #define ENET_RBD2_VLAN 0x00000004
122 #define ENET_RBD2_IPV6 0x00000002
123 #define ENET_RBD2_FRAG 0x00000001
124 #define ENET_RBD3_HEADER_LENGTH 0xF8000000
125 #define ENET_RBD3_PROTOCOL_TYPE 0x00FF0000
126 #define ENET_RBD3_PAYLOAD_CHECKSUM 0x0000FFFF
127 #define ENET_RBD4_BDU 0x80000000
128 #define ENET_RBD5_TIMESTAMP 0xFFFFFFFF
129 
130 //C++ guard
131 #ifdef __cplusplus
132 extern "C" {
133 #endif
134 
135 //i.MX6UL Ethernet MAC driver (ENET2 instance)
136 extern const NicDriver mcimx6ulEth2Driver;
137 
138 //i.MX6UL Ethernet MAC related functions
140 void mcimx6ulEth2InitGpio(NetInterface *interface);
142 
143 void mcimx6ulEth2Tick(NetInterface *interface);
144 
145 void mcimx6ulEth2EnableIrq(NetInterface *interface);
146 void mcimx6ulEth2DisableIrq(NetInterface *interface);
147 void mcimx6ulEth2EventHandler(NetInterface *interface);
148 
150  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
151 
153 
156 
157 void mcimx6ulEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr,
158  uint8_t regAddr, uint16_t data);
159 
160 uint16_t mcimx6ulEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
161  uint8_t regAddr);
162 
163 uint32_t mcimx6ulEth2CalcCrc(const void *data, size_t length);
164 
165 //C++ guard
166 #ifdef __cplusplus
167 }
168 #endif
169 
170 #endif
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
error_t mcimx6ulEth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t mcimx6ulEth2ReceivePacket(NetInterface *interface)
Receive a packet.
error_t mcimx6ulEth2Init(NetInterface *interface)
i.MX6UL Ethernet MAC initialization
uint32_t mcimx6ulEth2CalcCrc(const void *data, size_t length)
CRC calculation.
uint16_t mcimx6ulEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void mcimx6ulEth2DisableIrq(NetInterface *interface)
Disable interrupts.
void mcimx6ulEth2EventHandler(NetInterface *interface)
i.MX6UL Ethernet MAC event handler
void mcimx6ulEth2InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
const NicDriver mcimx6ulEth2Driver
i.MX6UL Ethernet MAC driver (ENET2 instance)
void mcimx6ulEth2InitGpio(NetInterface *interface)
GPIO configuration.
error_t mcimx6ulEth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void mcimx6ulEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void mcimx6ulEth2EnableIrq(NetInterface *interface)
Enable interrupts.
void mcimx6ulEth2Tick(NetInterface *interface)
i.MX6UL Ethernet MAC timer handler
error_t mcimx6ulEth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368