mcimx6ul_eth2_driver.c
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1 /**
2  * @file mcimx6ul_eth2_driver.c
3  * @brief i.MX6UL Ethernet MAC controller (ENET2 instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
50 #pragma location = "NonCacheable"
52 //RX buffer
53 #pragma data_alignment = 16
54 #pragma location = "NonCacheable"
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 #pragma location = "NonCacheable"
59 static uint32_t txBufferDesc[MCIMX6UL_ETH2_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 16
62 #pragma location = "NonCacheable"
63 static uint32_t rxBufferDesc[MCIMX6UL_ETH2_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(16), __section__("NonCacheable")));
71 //RX buffer
73  __attribute__((aligned(16), __section__("NonCacheable")));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MCIMX6UL_ETH2_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(16), __section__("NonCacheable")));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MCIMX6UL_ETH2_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(16), __section__("NonCacheable")));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX6UL Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX6UL Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX6UL Ethernet MAC #2...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mcimx6ulEth2InitGpio(interface);
136 
137  //Reset ENET module
138  ENET2->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while(ENET2->ECR & ENET_ECR_RESET_MASK)
141  {
142  }
143 
144  //Receive control register
145  ENET2->RCR = ENET_RCR_MAX_FL(MCIMX6UL_ETH2_RX_BUFFER_SIZE) |
146  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
147 
148  //Transmit control register
149  ENET2->TCR = 0;
150  //Configure MDC clock frequency
151  ENET2->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
152 
153  //PHY transceiver initialization
154  error = interface->phyDriver->init(interface);
155  //Failed to initialize PHY transceiver?
156  if(error)
157  return error;
158 
159  //Set the MAC address of the station (upper 16 bits)
160  value = interface->macAddr.b[5];
161  value |= (interface->macAddr.b[4] << 8);
162  ENET2->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
163 
164  //Set the MAC address of the station (lower 32 bits)
165  value = interface->macAddr.b[3];
166  value |= (interface->macAddr.b[2] << 8);
167  value |= (interface->macAddr.b[1] << 16);
168  value |= (interface->macAddr.b[0] << 24);
169  ENET2->PALR = ENET_PALR_PADDR1(value);
170 
171  //Hash table for unicast address filtering
172  ENET2->IALR = 0;
173  ENET2->IAUR = 0;
174  //Hash table for multicast address filtering
175  ENET2->GALR = 0;
176  ENET2->GAUR = 0;
177 
178  //Disable transmit accelerator functions
179  ENET2->TACC = 0;
180  //Disable receive accelerator functions
181  ENET2->RACC = 0;
182 
183  //Use enhanced buffer descriptors
184  ENET2->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
185  //Clear MIC counters
186  ENET2->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
187 
188  //Initialize buffer descriptors
189  mcimx6ulEth2InitBufferDesc(interface);
190 
191  //Clear any pending interrupts
192  ENET2->EIR = 0xFFFFFFFF;
193  //Enable desired interrupts
194  ENET2->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
195 
196  //Configure ENET interrupt priority
197  GIC_SetPriority(ENET2_IRQn, MCIMX6UL_ETH2_IRQ_PRIORITY);
198 
199  //Enable Ethernet MAC
200  ENET2->ECR |= ENET_ECR_ETHEREN_MASK;
201  //Instruct the DMA to poll the receive descriptor list
202  ENET2->RDAR = ENET_RDAR_RDAR_MASK;
203 
204  //Accept any packets from the upper layer
205  osSetEvent(&interface->nicTxEvent);
206 
207  //Successful initialization
208  return NO_ERROR;
209 }
210 
211 
212 //MCIMX6UL-EVKB or MCIMX6ULL-EVK evaluation board?
213 #if defined(USE_MCIMX6UL_EVKB) || defined(USE_MCIMX6ULL_EVK)
214 
215 /**
216  * @brief GPIO configuration
217  * @param[in] interface Underlying network interface
218  **/
219 
220 void mcimx6ulEth2InitGpio(NetInterface *interface)
221 {
222  gpio_pin_config_t pinConfig;
223 
224  //Enable ENET2_TX_CLK output driver
225  IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(1);
226 
227  //Enable IOMUXC clock
228  CLOCK_EnableClock(kCLOCK_Iomuxc);
229 
230  //Configure ENET2_TX_CLK pin as ENET2_REF_CLK2
231  IOMUXC_SetPinMux(IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2, 1);
232 
233  //Set ENET2_TX_CLK pad properties
234  IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2,
235  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
236  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
237  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
238  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
239  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
240  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
241  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
242  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
243 
244  //Configure ENET2_TX_EN pin as ENET2_TX_EN
245  IOMUXC_SetPinMux(IOMUXC_ENET2_TX_EN_ENET2_TX_EN, 0);
246 
247  //Set ENET2_TX_EN pad properties
248  IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_EN_ENET2_TX_EN,
249  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
250  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
251  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
252  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
253  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
254  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
255  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
256  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
257 
258  //Configure ENET2_TX_DATA0 pin as ENET2_TDATA00
259  IOMUXC_SetPinMux(IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00, 0);
260 
261  //Set ENET2_TX_DATA0 pad properties
262  IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00,
263  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
264  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
265  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
266  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
267  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
268  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
269  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
270  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
271 
272  //Configure ENET2_TX_DATA1 pin as ENET2_TDATA01
273  IOMUXC_SetPinMux(IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01, 0);
274 
275  //Set ENET2_TX_DATA1 pad properties
276  IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01,
277  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
278  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
279  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
280  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
281  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
282  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
283  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
284  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
285 
286  //Configure ENET2_RX_EN pin as ENET2_RX_EN
287  IOMUXC_SetPinMux(IOMUXC_ENET2_RX_EN_ENET2_RX_EN, 0);
288 
289  //Set ENET2_RX_EN pad properties
290  IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_EN_ENET2_RX_EN,
291  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
292  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
293  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
294  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
295  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
296  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
297  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
298  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
299 
300  //Configure ENET2_RX_ER pin as ENET2_RX_ER
301  IOMUXC_SetPinMux(IOMUXC_ENET2_RX_ER_ENET2_RX_ER, 0);
302 
303  //Set ENET2_RX_ER pad properties
304  IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_ER_ENET2_RX_ER,
305  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
306  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
307  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
308  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
309  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
310  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
311  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
312  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
313 
314  //Configure ENET2_RX_DATA0 pin as ENET2_RDATA00
315  IOMUXC_SetPinMux(IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00, 0);
316 
317  //Set ENET2_RX_DATA0 pad properties
318  IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00,
319  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
320  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
321  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
322  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
323  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
324  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
325  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
326  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
327 
328  //Configure ENET2_RX_DATA1 pin as ENET2_RDATA01
329  IOMUXC_SetPinMux(IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01, 0);
330 
331  //Set ENET2_RX_DATA1 pad properties
332  IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01,
333  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
334  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
335  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
336  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
337  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
338  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
339  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
340  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
341 
342 #if defined(USE_MCIMX6UL_EVKB)
343  //Configure SNVS_TAMPER6 pin as GPIO5_IO06
344  IOMUXC_SetPinMux(IOMUXC_SNVS_TAMPER6_GPIO5_IO06, 0);
345 
346  //Set SNVS_TAMPER5 pad properties
347  IOMUXC_SetPinConfig(IOMUXC_SNVS_TAMPER6_GPIO5_IO06,
348  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
349  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
350  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
351  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
352  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
353  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
354  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
355  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
356 
357 #elif defined(USE_MCIMX6ULL_EVK)
358  //Configure SNVS_TAMPER6 pin as GPIO5_IO06
359  IOMUXC_SetPinMux(IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06, 0);
360 
361  //Set SNVS_TAMPER5 pad properties
362  IOMUXC_SetPinConfig(IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06,
363  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
364  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
365  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
366  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
367  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
368  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
369  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
370  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
371 #endif
372 
373  //Configure ENET2_INT as an input
374  pinConfig.direction = kGPIO_DigitalInput;
375  pinConfig.outputLogic = 0;
376  pinConfig.interruptMode = kGPIO_NoIntmode;
377  GPIO_PinInit(GPIO5, 6, &pinConfig);
378 }
379 
380 #endif
381 
382 
383 /**
384  * @brief Initialize buffer descriptors
385  * @param[in] interface Underlying network interface
386  **/
387 
389 {
390  uint_t i;
391  uint32_t address;
392 
393  //Clear TX and RX buffer descriptors
394  memset(txBufferDesc, 0, sizeof(txBufferDesc));
395  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
396 
397  //Initialize TX buffer descriptors
398  for(i = 0; i < MCIMX6UL_ETH2_TX_BUFFER_COUNT; i++)
399  {
400  //Calculate the address of the current TX buffer
401  address = (uint32_t) txBuffer[i];
402  //Transmit buffer address
403  txBufferDesc[i][1] = address;
404  //Generate interrupts
405  txBufferDesc[i][2] = ENET_TBD2_INT;
406  }
407 
408  //Mark the last descriptor entry with the wrap flag
409  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
410  //Initialize TX buffer index
411  txBufferIndex = 0;
412 
413  //Initialize RX buffer descriptors
414  for(i = 0; i < MCIMX6UL_ETH2_RX_BUFFER_COUNT; i++)
415  {
416  //Calculate the address of the current RX buffer
417  address = (uint32_t) rxBuffer[i];
418  //The descriptor is initially owned by the DMA
419  rxBufferDesc[i][0] = ENET_RBD0_E;
420  //Receive buffer address
421  rxBufferDesc[i][1] = address;
422  //Generate interrupts
423  rxBufferDesc[i][2] = ENET_RBD2_INT;
424  }
425 
426  //Mark the last descriptor entry with the wrap flag
427  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
428  //Initialize RX buffer index
429  rxBufferIndex = 0;
430 
431  //Start location of the TX descriptor list
432  ENET2->TDSR = (uint32_t) txBufferDesc;
433  //Start location of the RX descriptor list
434  ENET2->RDSR = (uint32_t) rxBufferDesc;
435  //Maximum receive buffer size
436  ENET2->MRBR = MCIMX6UL_ETH2_RX_BUFFER_SIZE;
437 }
438 
439 
440 /**
441  * @brief i.MX6UL Ethernet MAC timer handler
442  *
443  * This routine is periodically called by the TCP/IP stack to
444  * handle periodic operations such as polling the link state
445  *
446  * @param[in] interface Underlying network interface
447  **/
448 
450 {
451  //Handle periodic operations
452  interface->phyDriver->tick(interface);
453 }
454 
455 
456 /**
457  * @brief Enable interrupts
458  * @param[in] interface Underlying network interface
459  **/
460 
462 {
463  //Enable Ethernet MAC interrupts
464  GIC_EnableIRQ(ENET2_IRQn);
465  //Enable Ethernet PHY interrupts
466  interface->phyDriver->enableIrq(interface);
467 }
468 
469 
470 /**
471  * @brief Disable interrupts
472  * @param[in] interface Underlying network interface
473  **/
474 
476 {
477  //Disable Ethernet MAC interrupts
478  GIC_DisableIRQ(ENET2_IRQn);
479  //Disable Ethernet PHY interrupts
480  interface->phyDriver->disableIrq(interface);
481 }
482 
483 
484 /**
485  * @brief Ethernet MAC interrupt (ENET2 instance)
486  * @param[in] giccIar Value of the GICC_IAR register
487  * @param[in] userParam User parameter
488  **/
489 
490 void ENET2_DriverIRQHandler (uint32_t giccIar, void *userParam)
491 {
492  bool_t flag;
493  uint32_t events;
494 
495  //Interrupt service routine prologue
496  osEnterIsr();
497 
498  //This flag will be set if a higher priority task must be woken
499  flag = FALSE;
500  //Read interrupt event register
501  events = ENET2->EIR;
502 
503  //A packet has been transmitted?
504  if(events & ENET_EIR_TXF_MASK)
505  {
506  //Clear TXF interrupt flag
507  ENET2->EIR = ENET_EIR_TXF_MASK;
508 
509  //Check whether the TX buffer is available for writing
510  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
511  {
512  //Notify the TCP/IP stack that the transmitter is ready to send
513  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
514  }
515 
516  //Instruct the DMA to poll the transmit descriptor list
517  ENET2->TDAR = ENET_TDAR_TDAR_MASK;
518  }
519 
520  //A packet has been received?
521  if(events & ENET_EIR_RXF_MASK)
522  {
523  //Disable RXF interrupt
524  ENET2->EIMR &= ~ENET_EIMR_RXF_MASK;
525 
526  //Set event flag
527  nicDriverInterface->nicEvent = TRUE;
528  //Notify the TCP/IP stack of the event
529  flag = osSetEventFromIsr(&netEvent);
530  }
531 
532  //System bus error?
533  if(events & ENET_EIR_EBERR_MASK)
534  {
535  //Disable EBERR interrupt
536  ENET2->EIMR &= ~ENET_EIMR_EBERR_MASK;
537 
538  //Set event flag
539  nicDriverInterface->nicEvent = TRUE;
540  //Notify the TCP/IP stack of the event
541  flag |= osSetEventFromIsr(&netEvent);
542  }
543 
544  //Interrupt service routine epilogue
545  osExitIsr(flag);
546 }
547 
548 
549 /**
550  * @brief i.MX6UL Ethernet MAC event handler
551  * @param[in] interface Underlying network interface
552  **/
553 
555 {
556  error_t error;
557  uint32_t status;
558 
559  //Read interrupt event register
560  status = ENET2->EIR;
561 
562  //Packet received?
563  if(status & ENET_EIR_RXF_MASK)
564  {
565  //Clear RXF interrupt flag
566  ENET2->EIR = ENET_EIR_RXF_MASK;
567 
568  //Process all pending packets
569  do
570  {
571  //Read incoming packet
572  error = mcimx6ulEth2ReceivePacket(interface);
573 
574  //No more data in the receive buffer?
575  } while(error != ERROR_BUFFER_EMPTY);
576  }
577 
578  //System bus error?
579  if(status & ENET_EIR_EBERR_MASK)
580  {
581  //Clear EBERR interrupt flag
582  ENET2->EIR = ENET_EIR_EBERR_MASK;
583 
584  //Disable Ethernet MAC
585  ENET2->ECR &= ~ENET_ECR_ETHEREN_MASK;
586  //Reset buffer descriptors
587  mcimx6ulEth2InitBufferDesc(interface);
588  //Resume normal operation
589  ENET2->ECR |= ENET_ECR_ETHEREN_MASK;
590  //Instruct the DMA to poll the receive descriptor list
591  ENET2->RDAR = ENET_RDAR_RDAR_MASK;
592  }
593 
594  //Re-enable Ethernet MAC interrupts
595  ENET2->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
596 }
597 
598 
599 /**
600  * @brief Send a packet
601  * @param[in] interface Underlying network interface
602  * @param[in] buffer Multi-part buffer containing the data to send
603  * @param[in] offset Offset to the first data byte
604  * @return Error code
605  **/
606 
608  const NetBuffer *buffer, size_t offset)
609 {
610  static uint8_t temp[MCIMX6UL_ETH2_TX_BUFFER_SIZE];
611  size_t length;
612 
613  //Retrieve the length of the packet
614  length = netBufferGetLength(buffer) - offset;
615 
616  //Check the frame length
618  {
619  //The transmitter can accept another packet
620  osSetEvent(&interface->nicTxEvent);
621  //Report an error
622  return ERROR_INVALID_LENGTH;
623  }
624 
625  //Make sure the current buffer is available for writing
626  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
627  return ERROR_FAILURE;
628 
629  //Copy user data to the transmit buffer
630  netBufferRead(temp, buffer, offset, length);
631  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
632 
633  //Clear BDU flag
634  txBufferDesc[txBufferIndex][4] = 0;
635 
636  //Check current index
637  if(txBufferIndex < (MCIMX6UL_ETH2_TX_BUFFER_COUNT - 1))
638  {
639  //Give the ownership of the descriptor to the DMA engine
640  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
642 
643  //Point to the next buffer
644  txBufferIndex++;
645  }
646  else
647  {
648  //Give the ownership of the descriptor to the DMA engine
649  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
651 
652  //Wrap around
653  txBufferIndex = 0;
654  }
655 
656  //Data synchronization barrier
657  __DSB();
658 
659  //Instruct the DMA to poll the transmit descriptor list
660  ENET2->TDAR = ENET_TDAR_TDAR_MASK;
661 
662  //Check whether the next buffer is available for writing
663  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
664  {
665  //The transmitter can accept another packet
666  osSetEvent(&interface->nicTxEvent);
667  }
668 
669  //Successful processing
670  return NO_ERROR;
671 }
672 
673 
674 /**
675  * @brief Receive a packet
676  * @param[in] interface Underlying network interface
677  * @return Error code
678  **/
679 
681 {
682  static uint8_t temp[MCIMX6UL_ETH2_RX_BUFFER_SIZE];
683  error_t error;
684  size_t n;
685 
686  //Make sure the current buffer is available for reading
687  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
688  {
689  //The frame should not span multiple buffers
690  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
691  {
692  //Check whether an error occurred
693  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
695  {
696  //Retrieve the length of the frame
697  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
698  //Limit the number of data to read
700 
701  //Copy data from the receive buffer
702  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
703 
704  //Pass the packet to the upper layer
705  nicProcessPacket(interface, temp, n);
706 
707  //Valid packet received
708  error = NO_ERROR;
709  }
710  else
711  {
712  //The received packet contains an error
713  error = ERROR_INVALID_PACKET;
714  }
715  }
716  else
717  {
718  //The packet is not valid
719  error = ERROR_INVALID_PACKET;
720  }
721 
722  //Clear BDU flag
723  rxBufferDesc[rxBufferIndex][4] = 0;
724 
725  //Check current index
726  if(rxBufferIndex < (MCIMX6UL_ETH2_RX_BUFFER_COUNT - 1))
727  {
728  //Give the ownership of the descriptor back to the DMA engine
729  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
730  //Point to the next buffer
731  rxBufferIndex++;
732  }
733  else
734  {
735  //Give the ownership of the descriptor back to the DMA engine
736  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
737  //Wrap around
738  rxBufferIndex = 0;
739  }
740 
741  //Instruct the DMA to poll the receive descriptor list
742  ENET2->RDAR = ENET_RDAR_RDAR_MASK;
743  }
744  else
745  {
746  //No more data in the receive buffer
747  error = ERROR_BUFFER_EMPTY;
748  }
749 
750  //Return status code
751  return error;
752 }
753 
754 
755 /**
756  * @brief Configure MAC address filtering
757  * @param[in] interface Underlying network interface
758  * @return Error code
759  **/
760 
762 {
763  uint_t i;
764  uint_t k;
765  uint32_t crc;
766  uint32_t unicastHashTable[2];
767  uint32_t multicastHashTable[2];
768  MacFilterEntry *entry;
769 
770  //Debug message
771  TRACE_DEBUG("Updating MAC filter...\r\n");
772 
773  //Clear hash table (unicast address filtering)
774  unicastHashTable[0] = 0;
775  unicastHashTable[1] = 0;
776 
777  //Clear hash table (multicast address filtering)
778  multicastHashTable[0] = 0;
779  multicastHashTable[1] = 0;
780 
781  //The MAC address filter contains the list of MAC addresses to accept
782  //when receiving an Ethernet frame
783  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
784  {
785  //Point to the current entry
786  entry = &interface->macAddrFilter[i];
787 
788  //Valid entry?
789  if(entry->refCount > 0)
790  {
791  //Compute CRC over the current MAC address
792  crc = mcimx6ulEth2CalcCrc(&entry->addr, sizeof(MacAddr));
793 
794  //The upper 6 bits in the CRC register are used to index the
795  //contents of the hash table
796  k = (crc >> 26) & 0x3F;
797 
798  //Multicast address?
799  if(macIsMulticastAddr(&entry->addr))
800  {
801  //Update the multicast hash table
802  multicastHashTable[k / 32] |= (1 << (k % 32));
803  }
804  else
805  {
806  //Update the unicast hash table
807  unicastHashTable[k / 32] |= (1 << (k % 32));
808  }
809  }
810  }
811 
812  //Write the hash table (unicast address filtering)
813  ENET2->IALR = unicastHashTable[0];
814  ENET2->IAUR = unicastHashTable[1];
815 
816  //Write the hash table (multicast address filtering)
817  ENET2->GALR = multicastHashTable[0];
818  ENET2->GAUR = multicastHashTable[1];
819 
820  //Debug message
821  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET2->IALR);
822  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET2->IAUR);
823  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET2->GALR);
824  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET2->GAUR);
825 
826  //Successful processing
827  return NO_ERROR;
828 }
829 
830 
831 /**
832  * @brief Adjust MAC configuration parameters for proper operation
833  * @param[in] interface Underlying network interface
834  * @return Error code
835  **/
836 
838 {
839  //Disable Ethernet MAC while modifying configuration registers
840  ENET2->ECR &= ~ENET_ECR_ETHEREN_MASK;
841 
842  //10BASE-T or 100BASE-TX operation mode?
843  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
844  {
845  //100 Mbps operation
846  ENET2->RCR &= ~ENET_RCR_RMII_10T_MASK;
847  }
848  else
849  {
850  //10 Mbps operation
851  ENET2->RCR |= ENET_RCR_RMII_10T_MASK;
852  }
853 
854  //Half-duplex or full-duplex mode?
855  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
856  {
857  //Full-duplex mode
858  ENET2->TCR |= ENET_TCR_FDEN_MASK;
859  //Receive path operates independently of transmit
860  ENET2->RCR &= ~ENET_RCR_DRT_MASK;
861  }
862  else
863  {
864  //Half-duplex mode
865  ENET2->TCR &= ~ENET_TCR_FDEN_MASK;
866  //Disable reception of frames while transmitting
867  ENET2->RCR |= ENET_RCR_DRT_MASK;
868  }
869 
870  //Reset buffer descriptors
871  mcimx6ulEth2InitBufferDesc(interface);
872 
873  //Re-enable Ethernet MAC
874  ENET2->ECR |= ENET_ECR_ETHEREN_MASK;
875  //Instruct the DMA to poll the receive descriptor list
876  ENET2->RDAR = ENET_RDAR_RDAR_MASK;
877 
878  //Successful processing
879  return NO_ERROR;
880 }
881 
882 
883 /**
884  * @brief Write PHY register
885  * @param[in] opcode Access type (2 bits)
886  * @param[in] phyAddr PHY address (5 bits)
887  * @param[in] regAddr Register address (5 bits)
888  * @param[in] data Register value
889  **/
890 
891 void mcimx6ulEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr,
892  uint8_t regAddr, uint16_t data)
893 {
894  uint32_t temp;
895 
896  //Valid opcode?
897  if(opcode == SMI_OPCODE_WRITE)
898  {
899  //Set up a write operation
900  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
901  //PHY address
902  temp |= ENET_MMFR_PA(phyAddr);
903  //Register address
904  temp |= ENET_MMFR_RA(regAddr);
905  //Register value
906  temp |= ENET_MMFR_DATA(data);
907 
908  //Clear MII interrupt flag
909  ENET1->EIR = ENET_EIR_MII_MASK;
910  //Start a write operation
911  ENET1->MMFR = temp;
912 
913  //Wait for the write to complete
914  while(!(ENET1->EIR & ENET_EIR_MII_MASK))
915  {
916  }
917  }
918  else
919  {
920  //The MAC peripheral only supports standard Clause 22 opcodes
921  }
922 }
923 
924 
925 /**
926  * @brief Read PHY register
927  * @param[in] opcode Access type (2 bits)
928  * @param[in] phyAddr PHY address (5 bits)
929  * @param[in] regAddr Register address (5 bits)
930  * @return Register value
931  **/
932 
933 uint16_t mcimx6ulEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
934  uint8_t regAddr)
935 {
936  uint16_t data;
937  uint32_t temp;
938 
939  //Valid opcode?
940  if(opcode == SMI_OPCODE_READ)
941  {
942  //Set up a read operation
943  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
944  //PHY address
945  temp |= ENET_MMFR_PA(phyAddr);
946  //Register address
947  temp |= ENET_MMFR_RA(regAddr);
948 
949  //Clear MII interrupt flag
950  ENET1->EIR = ENET_EIR_MII_MASK;
951  //Start a read operation
952  ENET1->MMFR = temp;
953 
954  //Wait for the read to complete
955  while(!(ENET1->EIR & ENET_EIR_MII_MASK))
956  {
957  }
958 
959  //Get register value
960  data = ENET1->MMFR & ENET_MMFR_DATA_MASK;
961  }
962  else
963  {
964  //The MAC peripheral only supports standard Clause 22 opcodes
965  data = 0;
966  }
967 
968  //Return the value of the PHY register
969  return data;
970 }
971 
972 
973 /**
974  * @brief CRC calculation
975  * @param[in] data Pointer to the data over which to calculate the CRC
976  * @param[in] length Number of bytes to process
977  * @return Resulting CRC value
978  **/
979 
980 uint32_t mcimx6ulEth2CalcCrc(const void *data, size_t length)
981 {
982  uint_t i;
983  uint_t j;
984 
985  //Point to the data over which to calculate the CRC
986  const uint8_t *p = (uint8_t *) data;
987  //CRC preset value
988  uint32_t crc = 0xFFFFFFFF;
989 
990  //Loop through data
991  for(i = 0; i < length; i++)
992  {
993  //Update CRC value
994  crc ^= p[i];
995  //The message is processed bit by bit
996  for(j = 0; j < 8; j++)
997  {
998  if(crc & 0x00000001)
999  crc = (crc >> 1) ^ 0xEDB88320;
1000  else
1001  crc = crc >> 1;
1002  }
1003  }
1004 
1005  //Return CRC value
1006  return crc;
1007 }
void mcimx6ulEth2EventHandler(NetInterface *interface)
i.MX6UL Ethernet MAC event handler
MacAddr addr
MAC address.
Definition: ethernet.h:222
#define ENET_RBD0_L
#define ENET_RBD0_W
void ENET2_DriverIRQHandler(uint32_t giccIar, void *userParam)
Ethernet MAC interrupt (ENET2 instance)
error_t mcimx6ulEth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define ENET_RBD0_OV
TCP/IP stack core.
void mcimx6ulEth2DisableIrq(NetInterface *interface)
Disable interrupts.
Debugging facilities.
uint8_t p
Definition: ndp.h:298
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
Generic error code.
Definition: error.h:45
void mcimx6ulEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
#define ENET_TBD2_INT
error_t mcimx6ulEth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define txBuffer
#define MCIMX6UL_ETH2_IRQ_PRIORITY
#define SMI_OPCODE_READ
Definition: nic.h:63
#define ENET_RBD0_LG
__start_packed struct @108 MacAddr
MAC address.
#define TRUE
Definition: os_port.h:50
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
void mcimx6ulEth2InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define ENET_RBD0_E
#define ENET_TBD0_R
#define ENET_RBD0_NO
uint8_t opcode
Definition: dns_common.h:172
#define ENET_TBD0_DATA_LENGTH
#define MCIMX6UL_ETH2_RX_BUFFER_COUNT
#define ENET_RBD0_CR
const NicDriver mcimx6ulEth2Driver
i.MX6UL Ethernet MAC driver
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
uint16_t mcimx6ulEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
NIC driver.
Definition: nic.h:179
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MIN(a, b)
Definition: os_port.h:62
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void mcimx6ulEth2EnableIrq(NetInterface *interface)
Enable interrupts.
error_t mcimx6ulEth2ReceivePacket(NetInterface *interface)
Receive a packet.
#define TRACE_INFO(...)
Definition: debug.h:94
#define ENET_TBD0_TC
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
error_t mcimx6ulEth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
Ethernet interface.
Definition: nic.h:79
#define ENET_RBD2_INT
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:74
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define ENET_RBD0_DATA_LENGTH
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
unsigned int uint_t
Definition: compiler_port.h:45
void mcimx6ulEth2InitGpio(NetInterface *interface)
error_t mcimx6ulEth2Init(NetInterface *interface)
i.MX6UL Ethernet MAC initialization
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint8_t value[]
Definition: dtls_misc.h:143
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
void mcimx6ulEth2Tick(NetInterface *interface)
i.MX6UL Ethernet MAC timer handler
#define MCIMX6UL_ETH2_TX_BUFFER_COUNT
#define osExitIsr(flag)
#define osEnterIsr()
#define ENET_TBD0_L
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define ENET_TBD0_W
uint32_t mcimx6ulEth2CalcCrc(const void *data, size_t length)
CRC calculation.
#define ENET_RBD0_TR
#define MCIMX6UL_ETH2_TX_BUFFER_SIZE
#define FALSE
Definition: os_port.h:46
i.MX6UL Ethernet MAC controller (ENET2 instance)
int bool_t
Definition: compiler_port.h:49
#define MCIMX6UL_ETH2_RX_BUFFER_SIZE
MAC filter table entry.
Definition: ethernet.h:220
#define TRACE_DEBUG(...)
Definition: debug.h:106