mcimx6ul_eth2_driver.c
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1 /**
2  * @file mcimx6ul_eth1_driver.c
3  * @brief i.MX6UL Ethernet MAC controller (ENET2 instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
50 #pragma location = "NonCacheable"
52 //RX buffer
53 #pragma data_alignment = 16
54 #pragma location = "NonCacheable"
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 #pragma location = "NonCacheable"
59 static uint32_t txBufferDesc[MCIMX6UL_ETH2_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 16
62 #pragma location = "NonCacheable"
63 static uint32_t rxBufferDesc[MCIMX6UL_ETH2_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(16), __section__("NonCacheable")));
71 //RX buffer
73  __attribute__((aligned(16), __section__("NonCacheable")));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MCIMX6UL_ETH2_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(16), __section__("NonCacheable")));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MCIMX6UL_ETH2_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(16), __section__("NonCacheable")));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX6UL Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX6UL Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX6UL Ethernet MAC #2...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mcimx6ulEth2InitGpio(interface);
136 
137  //Reset ENET module
138  ENET2->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while(ENET2->ECR & ENET_ECR_RESET_MASK);
141 
142  //Receive control register
143  ENET2->RCR = ENET_RCR_MAX_FL(MCIMX6UL_ETH2_RX_BUFFER_SIZE) |
144  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
145 
146  //Transmit control register
147  ENET2->TCR = 0;
148  //Configure MDC clock frequency
149  ENET2->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
150 
151  //PHY transceiver initialization
152  error = interface->phyDriver->init(interface);
153  //Failed to initialize PHY transceiver?
154  if(error)
155  return error;
156 
157  //Set the MAC address of the station (upper 16 bits)
158  value = interface->macAddr.b[5];
159  value |= (interface->macAddr.b[4] << 8);
160  ENET2->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
161 
162  //Set the MAC address of the station (lower 32 bits)
163  value = interface->macAddr.b[3];
164  value |= (interface->macAddr.b[2] << 8);
165  value |= (interface->macAddr.b[1] << 16);
166  value |= (interface->macAddr.b[0] << 24);
167  ENET2->PALR = ENET_PALR_PADDR1(value);
168 
169  //Hash table for unicast address filtering
170  ENET2->IALR = 0;
171  ENET2->IAUR = 0;
172  //Hash table for multicast address filtering
173  ENET2->GALR = 0;
174  ENET2->GAUR = 0;
175 
176  //Disable transmit accelerator functions
177  ENET2->TACC = 0;
178  //Disable receive accelerator functions
179  ENET2->RACC = 0;
180 
181  //Use enhanced buffer descriptors
182  ENET2->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
183  //Clear MIC counters
184  ENET2->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
185 
186  //Initialize buffer descriptors
187  mcimx6ulEth2InitBufferDesc(interface);
188 
189  //Clear any pending interrupts
190  ENET2->EIR = 0xFFFFFFFF;
191  //Enable desired interrupts
192  ENET2->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
193 
194  //Configure ENET interrupt priority
195  GIC_SetPriority(ENET2_IRQn, MCIMX6UL_ETH2_IRQ_PRIORITY);
196 
197  //Enable Ethernet MAC
198  ENET2->ECR |= ENET_ECR_ETHEREN_MASK;
199  //Instruct the DMA to poll the receive descriptor list
200  ENET2->RDAR = ENET_RDAR_RDAR_MASK;
201 
202  //Accept any packets from the upper layer
203  osSetEvent(&interface->nicTxEvent);
204 
205  //Successful initialization
206  return NO_ERROR;
207 }
208 
209 
210 //MCIMX6UL-EVKB or MCIMX6ULL-EVK evaluation board?
211 #if defined(USE_MCIMX6UL_EVKB) || defined(USE_MCIMX6ULL_EVK)
212 
213 /**
214  * @brief GPIO configuration
215  * @param[in] interface Underlying network interface
216  **/
217 
218 void mcimx6ulEth2InitGpio(NetInterface *interface)
219 {
220  gpio_pin_config_t pinConfig;
221 
222  //Enable ENET2_TX_CLK output driver
223  IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(1);
224 
225  //Enable IOMUXC clock
226  CLOCK_EnableClock(kCLOCK_Iomuxc);
227 
228  //Configure ENET2_TX_CLK pin as ENET2_REF_CLK2
229  IOMUXC_SetPinMux(IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2, 1);
230 
231  //Set ENET2_TX_CLK pad properties
232  IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2,
233  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
234  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
235  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
236  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
237  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
238  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
239  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
240  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
241 
242  //Configure ENET2_TX_EN pin as ENET2_TX_EN
243  IOMUXC_SetPinMux(IOMUXC_ENET2_TX_EN_ENET2_TX_EN, 0);
244 
245  //Set ENET2_TX_EN pad properties
246  IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_EN_ENET2_TX_EN,
247  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
248  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
249  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
250  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
251  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
252  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
253  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
254  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
255 
256  //Configure ENET2_TX_DATA0 pin as ENET2_TDATA00
257  IOMUXC_SetPinMux(IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00, 0);
258 
259  //Set ENET2_TX_DATA0 pad properties
260  IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00,
261  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
262  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
263  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
264  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
265  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
266  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
267  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
268  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
269 
270  //Configure ENET2_TX_DATA1 pin as ENET2_TDATA01
271  IOMUXC_SetPinMux(IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01, 0);
272 
273  //Set ENET2_TX_DATA1 pad properties
274  IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01,
275  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
276  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
277  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
278  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
279  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
280  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
281  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
282  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
283 
284  //Configure ENET2_RX_EN pin as ENET2_RX_EN
285  IOMUXC_SetPinMux(IOMUXC_ENET2_RX_EN_ENET2_RX_EN, 0);
286 
287  //Set ENET2_RX_EN pad properties
288  IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_EN_ENET2_RX_EN,
289  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
290  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
291  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
292  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
293  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
294  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
295  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
296  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
297 
298  //Configure ENET2_RX_ER pin as ENET2_RX_ER
299  IOMUXC_SetPinMux(IOMUXC_ENET2_RX_ER_ENET2_RX_ER, 0);
300 
301  //Set ENET2_RX_ER pad properties
302  IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_ER_ENET2_RX_ER,
303  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
304  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
305  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
306  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
307  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
308  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
309  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
310  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
311 
312  //Configure ENET2_RX_DATA0 pin as ENET2_RDATA00
313  IOMUXC_SetPinMux(IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00, 0);
314 
315  //Set ENET2_RX_DATA0 pad properties
316  IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00,
317  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
318  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
319  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
320  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
321  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
322  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
323  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
324  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
325 
326  //Configure ENET2_RX_DATA1 pin as ENET2_RDATA01
327  IOMUXC_SetPinMux(IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01, 0);
328 
329  //Set ENET2_RX_DATA1 pad properties
330  IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01,
331  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
332  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
333  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
334  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
335  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
336  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
337  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
338  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
339 
340 #if defined(USE_MCIMX6UL_EVKB)
341  //Configure SNVS_TAMPER6 pin as GPIO5_IO06
342  IOMUXC_SetPinMux(IOMUXC_SNVS_TAMPER6_GPIO5_IO06, 0);
343 
344  //Set SNVS_TAMPER5 pad properties
345  IOMUXC_SetPinConfig(IOMUXC_SNVS_TAMPER6_GPIO5_IO06,
346  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
347  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
348  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
349  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
350  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
351  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
352  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
353  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
354 
355 #elif defined(USE_MCIMX6ULL_EVK)
356  //Configure SNVS_TAMPER6 pin as GPIO5_IO06
357  IOMUXC_SetPinMux(IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06, 0);
358 
359  //Set SNVS_TAMPER5 pad properties
360  IOMUXC_SetPinConfig(IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06,
361  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
362  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
363  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
364  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
365  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
366  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
367  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
368  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
369 #endif
370 
371  //Configure ENET2_INT as an input
372  pinConfig.direction = kGPIO_DigitalInput;
373  pinConfig.outputLogic = 0;
374  pinConfig.interruptMode = kGPIO_NoIntmode;
375  GPIO_PinInit(GPIO5, 6, &pinConfig);
376 }
377 
378 #endif
379 
380 
381 /**
382  * @brief Initialize buffer descriptors
383  * @param[in] interface Underlying network interface
384  **/
385 
387 {
388  uint_t i;
389  uint32_t address;
390 
391  //Clear TX and RX buffer descriptors
392  memset(txBufferDesc, 0, sizeof(txBufferDesc));
393  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
394 
395  //Initialize TX buffer descriptors
396  for(i = 0; i < MCIMX6UL_ETH2_TX_BUFFER_COUNT; i++)
397  {
398  //Calculate the address of the current TX buffer
399  address = (uint32_t) txBuffer[i];
400  //Transmit buffer address
401  txBufferDesc[i][1] = address;
402  //Generate interrupts
403  txBufferDesc[i][2] = ENET_TBD2_INT;
404  }
405 
406  //Mark the last descriptor entry with the wrap flag
407  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
408  //Initialize TX buffer index
409  txBufferIndex = 0;
410 
411  //Initialize RX buffer descriptors
412  for(i = 0; i < MCIMX6UL_ETH2_RX_BUFFER_COUNT; i++)
413  {
414  //Calculate the address of the current RX buffer
415  address = (uint32_t) rxBuffer[i];
416  //The descriptor is initially owned by the DMA
417  rxBufferDesc[i][0] = ENET_RBD0_E;
418  //Receive buffer address
419  rxBufferDesc[i][1] = address;
420  //Generate interrupts
421  rxBufferDesc[i][2] = ENET_RBD2_INT;
422  }
423 
424  //Mark the last descriptor entry with the wrap flag
425  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
426  //Initialize RX buffer index
427  rxBufferIndex = 0;
428 
429  //Start location of the TX descriptor list
430  ENET2->TDSR = (uint32_t) txBufferDesc;
431  //Start location of the RX descriptor list
432  ENET2->RDSR = (uint32_t) rxBufferDesc;
433  //Maximum receive buffer size
434  ENET2->MRBR = MCIMX6UL_ETH2_RX_BUFFER_SIZE;
435 }
436 
437 
438 /**
439  * @brief i.MX6UL Ethernet MAC timer handler
440  *
441  * This routine is periodically called by the TCP/IP stack to
442  * handle periodic operations such as polling the link state
443  *
444  * @param[in] interface Underlying network interface
445  **/
446 
448 {
449  //Handle periodic operations
450  interface->phyDriver->tick(interface);
451 }
452 
453 
454 /**
455  * @brief Enable interrupts
456  * @param[in] interface Underlying network interface
457  **/
458 
460 {
461  //Enable Ethernet MAC interrupts
462  GIC_EnableIRQ(ENET2_IRQn);
463  //Enable Ethernet PHY interrupts
464  interface->phyDriver->enableIrq(interface);
465 }
466 
467 
468 /**
469  * @brief Disable interrupts
470  * @param[in] interface Underlying network interface
471  **/
472 
474 {
475  //Disable Ethernet MAC interrupts
476  GIC_DisableIRQ(ENET2_IRQn);
477  //Disable Ethernet PHY interrupts
478  interface->phyDriver->disableIrq(interface);
479 }
480 
481 
482 /**
483  * @brief Ethernet MAC interrupt (ENET2 instance)
484  * @param[in] giccIar Value of the GICC_IAR register
485  * @param[in] userParam User parameter
486  **/
487 
488 void ENET2_DriverIRQHandler (uint32_t giccIar, void *userParam)
489 {
490  bool_t flag;
491  uint32_t events;
492 
493  //Enter interrupt service routine
494  osEnterIsr();
495 
496  //This flag will be set if a higher priority task must be woken
497  flag = FALSE;
498  //Read interrupt event register
499  events = ENET2->EIR;
500 
501  //A packet has been transmitted?
502  if(events & ENET_EIR_TXF_MASK)
503  {
504  //Clear TXF interrupt flag
505  ENET2->EIR = ENET_EIR_TXF_MASK;
506 
507  //Check whether the TX buffer is available for writing
508  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
509  {
510  //Notify the TCP/IP stack that the transmitter is ready to send
511  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
512  }
513 
514  //Instruct the DMA to poll the transmit descriptor list
515  ENET2->TDAR = ENET_TDAR_TDAR_MASK;
516  }
517 
518  //A packet has been received?
519  if(events & ENET_EIR_RXF_MASK)
520  {
521  //Disable RXF interrupt
522  ENET2->EIMR &= ~ENET_EIMR_RXF_MASK;
523 
524  //Set event flag
525  nicDriverInterface->nicEvent = TRUE;
526  //Notify the TCP/IP stack of the event
527  flag = osSetEventFromIsr(&netEvent);
528  }
529 
530  //System bus error?
531  if(events & ENET_EIR_EBERR_MASK)
532  {
533  //Disable EBERR interrupt
534  ENET2->EIMR &= ~ENET_EIMR_EBERR_MASK;
535 
536  //Set event flag
537  nicDriverInterface->nicEvent = TRUE;
538  //Notify the TCP/IP stack of the event
539  flag |= osSetEventFromIsr(&netEvent);
540  }
541 
542  //Leave interrupt service routine
543  osExitIsr(flag);
544 }
545 
546 
547 /**
548  * @brief i.MX6UL Ethernet MAC event handler
549  * @param[in] interface Underlying network interface
550  **/
551 
553 {
554  error_t error;
555  uint32_t status;
556 
557  //Read interrupt event register
558  status = ENET2->EIR;
559 
560  //Packet received?
561  if(status & ENET_EIR_RXF_MASK)
562  {
563  //Clear RXF interrupt flag
564  ENET2->EIR = ENET_EIR_RXF_MASK;
565 
566  //Process all pending packets
567  do
568  {
569  //Read incoming packet
570  error = mcimx6ulEth2ReceivePacket(interface);
571 
572  //No more data in the receive buffer?
573  } while(error != ERROR_BUFFER_EMPTY);
574  }
575 
576  //System bus error?
577  if(status & ENET_EIR_EBERR_MASK)
578  {
579  //Clear EBERR interrupt flag
580  ENET2->EIR = ENET_EIR_EBERR_MASK;
581 
582  //Disable Ethernet MAC
583  ENET2->ECR &= ~ENET_ECR_ETHEREN_MASK;
584  //Reset buffer descriptors
585  mcimx6ulEth2InitBufferDesc(interface);
586  //Resume normal operation
587  ENET2->ECR |= ENET_ECR_ETHEREN_MASK;
588  //Instruct the DMA to poll the receive descriptor list
589  ENET2->RDAR = ENET_RDAR_RDAR_MASK;
590  }
591 
592  //Re-enable Ethernet MAC interrupts
593  ENET2->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
594 }
595 
596 
597 /**
598  * @brief Send a packet
599  * @param[in] interface Underlying network interface
600  * @param[in] buffer Multi-part buffer containing the data to send
601  * @param[in] offset Offset to the first data byte
602  * @return Error code
603  **/
604 
606  const NetBuffer *buffer, size_t offset)
607 {
608  static uint8_t temp[MCIMX6UL_ETH2_TX_BUFFER_SIZE];
609  size_t length;
610 
611  //Retrieve the length of the packet
612  length = netBufferGetLength(buffer) - offset;
613 
614  //Check the frame length
616  {
617  //The transmitter can accept another packet
618  osSetEvent(&interface->nicTxEvent);
619  //Report an error
620  return ERROR_INVALID_LENGTH;
621  }
622 
623  //Make sure the current buffer is available for writing
624  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
625  return ERROR_FAILURE;
626 
627  //Copy user data to the transmit buffer
628  netBufferRead(temp, buffer, offset, length);
629  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
630 
631  //Clear BDU flag
632  txBufferDesc[txBufferIndex][4] = 0;
633 
634  //Check current index
635  if(txBufferIndex < (MCIMX6UL_ETH2_TX_BUFFER_COUNT - 1))
636  {
637  //Give the ownership of the descriptor to the DMA engine
638  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
640 
641  //Point to the next buffer
642  txBufferIndex++;
643  }
644  else
645  {
646  //Give the ownership of the descriptor to the DMA engine
647  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
649 
650  //Wrap around
651  txBufferIndex = 0;
652  }
653 
654  //Data synchronization barrier
655  __DSB();
656 
657  //Instruct the DMA to poll the transmit descriptor list
658  ENET2->TDAR = ENET_TDAR_TDAR_MASK;
659 
660  //Check whether the next buffer is available for writing
661  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
662  {
663  //The transmitter can accept another packet
664  osSetEvent(&interface->nicTxEvent);
665  }
666 
667  //Successful processing
668  return NO_ERROR;
669 }
670 
671 
672 /**
673  * @brief Receive a packet
674  * @param[in] interface Underlying network interface
675  * @return Error code
676  **/
677 
679 {
680  static uint8_t temp[MCIMX6UL_ETH2_RX_BUFFER_SIZE];
681  error_t error;
682  size_t n;
683 
684  //Make sure the current buffer is available for reading
685  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
686  {
687  //The frame should not span multiple buffers
688  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
689  {
690  //Check whether an error occurred
691  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
693  {
694  //Retrieve the length of the frame
695  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
696  //Limit the number of data to read
698 
699  //Copy data from the receive buffer
700  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
701 
702  //Pass the packet to the upper layer
703  nicProcessPacket(interface, temp, n);
704 
705  //Valid packet received
706  error = NO_ERROR;
707  }
708  else
709  {
710  //The received packet contains an error
711  error = ERROR_INVALID_PACKET;
712  }
713  }
714  else
715  {
716  //The packet is not valid
717  error = ERROR_INVALID_PACKET;
718  }
719 
720  //Clear BDU flag
721  rxBufferDesc[rxBufferIndex][4] = 0;
722 
723  //Check current index
724  if(rxBufferIndex < (MCIMX6UL_ETH2_RX_BUFFER_COUNT - 1))
725  {
726  //Give the ownership of the descriptor back to the DMA engine
727  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
728  //Point to the next buffer
729  rxBufferIndex++;
730  }
731  else
732  {
733  //Give the ownership of the descriptor back to the DMA engine
734  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
735  //Wrap around
736  rxBufferIndex = 0;
737  }
738 
739  //Instruct the DMA to poll the receive descriptor list
740  ENET2->RDAR = ENET_RDAR_RDAR_MASK;
741  }
742  else
743  {
744  //No more data in the receive buffer
745  error = ERROR_BUFFER_EMPTY;
746  }
747 
748  //Return status code
749  return error;
750 }
751 
752 
753 /**
754  * @brief Configure MAC address filtering
755  * @param[in] interface Underlying network interface
756  * @return Error code
757  **/
758 
760 {
761  uint_t i;
762  uint_t k;
763  uint32_t crc;
764  uint32_t unicastHashTable[2];
765  uint32_t multicastHashTable[2];
766  MacFilterEntry *entry;
767 
768  //Debug message
769  TRACE_DEBUG("Updating MAC filter...\r\n");
770 
771  //Clear hash table (unicast address filtering)
772  unicastHashTable[0] = 0;
773  unicastHashTable[1] = 0;
774 
775  //Clear hash table (multicast address filtering)
776  multicastHashTable[0] = 0;
777  multicastHashTable[1] = 0;
778 
779  //The MAC address filter contains the list of MAC addresses to accept
780  //when receiving an Ethernet frame
781  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
782  {
783  //Point to the current entry
784  entry = &interface->macAddrFilter[i];
785 
786  //Valid entry?
787  if(entry->refCount > 0)
788  {
789  //Compute CRC over the current MAC address
790  crc = mcimx6ulEth2CalcCrc(&entry->addr, sizeof(MacAddr));
791 
792  //The upper 6 bits in the CRC register are used to index the
793  //contents of the hash table
794  k = (crc >> 26) & 0x3F;
795 
796  //Multicast address?
797  if(macIsMulticastAddr(&entry->addr))
798  {
799  //Update the multicast hash table
800  multicastHashTable[k / 32] |= (1 << (k % 32));
801  }
802  else
803  {
804  //Update the unicast hash table
805  unicastHashTable[k / 32] |= (1 << (k % 32));
806  }
807  }
808  }
809 
810  //Write the hash table (unicast address filtering)
811  ENET2->IALR = unicastHashTable[0];
812  ENET2->IAUR = unicastHashTable[1];
813 
814  //Write the hash table (multicast address filtering)
815  ENET2->GALR = multicastHashTable[0];
816  ENET2->GAUR = multicastHashTable[1];
817 
818  //Debug message
819  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET2->IALR);
820  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET2->IAUR);
821  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET2->GALR);
822  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET2->GAUR);
823 
824  //Successful processing
825  return NO_ERROR;
826 }
827 
828 
829 /**
830  * @brief Adjust MAC configuration parameters for proper operation
831  * @param[in] interface Underlying network interface
832  * @return Error code
833  **/
834 
836 {
837  //Disable Ethernet MAC while modifying configuration registers
838  ENET2->ECR &= ~ENET_ECR_ETHEREN_MASK;
839 
840  //10BASE-T or 100BASE-TX operation mode?
841  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
842  {
843  //100 Mbps operation
844  ENET2->RCR &= ~ENET_RCR_RMII_10T_MASK;
845  }
846  else
847  {
848  //10 Mbps operation
849  ENET2->RCR |= ENET_RCR_RMII_10T_MASK;
850  }
851 
852  //Half-duplex or full-duplex mode?
853  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
854  {
855  //Full-duplex mode
856  ENET2->TCR |= ENET_TCR_FDEN_MASK;
857  //Receive path operates independently of transmit
858  ENET2->RCR &= ~ENET_RCR_DRT_MASK;
859  }
860  else
861  {
862  //Half-duplex mode
863  ENET2->TCR &= ~ENET_TCR_FDEN_MASK;
864  //Disable reception of frames while transmitting
865  ENET2->RCR |= ENET_RCR_DRT_MASK;
866  }
867 
868  //Reset buffer descriptors
869  mcimx6ulEth2InitBufferDesc(interface);
870 
871  //Re-enable Ethernet MAC
872  ENET2->ECR |= ENET_ECR_ETHEREN_MASK;
873  //Instruct the DMA to poll the receive descriptor list
874  ENET2->RDAR = ENET_RDAR_RDAR_MASK;
875 
876  //Successful processing
877  return NO_ERROR;
878 }
879 
880 
881 /**
882  * @brief Write PHY register
883  * @param[in] phyAddr PHY address
884  * @param[in] regAddr Register address
885  * @param[in] data Register value
886  **/
887 
888 void mcimx6ulEth2WritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
889 {
890  uint32_t value;
891 
892  //Set up a write operation
893  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
894  //PHY address
895  value |= ENET_MMFR_PA(phyAddr);
896  //Register address
897  value |= ENET_MMFR_RA(regAddr);
898  //Register value
899  value |= ENET_MMFR_DATA(data);
900 
901  //Clear MII interrupt flag
902  ENET1->EIR = ENET_EIR_MII_MASK;
903  //Start a write operation
904  ENET1->MMFR = value;
905  //Wait for the write to complete
906  while(!(ENET1->EIR & ENET_EIR_MII_MASK));
907 }
908 
909 
910 /**
911  * @brief Read PHY register
912  * @param[in] phyAddr PHY address
913  * @param[in] regAddr Register address
914  * @return Register value
915  **/
916 
917 uint16_t mcimx6ulEth2ReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
918 {
919  uint32_t value;
920 
921  //Set up a read operation
922  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
923  //PHY address
924  value |= ENET_MMFR_PA(phyAddr);
925  //Register address
926  value |= ENET_MMFR_RA(regAddr);
927 
928  //Clear MII interrupt flag
929  ENET1->EIR = ENET_EIR_MII_MASK;
930  //Start a read operation
931  ENET1->MMFR = value;
932  //Wait for the read to complete
933  while(!(ENET1->EIR & ENET_EIR_MII_MASK));
934 
935  //Return PHY register contents
936  return ENET1->MMFR & ENET_MMFR_DATA_MASK;
937 }
938 
939 
940 /**
941  * @brief CRC calculation
942  * @param[in] data Pointer to the data over which to calculate the CRC
943  * @param[in] length Number of bytes to process
944  * @return Resulting CRC value
945  **/
946 
947 uint32_t mcimx6ulEth2CalcCrc(const void *data, size_t length)
948 {
949  uint_t i;
950  uint_t j;
951 
952  //Point to the data over which to calculate the CRC
953  const uint8_t *p = (uint8_t *) data;
954  //CRC preset value
955  uint32_t crc = 0xFFFFFFFF;
956 
957  //Loop through data
958  for(i = 0; i < length; i++)
959  {
960  //Update CRC value
961  crc ^= p[i];
962  //The message is processed bit by bit
963  for(j = 0; j < 8; j++)
964  {
965  if(crc & 0x00000001)
966  crc = (crc >> 1) ^ 0xEDB88320;
967  else
968  crc = crc >> 1;
969  }
970  }
971 
972  //Return CRC value
973  return crc;
974 }
void mcimx6ulEth2EventHandler(NetInterface *interface)
i.MX6UL Ethernet MAC event handler
MacAddr addr
MAC address.
Definition: ethernet.h:219
#define ENET_RBD0_L
#define ENET_RBD0_W
void ENET2_DriverIRQHandler(uint32_t giccIar, void *userParam)
Ethernet MAC interrupt (ENET2 instance)
error_t mcimx6ulEth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define ENET_RBD0_OV
uint16_t mcimx6ulEth2ReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
TCP/IP stack core.
void mcimx6ulEth2DisableIrq(NetInterface *interface)
Disable interrupts.
Debugging facilities.
uint8_t p
Definition: ndp.h:297
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:107
void mcimx6ulEth2WritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define ENET_TBD2_INT
error_t mcimx6ulEth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define txBuffer
#define MCIMX6UL_ETH2_IRQ_PRIORITY
#define ENET_RBD0_LG
#define TRUE
Definition: os_port.h:50
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
void mcimx6ulEth2InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define ENET_RBD0_E
#define ENET_TBD0_R
#define ENET_RBD0_NO
#define ENET_TBD0_DATA_LENGTH
#define MCIMX6UL_ETH2_RX_BUFFER_COUNT
#define ENET_RBD0_CR
const NicDriver mcimx6ulEth2Driver
i.MX6UL Ethernet MAC driver
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
NIC driver.
Definition: nic.h:164
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MIN(a, b)
Definition: os_port.h:62
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void mcimx6ulEth2EnableIrq(NetInterface *interface)
Enable interrupts.
error_t mcimx6ulEth2ReceivePacket(NetInterface *interface)
Receive a packet.
#define TRACE_INFO(...)
Definition: debug.h:94
#define ENET_TBD0_TC
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
error_t mcimx6ulEth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
Ethernet interface.
Definition: nic.h:71
#define ENET_RBD2_INT
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:73
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:220
#define ENET_RBD0_DATA_LENGTH
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
unsigned int uint_t
Definition: compiler_port.h:45
__start_packed struct @112 MacAddr
MAC address.
void mcimx6ulEth2InitGpio(NetInterface *interface)
error_t mcimx6ulEth2Init(NetInterface *interface)
i.MX6UL Ethernet MAC initialization
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint8_t value[]
Definition: dtls_misc.h:143
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
void mcimx6ulEth2Tick(NetInterface *interface)
i.MX6UL Ethernet MAC timer handler
#define MCIMX6UL_ETH2_TX_BUFFER_COUNT
#define osExitIsr(flag)
#define osEnterIsr()
#define ENET_TBD0_L
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define ENET_TBD0_W
uint32_t mcimx6ulEth2CalcCrc(const void *data, size_t length)
CRC calculation.
#define ENET_RBD0_TR
#define MCIMX6UL_ETH2_TX_BUFFER_SIZE
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
#define MCIMX6UL_ETH2_RX_BUFFER_SIZE
MAC filter table entry.
Definition: ethernet.h:217
#define TRACE_DEBUG(...)
Definition: debug.h:106