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31 #ifndef _MCXN947_ETH_DRIVER_H
32 #define _MCXN947_ETH_DRIVER_H
38 #ifndef MCXN947_ETH_TX_BUFFER_COUNT
39 #define MCXN947_ETH_TX_BUFFER_COUNT 3
40 #elif (MCXN947_ETH_TX_BUFFER_COUNT < 1)
41 #error MCXN947_ETH_TX_BUFFER_COUNT parameter is not valid
45 #ifndef MCXN947_ETH_TX_BUFFER_SIZE
46 #define MCXN947_ETH_TX_BUFFER_SIZE 1536
47 #elif (MCXN947_ETH_TX_BUFFER_SIZE != 1536)
48 #error MCXN947_ETH_TX_BUFFER_SIZE parameter is not valid
52 #ifndef MCXN947_ETH_RX_BUFFER_COUNT
53 #define MCXN947_ETH_RX_BUFFER_COUNT 6
54 #elif (MCXN947_ETH_RX_BUFFER_COUNT < 1)
55 #error MCXN947_ETH_RX_BUFFER_COUNT parameter is not valid
59 #ifndef MCXN947_ETH_RX_BUFFER_SIZE
60 #define MCXN947_ETH_RX_BUFFER_SIZE 1536
61 #elif (MCXN947_ETH_RX_BUFFER_SIZE != 1536)
62 #error MCXN947_ETH_RX_BUFFER_SIZE parameter is not valid
66 #ifndef MCXN947_ETH_IRQ_PRIORITY_GROUPING
67 #define MCXN947_ETH_IRQ_PRIORITY_GROUPING 4
68 #elif (MCXN947_ETH_IRQ_PRIORITY_GROUPING < 0)
69 #error MCXN947_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
73 #ifndef MCXN947_ETH_IRQ_GROUP_PRIORITY
74 #define MCXN947_ETH_IRQ_GROUP_PRIORITY 6
75 #elif (MCXN947_ETH_IRQ_GROUP_PRIORITY < 0)
76 #error MCXN947_ETH_IRQ_GROUP_PRIORITY parameter is not valid
80 #ifndef MCXN947_ETH_IRQ_SUB_PRIORITY
81 #define MCXN947_ETH_IRQ_SUB_PRIORITY 0
82 #elif (MCXN947_ETH_IRQ_SUB_PRIORITY < 0)
83 #error MCXN947_ETH_IRQ_SUB_PRIORITY parameter is not valid
87 #define ENET_TDES0_BUF1AP 0xFFFFFFFF
88 #define ENET_TDES1_BUF2AP 0xFFFFFFFF
89 #define ENET_TDES2_IOC 0x80000000
90 #define ENET_TDES2_TTSE 0x40000000
91 #define ENET_TDES2_B2L 0x3FFF0000
92 #define ENET_TDES2_B1L 0x00003FFF
93 #define ENET_TDES3_OWN 0x80000000
94 #define ENET_TDES3_CTXT 0x40000000
95 #define ENET_TDES3_FD 0x20000000
96 #define ENET_TDES3_LD 0x10000000
97 #define ENET_TDES3_CPC 0x0C000000
98 #define ENET_TDES3_SLOTNUM 0x00780000
99 #define ENET_TDES3_CIC 0x00030000
100 #define ENET_TDES3_FL 0x00007FFF
103 #define ENET_TDES0_TTSL 0xFFFFFFFF
104 #define ENET_TDES1_TTSH 0xFFFFFFFF
105 #define ENET_TDES3_OWN 0x80000000
106 #define ENET_TDES3_CTXT 0x40000000
107 #define ENET_TDES3_FD 0x20000000
108 #define ENET_TDES3_LD 0x10000000
109 #define ENET_TDES3_TTSS 0x00020000
110 #define ENET_TDES3_ES 0x00008000
111 #define ENET_TDES3_JT 0x00004000
112 #define ENET_TDES3_FF 0x00002000
113 #define ENET_TDES3_PCE 0x00001000
114 #define ENET_TDES3_LOC 0x00000800
115 #define ENET_TDES3_NC 0x00000400
116 #define ENET_TDES3_LC 0x00000200
117 #define ENET_TDES3_EC 0x00000100
118 #define ENET_TDES3_CC 0x000000F0
119 #define ENET_TDES3_ED 0x00000008
120 #define ENET_TDES3_UF 0x00000004
121 #define ENET_TDES3_DB 0x00000002
122 #define ENET_TDES3_IHE 0x00000001
125 #define ENET_RDES0_BUF1AP 0xFFFFFFFF
126 #define ENET_RDES2_BUF2AP 0xFFFFFFFF
127 #define ENET_RDES3_OWN 0x80000000
128 #define ENET_RDES3_IOC 0x40000000
129 #define ENET_RDES3_BUF2V 0x02000000
130 #define ENET_RDES3_BUF1V 0x01000000
133 #define ENET_RDES0_IVT 0xFFFF0000
134 #define ENET_RDES0_OVT 0x0000FFFF
135 #define ENET_RDES1_OPC 0xFFFF0000
136 #define ENET_RDES1_TD 0x00008000
137 #define ENET_RDES1_TSA 0x00004000
138 #define ENET_RDES1_PV 0x00002000
139 #define ENET_RDES1_PFT 0x00001000
140 #define ENET_RDES1_PMT 0x00000F00
141 #define ENET_RDES1_IPCE 0x00000080
142 #define ENET_RDES1_IPCB 0x00000040
143 #define ENET_RDES1_IPV6 0x00000020
144 #define ENET_RDES1_IPV4 0x00000010
145 #define ENET_RDES1_IPHE 0x00000008
146 #define ENET_RDES1_PT 0x00000007
147 #define ENET_RDES2_MADRM 0x07F80000
148 #define ENET_RDES2_DAF 0x00020000
149 #define ENET_RDES2_SAF 0x00010000
150 #define ENET_RDES3_OWN 0x80000000
151 #define ENET_RDES3_CTXT 0x40000000
152 #define ENET_RDES3_FD 0x20000000
153 #define ENET_RDES3_LD 0x10000000
154 #define ENET_RDES3_RS2V 0x08000000
155 #define ENET_RDES3_RS1V 0x04000000
156 #define ENET_RDES3_RS0V 0x02000000
157 #define ENET_RDES3_CE 0x01000000
158 #define ENET_RDES3_GP 0x00800000
159 #define ENET_RDES3_RWT 0x00400000
160 #define ENET_RDES3_OE 0x00200000
161 #define ENET_RDES3_RE 0x00100000
162 #define ENET_RDES3_DE 0x00080000
163 #define ENET_RDES3_LT 0x00070000
164 #define ENET_RDES3_ES 0x00008000
165 #define ENET_RDES3_PL 0x00007FFF
error_t mcxn947EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Structure describing a buffer that spans multiple chunks.
void mcxn947EthDisableIrq(NetInterface *interface)
Disable interrupts.
void mcxn947EthInitGpio(NetInterface *interface)
GPIO configuration.
void mcxn947EthEventHandler(NetInterface *interface)
MCX N947 Ethernet MAC event handler.
void mcxn947EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t mcxn947EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void mcxn947EthTick(NetInterface *interface)
MCX N947 Ethernet MAC timer handler.
void mcxn947EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t mcxn947EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Network interface controller abstraction layer.
uint16_t mcxn947EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t mcxn947EthInit(NetInterface *interface)
MCX N947 Ethernet MAC initialization.
error_t mcxn947EthReceivePacket(NetInterface *interface)
Receive a packet.
void mcxn947EthEnableIrq(NetInterface *interface)
Enable interrupts.
const NicDriver mcxn947EthDriver
MCX N947 Ethernet MAC driver.