mimxrt1052_eth_driver.h
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1 /**
2  * @file mimxrt1052_eth_driver.h
3  * @brief i.MX RT1050 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _MIMXRT1052_ETH_DRIVER_H
30 #define _MIMXRT1052_ETH_DRIVER_H
31 
32 //Number of TX buffers
33 #ifndef MIMXRT1052_ETH_TX_BUFFER_COUNT
34  #define MIMXRT1052_ETH_TX_BUFFER_COUNT 8
35 #elif (MIMXRT1052_ETH_TX_BUFFER_COUNT < 1)
36  #error MIMXRT1052_ETH_TX_BUFFER_COUNT parameter is not valid
37 #endif
38 
39 //TX buffer size
40 #ifndef MIMXRT1052_ETH_TX_BUFFER_SIZE
41  #define MIMXRT1052_ETH_TX_BUFFER_SIZE 1536
42 #elif (MIMXRT1052_ETH_TX_BUFFER_SIZE != 1536)
43  #error MIMXRT1052_ETH_TX_BUFFER_SIZE parameter is not valid
44 #endif
45 
46 //Number of RX buffers
47 #ifndef MIMXRT1052_ETH_RX_BUFFER_COUNT
48  #define MIMXRT1052_ETH_RX_BUFFER_COUNT 8
49 #elif (MIMXRT1052_ETH_RX_BUFFER_COUNT < 1)
50  #error MIMXRT1052_ETH_RX_BUFFER_COUNT parameter is not valid
51 #endif
52 
53 //RX buffer size
54 #ifndef MIMXRT1052_ETH_RX_BUFFER_SIZE
55  #define MIMXRT1052_ETH_RX_BUFFER_SIZE 1536
56 #elif (MIMXRT1052_ETH_RX_BUFFER_SIZE != 1536)
57  #error MIMXRT1052_ETH_RX_BUFFER_SIZE parameter is not valid
58 #endif
59 
60 //Interrupt priority grouping
61 #ifndef MIMXRT1052_ETH_IRQ_PRIORITY_GROUPING
62  #define MIMXRT1052_ETH_IRQ_PRIORITY_GROUPING 3
63 #elif (MIMXRT1052_ETH_IRQ_PRIORITY_GROUPING < 0)
64  #error MIMXRT1052_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
65 #endif
66 
67 //Ethernet interrupt group priority
68 #ifndef MIMXRT1052_ETH_IRQ_GROUP_PRIORITY
69  #define MIMXRT1052_ETH_IRQ_GROUP_PRIORITY 12
70 #elif (MIMXRT1052_ETH_IRQ_GROUP_PRIORITY < 0)
71  #error MIMXRT1052_ETH_IRQ_GROUP_PRIORITY parameter is not valid
72 #endif
73 
74 //Ethernet interrupt subpriority
75 #ifndef MIMXRT1052_ETH_IRQ_SUB_PRIORITY
76  #define MIMXRT1052_ETH_IRQ_SUB_PRIORITY 0
77 #elif (MIMXRT1052_ETH_IRQ_SUB_PRIORITY < 0)
78  #error MIMXRT1052_ETH_IRQ_SUB_PRIORITY parameter is not valid
79 #endif
80 
81 //Enhanced transmit buffer descriptor
82 #define ENET_TBD0_R 0x80000000
83 #define ENET_TBD0_TO1 0x40000000
84 #define ENET_TBD0_W 0x20000000
85 #define ENET_TBD0_TO2 0x10000000
86 #define ENET_TBD0_L 0x08000000
87 #define ENET_TBD0_TC 0x04000000
88 #define ENET_TBD0_DATA_LENGTH 0x0000FFFF
89 #define ENET_TBD1_DATA_POINTER 0xFFFFFFFF
90 #define ENET_TBD2_INT 0x40000000
91 #define ENET_TBD2_TS 0x20000000
92 #define ENET_TBD2_PINS 0x10000000
93 #define ENET_TBD2_IINS 0x08000000
94 #define ENET_TBD2_TXE 0x00008000
95 #define ENET_TBD2_UE 0x00002000
96 #define ENET_TBD2_EE 0x00001000
97 #define ENET_TBD2_FE 0x00000800
98 #define ENET_TBD2_LCE 0x00000400
99 #define ENET_TBD2_OE 0x00000200
100 #define ENET_TBD2_TSE 0x00000100
101 #define ENET_TBD4_BDU 0x80000000
102 #define ENET_TBD5_TIMESTAMP 0xFFFFFFFF
103 
104 //Enhanced receive buffer descriptor
105 #define ENET_RBD0_E 0x80000000
106 #define ENET_RBD0_RO1 0x40000000
107 #define ENET_RBD0_W 0x20000000
108 #define ENET_RBD0_RO2 0x10000000
109 #define ENET_RBD0_L 0x08000000
110 #define ENET_RBD0_M 0x01000000
111 #define ENET_RBD0_BC 0x00800000
112 #define ENET_RBD0_MC 0x00400000
113 #define ENET_RBD0_LG 0x00200000
114 #define ENET_RBD0_NO 0x00100000
115 #define ENET_RBD0_CR 0x00040000
116 #define ENET_RBD0_OV 0x00020000
117 #define ENET_RBD0_TR 0x00010000
118 #define ENET_RBD0_DATA_LENGTH 0x0000FFFF
119 #define ENET_RBD1_DATA_POINTER 0xFFFFFFFF
120 #define ENET_RBD2_ME 0x80000000
121 #define ENET_RBD2_PE 0x04000000
122 #define ENET_RBD2_CE 0x02000000
123 #define ENET_RBD2_UC 0x01000000
124 #define ENET_RBD2_INT 0x00800000
125 #define ENET_RBD2_VPCP 0x0000E000
126 #define ENET_RBD2_ICE 0x00000020
127 #define ENET_RBD2_PCR 0x00000010
128 #define ENET_RBD2_VLAN 0x00000004
129 #define ENET_RBD2_IPV6 0x00000002
130 #define ENET_RBD2_FRAG 0x00000001
131 #define ENET_RBD3_HEADER_LENGTH 0xF8000000
132 #define ENET_RBD3_PROTOCOL_TYPE 0x00FF0000
133 #define ENET_RBD3_PAYLOAD_CHECKSUM 0x0000FFFF
134 #define ENET_RBD4_BDU 0x80000000
135 #define ENET_RBD5_TIMESTAMP 0xFFFFFFFF
136 
137 //C++ guard
138 #ifdef __cplusplus
139  extern "C" {
140 #endif
141 
142 //i.MX RT1052 Ethernet MAC driver
143 extern const NicDriver mimxrt1052EthDriver;
144 
145 //i.MX RT1052 Ethernet MAC related functions
147 void mimxrt1052EthInitGpio(NetInterface *interface);
149 
150 void mimxrt1052EthTick(NetInterface *interface);
151 
152 void mimxrt1052EthEnableIrq(NetInterface *interface);
153 void mimxrt1052EthDisableIrq(NetInterface *interface);
154 void mimxrt1052EthEventHandler(NetInterface *interface);
155 
157  const NetBuffer *buffer, size_t offset);
158 
160 
163 
164 void mimxrt1052EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
165 uint16_t mimxrt1052EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
166 
167 uint32_t mimxrt1052EthCalcCrc(const void *data, size_t length);
168 
169 //C++ guard
170 #ifdef __cplusplus
171  }
172 #endif
173 
174 #endif
void mimxrt1052EthEventHandler(NetInterface *interface)
i.MX RT1052 Ethernet MAC event handler
void mimxrt1052EthInitGpio(NetInterface *interface)
void mimxrt1052EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t mimxrt1052EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void mimxrt1052EthEnableIrq(NetInterface *interface)
Enable interrupts.
void mimxrt1052EthTick(NetInterface *interface)
i.MX RT1052 Ethernet MAC timer handler
error_t mimxrt1052EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t mimxrt1052EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void mimxrt1052EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
const NicDriver mimxrt1052EthDriver
i.MX RT1052 Ethernet MAC driver
NIC driver.
Definition: nic.h:161
error_t mimxrt1052EthInit(NetInterface *interface)
i.MX RT1052 Ethernet MAC initialization
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
uint32_t mimxrt1052EthCalcCrc(const void *data, size_t length)
CRC calculation.
uint16_t regAddr
error_t
Error codes.
Definition: error.h:40
void mimxrt1052EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t length
Definition: dtls_misc.h:140
error_t mimxrt1052EthReceivePacket(NetInterface *interface)
Receive a packet.
error_t mimxrt1052EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.