mimxrt1050_eth_driver.c
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1 /**
2  * @file mimxrt1050_eth_driver.c
3  * @brief i.MX RT1050 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
50 #pragma location = ".ram_no_cache"
52 //RX buffer
53 #pragma data_alignment = 16
54 #pragma location = ".ram_no_cache"
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 #pragma location = ".ram_no_cache"
59 static uint32_t txBufferDesc[MIMXRT1050_ETH_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 16
62 #pragma location = ".ram_no_cache"
63 static uint32_t rxBufferDesc[MIMXRT1050_ETH_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(16), __section__(".ram_no_cache")));
71 //RX buffer
73  __attribute__((aligned(16), __section__(".ram_no_cache")));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MIMXRT1050_ETH_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(16), __section__(".ram_no_cache")));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MIMXRT1050_ETH_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(16), __section__(".ram_no_cache")));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX RT1050 Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX RT1050 Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX RT1050 Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mimxrt1050EthInitGpio(interface);
136 
137  //Reset ENET module
138  ENET->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while(ENET->ECR & ENET_ECR_RESET_MASK);
141 
142  //Receive control register
143  ENET->RCR = ENET_RCR_MAX_FL(MIMXRT1050_ETH_RX_BUFFER_SIZE) |
144  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
145 
146  //Transmit control register
147  ENET->TCR = 0;
148  //Configure MDC clock frequency
149  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
150 
151  //PHY transceiver initialization
152  error = interface->phyDriver->init(interface);
153  //Failed to initialize PHY transceiver?
154  if(error)
155  return error;
156 
157  //Set the MAC address of the station (upper 16 bits)
158  value = interface->macAddr.b[5];
159  value |= (interface->macAddr.b[4] << 8);
160  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
161 
162  //Set the MAC address of the station (lower 32 bits)
163  value = interface->macAddr.b[3];
164  value |= (interface->macAddr.b[2] << 8);
165  value |= (interface->macAddr.b[1] << 16);
166  value |= (interface->macAddr.b[0] << 24);
167  ENET->PALR = ENET_PALR_PADDR1(value);
168 
169  //Hash table for unicast address filtering
170  ENET->IALR = 0;
171  ENET->IAUR = 0;
172  //Hash table for multicast address filtering
173  ENET->GALR = 0;
174  ENET->GAUR = 0;
175 
176  //Disable transmit accelerator functions
177  ENET->TACC = 0;
178  //Disable receive accelerator functions
179  ENET->RACC = 0;
180 
181  //Use enhanced buffer descriptors
182  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
183  //Clear MIC counters
184  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
185 
186  //Initialize buffer descriptors
187  mimxrt1050EthInitBufferDesc(interface);
188 
189  //Clear any pending interrupts
190  ENET->EIR = 0xFFFFFFFF;
191  //Enable desired interrupts
192  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
193 
194  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
195  NVIC_SetPriorityGrouping(MIMXRT1050_ETH_IRQ_PRIORITY_GROUPING);
196 
197  //Configure ENET interrupt priority
198  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1050_ETH_IRQ_PRIORITY_GROUPING,
200 
201  //Enable Ethernet MAC
202  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
203  //Instruct the DMA to poll the receive descriptor list
204  ENET->RDAR = ENET_RDAR_RDAR_MASK;
205 
206  //Accept any packets from the upper layer
207  osSetEvent(&interface->nicTxEvent);
208 
209  //Successful initialization
210  return NO_ERROR;
211 }
212 
213 
214 //MIMXRT1050-EVKA or MIMXRT1050-EVKB evaluation board?
215 #if defined(USE_MIMXRT1050_EVKA) || defined(USE_MIMXRT1050_EVKB)
216 
217 /**
218  * @brief GPIO configuration
219  * @param[in] interface Underlying network interface
220  **/
221 
222 void mimxrt1050EthInitGpio(NetInterface *interface)
223 {
224  gpio_pin_config_t pinConfig;
225  clock_enet_pll_config_t pllConfig;
226 
227 #if (defined(CPU_MIMXRT1052CVL5A) || defined(CPU_MIMXRT1052DVL6A))
228  //Configure ENET PLL (50MHz)
229  pllConfig.enableClkOutput0 = true;
230  pllConfig.enableClkOutput1 = false;
231  pllConfig.enableClkOutput2 = false;
232  pllConfig.loopDivider0 = 1;
233  pllConfig.loopDivider1 = 0;
234  CLOCK_InitEnetPll(&pllConfig);
235 #else
236  //Configure ENET PLL (50MHz)
237  pllConfig.enableClkOutput = true;
238  pllConfig.enableClkOutput25M = false;
239  pllConfig.loopDivider = 1;
240  pllConfig.src = 0;
241  CLOCK_InitEnetPll(&pllConfig);
242 #endif
243 
244  //Enable ENET1_TX_CLK output driver
245  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
246 
247  //Enable IOMUXC clock
248  CLOCK_EnableClock(kCLOCK_Iomuxc);
249 
250  //Configure GPIO_B1_04 pin as ENET_RX_DATA00
251  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
252 
253  //Set GPIO_B1_04 pad properties
254  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00,
255  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
256  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
257  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
258  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
259  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
260  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
261  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
262  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
263 
264  //Configure GPIO_B1_05 pin as ENET_RX_DATA01
265  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
266 
267  //Set GPIO_B1_05 pad properties
268  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01,
269  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
270  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
271  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
272  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
273  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
274  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
275  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
276  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
277 
278  //Configure GPIO_B1_06 pin as ENET_RX_EN
279  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
280 
281  //Set GPIO_B1_06 pad properties
282  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN,
283  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
284  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
285  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
286  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
287  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
288  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
289  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
290  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
291 
292  //Configure GPIO_B1_07 pin as ENET_TX_DATA00
293  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
294 
295  //Set GPIO_B1_07 pad properties
296  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00,
297  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
298  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
299  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
300  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
301  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
302  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
303  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
304  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
305 
306  //Configure GPIO_B1_08 pin as ENET_TX_DATA01
307  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
308 
309  //Set GPIO_B1_08 pad properties
310  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01,
311  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
312  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
313  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
314  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
315  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
316  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
317  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
318  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
319 
320  //Configure GPIO_B1_09 pin as ENET_TX_EN
321  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
322 
323  //Set GPIO_B1_09 pad properties
324  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN,
325  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
326  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
327  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
328  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
329  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
330  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
331  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
332  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
333 
334  //Configure GPIO_B1_10 pin as ENET_REF_CLK
335  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
336 
337  //Set GPIO_B1_10 pad properties
338  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK,
339  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
340  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
341  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
342  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
343  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
344  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
345  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
346  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
347 
348  //Configure GPIO_B1_11 pin as ENET_RX_ER
349  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
350 
351  //Set GPIO_B1_11 pad properties
352  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER,
353  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
354  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
355  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
356  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
357  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
358  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
359  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
360  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
361 
362  //Configure GPIO_EMC_40 pin as ENET_MDC
363  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
364 
365  //Set GPIO_EMC_40 pad properties
366  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC,
367  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
368  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
369  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
370  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
371  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
372  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
373  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
374  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
375 
376  //Configure GPIO_EMC_41 pin as ENET_MDIO
377  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
378 
379  //Set GPIO_EMC_41 pad properties
380  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO,
381  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
382  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
383  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
384  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
385  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
386  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
387  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
388  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
389 
390  //Configure GPIO_AD_B0_09 pin as GPIO1_IO09
391  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
392 
393  //Set GPIO_AD_B0_09 pad properties
394  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
395  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
396  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
397  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
398  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
399  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
400  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
401  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
402  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
403 
404  //Configure GPIO_AD_B0_10 pin as GPIO1_IO10
405  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0);
406 
407  //Set GPIO_AD_B0_10 pad properties
408  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,
409  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
410  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
411  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
412  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
413  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
414  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
415  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
416  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
417 
418  //Configure ENET_RST as an output
419  pinConfig.direction = kGPIO_DigitalOutput;
420  pinConfig.outputLogic = 0;
421  pinConfig.interruptMode = kGPIO_NoIntmode;
422  GPIO_PinInit(GPIO1, 9, &pinConfig);
423 
424  //Configure ENET_INT as an input
425  pinConfig.direction = kGPIO_DigitalInput;
426  pinConfig.outputLogic = 0;
427  pinConfig.interruptMode = kGPIO_NoIntmode;
428  GPIO_PinInit(GPIO1, 10, &pinConfig);
429 
430  //Reset PHY transceiver (hard reset)
431  GPIO_PinWrite(GPIO1, 9, 0);
432  sleep(10);
433  GPIO_PinWrite(GPIO1, 9, 1);
434  sleep(10);
435 }
436 
437 #endif
438 
439 
440 /**
441  * @brief Initialize buffer descriptors
442  * @param[in] interface Underlying network interface
443  **/
444 
446 {
447  uint_t i;
448  uint32_t address;
449 
450  //Clear TX and RX buffer descriptors
451  memset(txBufferDesc, 0, sizeof(txBufferDesc));
452  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
453 
454  //Initialize TX buffer descriptors
455  for(i = 0; i < MIMXRT1050_ETH_TX_BUFFER_COUNT; i++)
456  {
457  //Calculate the address of the current TX buffer
458  address = (uint32_t) txBuffer[i];
459  //Transmit buffer address
460  txBufferDesc[i][1] = address;
461  //Generate interrupts
462  txBufferDesc[i][2] = ENET_TBD2_INT;
463  }
464 
465  //Mark the last descriptor entry with the wrap flag
466  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
467  //Initialize TX buffer index
468  txBufferIndex = 0;
469 
470  //Initialize RX buffer descriptors
471  for(i = 0; i < MIMXRT1050_ETH_RX_BUFFER_COUNT; i++)
472  {
473  //Calculate the address of the current RX buffer
474  address = (uint32_t) rxBuffer[i];
475  //The descriptor is initially owned by the DMA
476  rxBufferDesc[i][0] = ENET_RBD0_E;
477  //Receive buffer address
478  rxBufferDesc[i][1] = address;
479  //Generate interrupts
480  rxBufferDesc[i][2] = ENET_RBD2_INT;
481  }
482 
483  //Mark the last descriptor entry with the wrap flag
484  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
485  //Initialize RX buffer index
486  rxBufferIndex = 0;
487 
488  //Start location of the TX descriptor list
489  ENET->TDSR = (uint32_t) txBufferDesc;
490  //Start location of the RX descriptor list
491  ENET->RDSR = (uint32_t) rxBufferDesc;
492  //Maximum receive buffer size
493  ENET->MRBR = MIMXRT1050_ETH_RX_BUFFER_SIZE;
494 }
495 
496 
497 /**
498  * @brief i.MX RT1050 Ethernet MAC timer handler
499  *
500  * This routine is periodically called by the TCP/IP stack to
501  * handle periodic operations such as polling the link state
502  *
503  * @param[in] interface Underlying network interface
504  **/
505 
507 {
508  //Handle periodic operations
509  interface->phyDriver->tick(interface);
510 }
511 
512 
513 /**
514  * @brief Enable interrupts
515  * @param[in] interface Underlying network interface
516  **/
517 
519 {
520  //Enable Ethernet MAC interrupts
521  NVIC_EnableIRQ(ENET_IRQn);
522  //Enable Ethernet PHY interrupts
523  interface->phyDriver->enableIrq(interface);
524 }
525 
526 
527 /**
528  * @brief Disable interrupts
529  * @param[in] interface Underlying network interface
530  **/
531 
533 {
534  //Disable Ethernet MAC interrupts
535  NVIC_DisableIRQ(ENET_IRQn);
536  //Disable Ethernet PHY interrupts
537  interface->phyDriver->disableIrq(interface);
538 }
539 
540 
541 /**
542  * @brief Ethernet MAC interrupt
543  **/
544 
545 void ENET_IRQHandler(void)
546 {
547  bool_t flag;
548  uint32_t events;
549 
550  //Enter interrupt service routine
551  osEnterIsr();
552 
553  //This flag will be set if a higher priority task must be woken
554  flag = FALSE;
555  //Read interrupt event register
556  events = ENET->EIR;
557 
558  //A packet has been transmitted?
559  if(events & ENET_EIR_TXF_MASK)
560  {
561  //Clear TXF interrupt flag
562  ENET->EIR = ENET_EIR_TXF_MASK;
563 
564  //Check whether the TX buffer is available for writing
565  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
566  {
567  //Notify the TCP/IP stack that the transmitter is ready to send
568  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
569  }
570 
571  //Instruct the DMA to poll the transmit descriptor list
572  ENET->TDAR = ENET_TDAR_TDAR_MASK;
573  }
574 
575  //A packet has been received?
576  if(events & ENET_EIR_RXF_MASK)
577  {
578  //Disable RXF interrupt
579  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
580 
581  //Set event flag
582  nicDriverInterface->nicEvent = TRUE;
583  //Notify the TCP/IP stack of the event
584  flag = osSetEventFromIsr(&netEvent);
585  }
586 
587  //System bus error?
588  if(events & ENET_EIR_EBERR_MASK)
589  {
590  //Disable EBERR interrupt
591  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
592 
593  //Set event flag
594  nicDriverInterface->nicEvent = TRUE;
595  //Notify the TCP/IP stack of the event
596  flag |= osSetEventFromIsr(&netEvent);
597  }
598 
599  //Leave interrupt service routine
600  osExitIsr(flag);
601 }
602 
603 
604 /**
605  * @brief i.MX RT1050 Ethernet MAC event handler
606  * @param[in] interface Underlying network interface
607  **/
608 
610 {
611  error_t error;
612  uint32_t status;
613 
614  //Read interrupt event register
615  status = ENET->EIR;
616 
617  //Packet received?
618  if(status & ENET_EIR_RXF_MASK)
619  {
620  //Clear RXF interrupt flag
621  ENET->EIR = ENET_EIR_RXF_MASK;
622 
623  //Process all pending packets
624  do
625  {
626  //Read incoming packet
627  error = mimxrt1050EthReceivePacket(interface);
628 
629  //No more data in the receive buffer?
630  } while(error != ERROR_BUFFER_EMPTY);
631  }
632 
633  //System bus error?
634  if(status & ENET_EIR_EBERR_MASK)
635  {
636  //Clear EBERR interrupt flag
637  ENET->EIR = ENET_EIR_EBERR_MASK;
638 
639  //Disable Ethernet MAC
640  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
641  //Reset buffer descriptors
642  mimxrt1050EthInitBufferDesc(interface);
643  //Resume normal operation
644  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
645  //Instruct the DMA to poll the receive descriptor list
646  ENET->RDAR = ENET_RDAR_RDAR_MASK;
647  }
648 
649  //Re-enable Ethernet MAC interrupts
650  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
651 }
652 
653 
654 /**
655  * @brief Send a packet
656  * @param[in] interface Underlying network interface
657  * @param[in] buffer Multi-part buffer containing the data to send
658  * @param[in] offset Offset to the first data byte
659  * @return Error code
660  **/
661 
663  const NetBuffer *buffer, size_t offset)
664 {
665  static uint8_t temp[MIMXRT1050_ETH_TX_BUFFER_SIZE];
666  size_t length;
667 
668  //Retrieve the length of the packet
669  length = netBufferGetLength(buffer) - offset;
670 
671  //Check the frame length
673  {
674  //The transmitter can accept another packet
675  osSetEvent(&interface->nicTxEvent);
676  //Report an error
677  return ERROR_INVALID_LENGTH;
678  }
679 
680  //Make sure the current buffer is available for writing
681  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
682  return ERROR_FAILURE;
683 
684  //Copy user data to the transmit buffer
685  netBufferRead(temp, buffer, offset, length);
686  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
687 
688  //Clear BDU flag
689  txBufferDesc[txBufferIndex][4] = 0;
690 
691  //Check current index
692  if(txBufferIndex < (MIMXRT1050_ETH_TX_BUFFER_COUNT - 1))
693  {
694  //Give the ownership of the descriptor to the DMA engine
695  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
697 
698  //Point to the next buffer
699  txBufferIndex++;
700  }
701  else
702  {
703  //Give the ownership of the descriptor to the DMA engine
704  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
706 
707  //Wrap around
708  txBufferIndex = 0;
709  }
710 
711  //Data synchronization barrier
712  __DSB();
713 
714  //Instruct the DMA to poll the transmit descriptor list
715  ENET->TDAR = ENET_TDAR_TDAR_MASK;
716 
717  //Check whether the next buffer is available for writing
718  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
719  {
720  //The transmitter can accept another packet
721  osSetEvent(&interface->nicTxEvent);
722  }
723 
724  //Successful processing
725  return NO_ERROR;
726 }
727 
728 
729 /**
730  * @brief Receive a packet
731  * @param[in] interface Underlying network interface
732  * @return Error code
733  **/
734 
736 {
737  static uint8_t temp[MIMXRT1050_ETH_RX_BUFFER_SIZE];
738  error_t error;
739  size_t n;
740 
741  //Make sure the current buffer is available for reading
742  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
743  {
744  //The frame should not span multiple buffers
745  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
746  {
747  //Check whether an error occurred
748  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
750  {
751  //Retrieve the length of the frame
752  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
753  //Limit the number of data to read
755 
756  //Copy data from the receive buffer
757  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
758 
759  //Pass the packet to the upper layer
760  nicProcessPacket(interface, temp, n);
761 
762  //Valid packet received
763  error = NO_ERROR;
764  }
765  else
766  {
767  //The received packet contains an error
768  error = ERROR_INVALID_PACKET;
769  }
770  }
771  else
772  {
773  //The packet is not valid
774  error = ERROR_INVALID_PACKET;
775  }
776 
777  //Clear BDU flag
778  rxBufferDesc[rxBufferIndex][4] = 0;
779 
780  //Check current index
781  if(rxBufferIndex < (MIMXRT1050_ETH_RX_BUFFER_COUNT - 1))
782  {
783  //Give the ownership of the descriptor back to the DMA engine
784  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
785  //Point to the next buffer
786  rxBufferIndex++;
787  }
788  else
789  {
790  //Give the ownership of the descriptor back to the DMA engine
791  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
792  //Wrap around
793  rxBufferIndex = 0;
794  }
795 
796  //Instruct the DMA to poll the receive descriptor list
797  ENET->RDAR = ENET_RDAR_RDAR_MASK;
798  }
799  else
800  {
801  //No more data in the receive buffer
802  error = ERROR_BUFFER_EMPTY;
803  }
804 
805  //Return status code
806  return error;
807 }
808 
809 
810 /**
811  * @brief Configure MAC address filtering
812  * @param[in] interface Underlying network interface
813  * @return Error code
814  **/
815 
817 {
818  uint_t i;
819  uint_t k;
820  uint32_t crc;
821  uint32_t unicastHashTable[2];
822  uint32_t multicastHashTable[2];
823  MacFilterEntry *entry;
824 
825  //Debug message
826  TRACE_DEBUG("Updating MAC filter...\r\n");
827 
828  //Clear hash table (unicast address filtering)
829  unicastHashTable[0] = 0;
830  unicastHashTable[1] = 0;
831 
832  //Clear hash table (multicast address filtering)
833  multicastHashTable[0] = 0;
834  multicastHashTable[1] = 0;
835 
836  //The MAC address filter contains the list of MAC addresses to accept
837  //when receiving an Ethernet frame
838  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
839  {
840  //Point to the current entry
841  entry = &interface->macAddrFilter[i];
842 
843  //Valid entry?
844  if(entry->refCount > 0)
845  {
846  //Compute CRC over the current MAC address
847  crc = mimxrt1050EthCalcCrc(&entry->addr, sizeof(MacAddr));
848 
849  //The upper 6 bits in the CRC register are used to index the
850  //contents of the hash table
851  k = (crc >> 26) & 0x3F;
852 
853  //Multicast address?
854  if(macIsMulticastAddr(&entry->addr))
855  {
856  //Update the multicast hash table
857  multicastHashTable[k / 32] |= (1 << (k % 32));
858  }
859  else
860  {
861  //Update the unicast hash table
862  unicastHashTable[k / 32] |= (1 << (k % 32));
863  }
864  }
865  }
866 
867  //Write the hash table (unicast address filtering)
868  ENET->IALR = unicastHashTable[0];
869  ENET->IAUR = unicastHashTable[1];
870 
871  //Write the hash table (multicast address filtering)
872  ENET->GALR = multicastHashTable[0];
873  ENET->GAUR = multicastHashTable[1];
874 
875  //Debug message
876  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
877  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
878  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
879  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
880 
881  //Successful processing
882  return NO_ERROR;
883 }
884 
885 
886 /**
887  * @brief Adjust MAC configuration parameters for proper operation
888  * @param[in] interface Underlying network interface
889  * @return Error code
890  **/
891 
893 {
894  //Disable Ethernet MAC while modifying configuration registers
895  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
896 
897  //10BASE-T or 100BASE-TX operation mode?
898  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
899  {
900  //100 Mbps operation
901  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
902  }
903  else
904  {
905  //10 Mbps operation
906  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
907  }
908 
909  //Half-duplex or full-duplex mode?
910  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
911  {
912  //Full-duplex mode
913  ENET->TCR |= ENET_TCR_FDEN_MASK;
914  //Receive path operates independently of transmit
915  ENET->RCR &= ~ENET_RCR_DRT_MASK;
916  }
917  else
918  {
919  //Half-duplex mode
920  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
921  //Disable reception of frames while transmitting
922  ENET->RCR |= ENET_RCR_DRT_MASK;
923  }
924 
925  //Reset buffer descriptors
926  mimxrt1050EthInitBufferDesc(interface);
927 
928  //Re-enable Ethernet MAC
929  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
930  //Instruct the DMA to poll the receive descriptor list
931  ENET->RDAR = ENET_RDAR_RDAR_MASK;
932 
933  //Successful processing
934  return NO_ERROR;
935 }
936 
937 
938 /**
939  * @brief Write PHY register
940  * @param[in] phyAddr PHY address
941  * @param[in] regAddr Register address
942  * @param[in] data Register value
943  **/
944 
945 void mimxrt1050EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
946 {
947  uint32_t value;
948 
949  //Set up a write operation
950  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
951  //PHY address
952  value |= ENET_MMFR_PA(phyAddr);
953  //Register address
954  value |= ENET_MMFR_RA(regAddr);
955  //Register value
956  value |= ENET_MMFR_DATA(data);
957 
958  //Clear MII interrupt flag
959  ENET->EIR = ENET_EIR_MII_MASK;
960  //Start a write operation
961  ENET->MMFR = value;
962  //Wait for the write to complete
963  while(!(ENET->EIR & ENET_EIR_MII_MASK));
964 }
965 
966 
967 /**
968  * @brief Read PHY register
969  * @param[in] phyAddr PHY address
970  * @param[in] regAddr Register address
971  * @return Register value
972  **/
973 
974 uint16_t mimxrt1050EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
975 {
976  uint32_t value;
977 
978  //Set up a read operation
979  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
980  //PHY address
981  value |= ENET_MMFR_PA(phyAddr);
982  //Register address
983  value |= ENET_MMFR_RA(regAddr);
984 
985  //Clear MII interrupt flag
986  ENET->EIR = ENET_EIR_MII_MASK;
987  //Start a read operation
988  ENET->MMFR = value;
989  //Wait for the read to complete
990  while(!(ENET->EIR & ENET_EIR_MII_MASK));
991 
992  //Return PHY register contents
993  return ENET->MMFR & ENET_MMFR_DATA_MASK;
994 }
995 
996 
997 /**
998  * @brief CRC calculation
999  * @param[in] data Pointer to the data over which to calculate the CRC
1000  * @param[in] length Number of bytes to process
1001  * @return Resulting CRC value
1002  **/
1003 
1004 uint32_t mimxrt1050EthCalcCrc(const void *data, size_t length)
1005 {
1006  uint_t i;
1007  uint_t j;
1008 
1009  //Point to the data over which to calculate the CRC
1010  const uint8_t *p = (uint8_t *) data;
1011  //CRC preset value
1012  uint32_t crc = 0xFFFFFFFF;
1013 
1014  //Loop through data
1015  for(i = 0; i < length; i++)
1016  {
1017  //Update CRC value
1018  crc ^= p[i];
1019  //The message is processed bit by bit
1020  for(j = 0; j < 8; j++)
1021  {
1022  if(crc & 0x00000001)
1023  crc = (crc >> 1) ^ 0xEDB88320;
1024  else
1025  crc = crc >> 1;
1026  }
1027  }
1028 
1029  //Return CRC value
1030  return crc;
1031 }
void mimxrt1050EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void mimxrt1050EthEnableIrq(NetInterface *interface)
Enable interrupts.
MacAddr addr
MAC address.
Definition: ethernet.h:219
#define ENET_RBD0_L
#define ENET_RBD0_W
#define ENET_RBD0_OV
void mimxrt1050EthDisableIrq(NetInterface *interface)
Disable interrupts.
TCP/IP stack core.
error_t mimxrt1050EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Debugging facilities.
uint8_t p
Definition: ndp.h:297
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
uint16_t mimxrt1050EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:107
#define ENET_TBD2_INT
#define txBuffer
void mimxrt1050EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
error_t mimxrt1050EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define sleep(delay)
Definition: os_port.h:128
uint32_t mimxrt1050EthCalcCrc(const void *data, size_t length)
CRC calculation.
#define ENET_RBD0_LG
const NicDriver mimxrt1050EthDriver
i.MX RT1050 Ethernet MAC driver
#define TRUE
Definition: os_port.h:50
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define ENET_RBD0_E
error_t mimxrt1050EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define ENET_TBD0_R
#define ENET_RBD0_NO
#define ENET_TBD0_DATA_LENGTH
#define MIMXRT1050_ETH_RX_BUFFER_COUNT
#define ENET_RBD0_CR
void mimxrt1050EthEventHandler(NetInterface *interface)
i.MX RT1050 Ethernet MAC event handler
#define MIMXRT1050_ETH_TX_BUFFER_COUNT
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
NIC driver.
Definition: nic.h:164
#define MIMXRT1050_ETH_TX_BUFFER_SIZE
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t mimxrt1050EthReceivePacket(NetInterface *interface)
Receive a packet.
#define MIN(a, b)
Definition: os_port.h:62
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
error_t mimxrt1050EthInit(NetInterface *interface)
i.MX RT1050 Ethernet MAC initialization
#define TRACE_INFO(...)
Definition: debug.h:94
#define ENET_TBD0_TC
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
Ethernet interface.
Definition: nic.h:71
#define ENET_RBD2_INT
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
void mimxrt1050EthInitGpio(NetInterface *interface)
OsEvent netEvent
Definition: net.c:73
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:220
#define ENET_RBD0_DATA_LENGTH
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
unsigned int uint_t
Definition: compiler_port.h:45
void mimxrt1050EthTick(NetInterface *interface)
i.MX RT1050 Ethernet MAC timer handler
__start_packed struct @112 MacAddr
MAC address.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint8_t value[]
Definition: dtls_misc.h:143
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
#define osExitIsr(flag)
#define MIMXRT1050_ETH_IRQ_PRIORITY_GROUPING
#define osEnterIsr()
i.MX RT1050 Ethernet MAC controller
#define MIMXRT1050_ETH_IRQ_SUB_PRIORITY
#define ENET_TBD0_L
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define MIMXRT1050_ETH_IRQ_GROUP_PRIORITY
#define ENET_TBD0_W
#define ENET_RBD0_TR
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
#define MIMXRT1050_ETH_RX_BUFFER_SIZE
MAC filter table entry.
Definition: ethernet.h:217
#define TRACE_DEBUG(...)
Definition: debug.h:106