mimxrt1050_eth_driver.c
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1 /**
2  * @file mimxrt1050_eth_driver.c
3  * @brief i.MX RT1050 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
50 #pragma location = ".ram_no_cache"
52 //RX buffer
53 #pragma data_alignment = 16
54 #pragma location = ".ram_no_cache"
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 #pragma location = ".ram_no_cache"
59 static uint32_t txBufferDesc[MIMXRT1050_ETH_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 16
62 #pragma location = ".ram_no_cache"
63 static uint32_t rxBufferDesc[MIMXRT1050_ETH_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(16), __section__(".ram_no_cache")));
71 //RX buffer
73  __attribute__((aligned(16), __section__(".ram_no_cache")));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MIMXRT1050_ETH_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(16), __section__(".ram_no_cache")));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MIMXRT1050_ETH_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(16), __section__(".ram_no_cache")));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX RT1050 Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX RT1050 Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX RT1050 Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mimxrt1050EthInitGpio(interface);
136 
137  //Reset ENET module
138  ENET->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while(ENET->ECR & ENET_ECR_RESET_MASK)
141  {
142  }
143 
144  //Receive control register
145  ENET->RCR = ENET_RCR_MAX_FL(MIMXRT1050_ETH_RX_BUFFER_SIZE) |
146  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
147 
148  //Transmit control register
149  ENET->TCR = 0;
150  //Configure MDC clock frequency
151  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
152 
153  //PHY transceiver initialization
154  error = interface->phyDriver->init(interface);
155  //Failed to initialize PHY transceiver?
156  if(error)
157  return error;
158 
159  //Set the MAC address of the station (upper 16 bits)
160  value = interface->macAddr.b[5];
161  value |= (interface->macAddr.b[4] << 8);
162  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
163 
164  //Set the MAC address of the station (lower 32 bits)
165  value = interface->macAddr.b[3];
166  value |= (interface->macAddr.b[2] << 8);
167  value |= (interface->macAddr.b[1] << 16);
168  value |= (interface->macAddr.b[0] << 24);
169  ENET->PALR = ENET_PALR_PADDR1(value);
170 
171  //Hash table for unicast address filtering
172  ENET->IALR = 0;
173  ENET->IAUR = 0;
174  //Hash table for multicast address filtering
175  ENET->GALR = 0;
176  ENET->GAUR = 0;
177 
178  //Disable transmit accelerator functions
179  ENET->TACC = 0;
180  //Disable receive accelerator functions
181  ENET->RACC = 0;
182 
183  //Use enhanced buffer descriptors
184  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
185  //Clear MIC counters
186  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
187 
188  //Initialize buffer descriptors
189  mimxrt1050EthInitBufferDesc(interface);
190 
191  //Clear any pending interrupts
192  ENET->EIR = 0xFFFFFFFF;
193  //Enable desired interrupts
194  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
195 
196  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
197  NVIC_SetPriorityGrouping(MIMXRT1050_ETH_IRQ_PRIORITY_GROUPING);
198 
199  //Configure ENET interrupt priority
200  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1050_ETH_IRQ_PRIORITY_GROUPING,
202 
203  //Enable Ethernet MAC
204  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
205  //Instruct the DMA to poll the receive descriptor list
206  ENET->RDAR = ENET_RDAR_RDAR_MASK;
207 
208  //Accept any packets from the upper layer
209  osSetEvent(&interface->nicTxEvent);
210 
211  //Successful initialization
212  return NO_ERROR;
213 }
214 
215 
216 //MIMXRT1050-EVKA or MIMXRT1050-EVKB evaluation board?
217 #if defined(USE_MIMXRT1050_EVKA) || defined(USE_MIMXRT1050_EVKB)
218 
219 /**
220  * @brief GPIO configuration
221  * @param[in] interface Underlying network interface
222  **/
223 
224 void mimxrt1050EthInitGpio(NetInterface *interface)
225 {
226  gpio_pin_config_t pinConfig;
227  clock_enet_pll_config_t pllConfig;
228 
229 #if (defined(CPU_MIMXRT1052CVL5A) || defined(CPU_MIMXRT1052DVL6A))
230  //Configure ENET PLL (50MHz)
231  pllConfig.enableClkOutput0 = true;
232  pllConfig.enableClkOutput1 = false;
233  pllConfig.enableClkOutput2 = false;
234  pllConfig.loopDivider0 = 1;
235  pllConfig.loopDivider1 = 0;
236  CLOCK_InitEnetPll(&pllConfig);
237 #else
238  //Configure ENET PLL (50MHz)
239  pllConfig.enableClkOutput = true;
240  pllConfig.enableClkOutput25M = false;
241  pllConfig.loopDivider = 1;
242  pllConfig.src = 0;
243  CLOCK_InitEnetPll(&pllConfig);
244 #endif
245 
246  //Enable ENET1_TX_CLK output driver
247  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
248 
249  //Enable IOMUXC clock
250  CLOCK_EnableClock(kCLOCK_Iomuxc);
251 
252  //Configure GPIO_B1_04 pin as ENET_RX_DATA00
253  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
254 
255  //Set GPIO_B1_04 pad properties
256  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00,
257  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
258  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
259  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
260  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
261  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
262  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
263  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
264  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
265 
266  //Configure GPIO_B1_05 pin as ENET_RX_DATA01
267  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
268 
269  //Set GPIO_B1_05 pad properties
270  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01,
271  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
272  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
273  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
274  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
275  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
276  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
277  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
278  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
279 
280  //Configure GPIO_B1_06 pin as ENET_RX_EN
281  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
282 
283  //Set GPIO_B1_06 pad properties
284  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN,
285  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
286  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
287  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
288  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
289  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
290  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
291  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
292  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
293 
294  //Configure GPIO_B1_07 pin as ENET_TX_DATA00
295  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
296 
297  //Set GPIO_B1_07 pad properties
298  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00,
299  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
300  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
301  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
302  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
303  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
304  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
305  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
306  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
307 
308  //Configure GPIO_B1_08 pin as ENET_TX_DATA01
309  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
310 
311  //Set GPIO_B1_08 pad properties
312  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01,
313  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
314  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
315  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
316  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
317  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
318  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
319  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
320  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
321 
322  //Configure GPIO_B1_09 pin as ENET_TX_EN
323  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
324 
325  //Set GPIO_B1_09 pad properties
326  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN,
327  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
328  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
329  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
330  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
331  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
332  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
333  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
334  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
335 
336  //Configure GPIO_B1_10 pin as ENET_REF_CLK
337  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
338 
339  //Set GPIO_B1_10 pad properties
340  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK,
341  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
342  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
343  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
344  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
345  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
346  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
347  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
348  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
349 
350  //Configure GPIO_B1_11 pin as ENET_RX_ER
351  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
352 
353  //Set GPIO_B1_11 pad properties
354  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER,
355  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
356  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
357  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
358  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
359  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
360  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
361  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
362  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
363 
364  //Configure GPIO_EMC_40 pin as ENET_MDC
365  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
366 
367  //Set GPIO_EMC_40 pad properties
368  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC,
369  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
370  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
371  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
372  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
373  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
374  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
375  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
376  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
377 
378  //Configure GPIO_EMC_41 pin as ENET_MDIO
379  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
380 
381  //Set GPIO_EMC_41 pad properties
382  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO,
383  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
384  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
385  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
386  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
387  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
388  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
389  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
390  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
391 
392  //Configure GPIO_AD_B0_09 pin as GPIO1_IO09
393  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
394 
395  //Set GPIO_AD_B0_09 pad properties
396  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
397  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
398  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
399  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
400  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
401  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
402  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
403  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
404  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
405 
406  //Configure GPIO_AD_B0_10 pin as GPIO1_IO10
407  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0);
408 
409  //Set GPIO_AD_B0_10 pad properties
410  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,
411  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
412  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
413  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
414  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
415  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
416  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
417  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
418  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
419 
420  //Configure ENET_RST as an output
421  pinConfig.direction = kGPIO_DigitalOutput;
422  pinConfig.outputLogic = 0;
423  pinConfig.interruptMode = kGPIO_NoIntmode;
424  GPIO_PinInit(GPIO1, 9, &pinConfig);
425 
426  //Configure ENET_INT as an input
427  pinConfig.direction = kGPIO_DigitalInput;
428  pinConfig.outputLogic = 0;
429  pinConfig.interruptMode = kGPIO_NoIntmode;
430  GPIO_PinInit(GPIO1, 10, &pinConfig);
431 
432  //Reset PHY transceiver (hard reset)
433  GPIO_PinWrite(GPIO1, 9, 0);
434  sleep(10);
435  GPIO_PinWrite(GPIO1, 9, 1);
436  sleep(10);
437 }
438 
439 #endif
440 
441 
442 /**
443  * @brief Initialize buffer descriptors
444  * @param[in] interface Underlying network interface
445  **/
446 
448 {
449  uint_t i;
450  uint32_t address;
451 
452  //Clear TX and RX buffer descriptors
453  memset(txBufferDesc, 0, sizeof(txBufferDesc));
454  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
455 
456  //Initialize TX buffer descriptors
457  for(i = 0; i < MIMXRT1050_ETH_TX_BUFFER_COUNT; i++)
458  {
459  //Calculate the address of the current TX buffer
460  address = (uint32_t) txBuffer[i];
461  //Transmit buffer address
462  txBufferDesc[i][1] = address;
463  //Generate interrupts
464  txBufferDesc[i][2] = ENET_TBD2_INT;
465  }
466 
467  //Mark the last descriptor entry with the wrap flag
468  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
469  //Initialize TX buffer index
470  txBufferIndex = 0;
471 
472  //Initialize RX buffer descriptors
473  for(i = 0; i < MIMXRT1050_ETH_RX_BUFFER_COUNT; i++)
474  {
475  //Calculate the address of the current RX buffer
476  address = (uint32_t) rxBuffer[i];
477  //The descriptor is initially owned by the DMA
478  rxBufferDesc[i][0] = ENET_RBD0_E;
479  //Receive buffer address
480  rxBufferDesc[i][1] = address;
481  //Generate interrupts
482  rxBufferDesc[i][2] = ENET_RBD2_INT;
483  }
484 
485  //Mark the last descriptor entry with the wrap flag
486  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
487  //Initialize RX buffer index
488  rxBufferIndex = 0;
489 
490  //Start location of the TX descriptor list
491  ENET->TDSR = (uint32_t) txBufferDesc;
492  //Start location of the RX descriptor list
493  ENET->RDSR = (uint32_t) rxBufferDesc;
494  //Maximum receive buffer size
495  ENET->MRBR = MIMXRT1050_ETH_RX_BUFFER_SIZE;
496 }
497 
498 
499 /**
500  * @brief i.MX RT1050 Ethernet MAC timer handler
501  *
502  * This routine is periodically called by the TCP/IP stack to
503  * handle periodic operations such as polling the link state
504  *
505  * @param[in] interface Underlying network interface
506  **/
507 
509 {
510  //Handle periodic operations
511  interface->phyDriver->tick(interface);
512 }
513 
514 
515 /**
516  * @brief Enable interrupts
517  * @param[in] interface Underlying network interface
518  **/
519 
521 {
522  //Enable Ethernet MAC interrupts
523  NVIC_EnableIRQ(ENET_IRQn);
524  //Enable Ethernet PHY interrupts
525  interface->phyDriver->enableIrq(interface);
526 }
527 
528 
529 /**
530  * @brief Disable interrupts
531  * @param[in] interface Underlying network interface
532  **/
533 
535 {
536  //Disable Ethernet MAC interrupts
537  NVIC_DisableIRQ(ENET_IRQn);
538  //Disable Ethernet PHY interrupts
539  interface->phyDriver->disableIrq(interface);
540 }
541 
542 
543 /**
544  * @brief Ethernet MAC interrupt
545  **/
546 
547 void ENET_IRQHandler(void)
548 {
549  bool_t flag;
550  uint32_t events;
551 
552  //Interrupt service routine prologue
553  osEnterIsr();
554 
555  //This flag will be set if a higher priority task must be woken
556  flag = FALSE;
557  //Read interrupt event register
558  events = ENET->EIR;
559 
560  //A packet has been transmitted?
561  if(events & ENET_EIR_TXF_MASK)
562  {
563  //Clear TXF interrupt flag
564  ENET->EIR = ENET_EIR_TXF_MASK;
565 
566  //Check whether the TX buffer is available for writing
567  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
568  {
569  //Notify the TCP/IP stack that the transmitter is ready to send
570  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
571  }
572 
573  //Instruct the DMA to poll the transmit descriptor list
574  ENET->TDAR = ENET_TDAR_TDAR_MASK;
575  }
576 
577  //A packet has been received?
578  if(events & ENET_EIR_RXF_MASK)
579  {
580  //Disable RXF interrupt
581  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
582 
583  //Set event flag
584  nicDriverInterface->nicEvent = TRUE;
585  //Notify the TCP/IP stack of the event
586  flag = osSetEventFromIsr(&netEvent);
587  }
588 
589  //System bus error?
590  if(events & ENET_EIR_EBERR_MASK)
591  {
592  //Disable EBERR interrupt
593  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
594 
595  //Set event flag
596  nicDriverInterface->nicEvent = TRUE;
597  //Notify the TCP/IP stack of the event
598  flag |= osSetEventFromIsr(&netEvent);
599  }
600 
601  //Interrupt service routine epilogue
602  osExitIsr(flag);
603 }
604 
605 
606 /**
607  * @brief i.MX RT1050 Ethernet MAC event handler
608  * @param[in] interface Underlying network interface
609  **/
610 
612 {
613  error_t error;
614  uint32_t status;
615 
616  //Read interrupt event register
617  status = ENET->EIR;
618 
619  //Packet received?
620  if(status & ENET_EIR_RXF_MASK)
621  {
622  //Clear RXF interrupt flag
623  ENET->EIR = ENET_EIR_RXF_MASK;
624 
625  //Process all pending packets
626  do
627  {
628  //Read incoming packet
629  error = mimxrt1050EthReceivePacket(interface);
630 
631  //No more data in the receive buffer?
632  } while(error != ERROR_BUFFER_EMPTY);
633  }
634 
635  //System bus error?
636  if(status & ENET_EIR_EBERR_MASK)
637  {
638  //Clear EBERR interrupt flag
639  ENET->EIR = ENET_EIR_EBERR_MASK;
640 
641  //Disable Ethernet MAC
642  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
643  //Reset buffer descriptors
644  mimxrt1050EthInitBufferDesc(interface);
645  //Resume normal operation
646  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
647  //Instruct the DMA to poll the receive descriptor list
648  ENET->RDAR = ENET_RDAR_RDAR_MASK;
649  }
650 
651  //Re-enable Ethernet MAC interrupts
652  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
653 }
654 
655 
656 /**
657  * @brief Send a packet
658  * @param[in] interface Underlying network interface
659  * @param[in] buffer Multi-part buffer containing the data to send
660  * @param[in] offset Offset to the first data byte
661  * @return Error code
662  **/
663 
665  const NetBuffer *buffer, size_t offset)
666 {
667  static uint8_t temp[MIMXRT1050_ETH_TX_BUFFER_SIZE];
668  size_t length;
669 
670  //Retrieve the length of the packet
671  length = netBufferGetLength(buffer) - offset;
672 
673  //Check the frame length
675  {
676  //The transmitter can accept another packet
677  osSetEvent(&interface->nicTxEvent);
678  //Report an error
679  return ERROR_INVALID_LENGTH;
680  }
681 
682  //Make sure the current buffer is available for writing
683  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
684  return ERROR_FAILURE;
685 
686  //Copy user data to the transmit buffer
687  netBufferRead(temp, buffer, offset, length);
688  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
689 
690  //Clear BDU flag
691  txBufferDesc[txBufferIndex][4] = 0;
692 
693  //Check current index
694  if(txBufferIndex < (MIMXRT1050_ETH_TX_BUFFER_COUNT - 1))
695  {
696  //Give the ownership of the descriptor to the DMA engine
697  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
699 
700  //Point to the next buffer
701  txBufferIndex++;
702  }
703  else
704  {
705  //Give the ownership of the descriptor to the DMA engine
706  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
708 
709  //Wrap around
710  txBufferIndex = 0;
711  }
712 
713  //Data synchronization barrier
714  __DSB();
715 
716  //Instruct the DMA to poll the transmit descriptor list
717  ENET->TDAR = ENET_TDAR_TDAR_MASK;
718 
719  //Check whether the next buffer is available for writing
720  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
721  {
722  //The transmitter can accept another packet
723  osSetEvent(&interface->nicTxEvent);
724  }
725 
726  //Successful processing
727  return NO_ERROR;
728 }
729 
730 
731 /**
732  * @brief Receive a packet
733  * @param[in] interface Underlying network interface
734  * @return Error code
735  **/
736 
738 {
739  static uint8_t temp[MIMXRT1050_ETH_RX_BUFFER_SIZE];
740  error_t error;
741  size_t n;
742 
743  //Make sure the current buffer is available for reading
744  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
745  {
746  //The frame should not span multiple buffers
747  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
748  {
749  //Check whether an error occurred
750  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
752  {
753  //Retrieve the length of the frame
754  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
755  //Limit the number of data to read
757 
758  //Copy data from the receive buffer
759  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
760 
761  //Pass the packet to the upper layer
762  nicProcessPacket(interface, temp, n);
763 
764  //Valid packet received
765  error = NO_ERROR;
766  }
767  else
768  {
769  //The received packet contains an error
770  error = ERROR_INVALID_PACKET;
771  }
772  }
773  else
774  {
775  //The packet is not valid
776  error = ERROR_INVALID_PACKET;
777  }
778 
779  //Clear BDU flag
780  rxBufferDesc[rxBufferIndex][4] = 0;
781 
782  //Check current index
783  if(rxBufferIndex < (MIMXRT1050_ETH_RX_BUFFER_COUNT - 1))
784  {
785  //Give the ownership of the descriptor back to the DMA engine
786  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
787  //Point to the next buffer
788  rxBufferIndex++;
789  }
790  else
791  {
792  //Give the ownership of the descriptor back to the DMA engine
793  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
794  //Wrap around
795  rxBufferIndex = 0;
796  }
797 
798  //Instruct the DMA to poll the receive descriptor list
799  ENET->RDAR = ENET_RDAR_RDAR_MASK;
800  }
801  else
802  {
803  //No more data in the receive buffer
804  error = ERROR_BUFFER_EMPTY;
805  }
806 
807  //Return status code
808  return error;
809 }
810 
811 
812 /**
813  * @brief Configure MAC address filtering
814  * @param[in] interface Underlying network interface
815  * @return Error code
816  **/
817 
819 {
820  uint_t i;
821  uint_t k;
822  uint32_t crc;
823  uint32_t unicastHashTable[2];
824  uint32_t multicastHashTable[2];
825  MacFilterEntry *entry;
826 
827  //Debug message
828  TRACE_DEBUG("Updating MAC filter...\r\n");
829 
830  //Clear hash table (unicast address filtering)
831  unicastHashTable[0] = 0;
832  unicastHashTable[1] = 0;
833 
834  //Clear hash table (multicast address filtering)
835  multicastHashTable[0] = 0;
836  multicastHashTable[1] = 0;
837 
838  //The MAC address filter contains the list of MAC addresses to accept
839  //when receiving an Ethernet frame
840  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
841  {
842  //Point to the current entry
843  entry = &interface->macAddrFilter[i];
844 
845  //Valid entry?
846  if(entry->refCount > 0)
847  {
848  //Compute CRC over the current MAC address
849  crc = mimxrt1050EthCalcCrc(&entry->addr, sizeof(MacAddr));
850 
851  //The upper 6 bits in the CRC register are used to index the
852  //contents of the hash table
853  k = (crc >> 26) & 0x3F;
854 
855  //Multicast address?
856  if(macIsMulticastAddr(&entry->addr))
857  {
858  //Update the multicast hash table
859  multicastHashTable[k / 32] |= (1 << (k % 32));
860  }
861  else
862  {
863  //Update the unicast hash table
864  unicastHashTable[k / 32] |= (1 << (k % 32));
865  }
866  }
867  }
868 
869  //Write the hash table (unicast address filtering)
870  ENET->IALR = unicastHashTable[0];
871  ENET->IAUR = unicastHashTable[1];
872 
873  //Write the hash table (multicast address filtering)
874  ENET->GALR = multicastHashTable[0];
875  ENET->GAUR = multicastHashTable[1];
876 
877  //Debug message
878  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
879  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
880  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
881  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
882 
883  //Successful processing
884  return NO_ERROR;
885 }
886 
887 
888 /**
889  * @brief Adjust MAC configuration parameters for proper operation
890  * @param[in] interface Underlying network interface
891  * @return Error code
892  **/
893 
895 {
896  //Disable Ethernet MAC while modifying configuration registers
897  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
898 
899  //10BASE-T or 100BASE-TX operation mode?
900  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
901  {
902  //100 Mbps operation
903  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
904  }
905  else
906  {
907  //10 Mbps operation
908  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
909  }
910 
911  //Half-duplex or full-duplex mode?
912  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
913  {
914  //Full-duplex mode
915  ENET->TCR |= ENET_TCR_FDEN_MASK;
916  //Receive path operates independently of transmit
917  ENET->RCR &= ~ENET_RCR_DRT_MASK;
918  }
919  else
920  {
921  //Half-duplex mode
922  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
923  //Disable reception of frames while transmitting
924  ENET->RCR |= ENET_RCR_DRT_MASK;
925  }
926 
927  //Reset buffer descriptors
928  mimxrt1050EthInitBufferDesc(interface);
929 
930  //Re-enable Ethernet MAC
931  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
932  //Instruct the DMA to poll the receive descriptor list
933  ENET->RDAR = ENET_RDAR_RDAR_MASK;
934 
935  //Successful processing
936  return NO_ERROR;
937 }
938 
939 
940 /**
941  * @brief Write PHY register
942  * @param[in] opcode Access type (2 bits)
943  * @param[in] phyAddr PHY address (5 bits)
944  * @param[in] regAddr Register address (5 bits)
945  * @param[in] data Register value
946  **/
947 
948 void mimxrt1050EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
949  uint8_t regAddr, uint16_t data)
950 {
951  uint32_t temp;
952 
953  //Valid opcode?
954  if(opcode == SMI_OPCODE_WRITE)
955  {
956  //Set up a write operation
957  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
958  //PHY address
959  temp |= ENET_MMFR_PA(phyAddr);
960  //Register address
961  temp |= ENET_MMFR_RA(regAddr);
962  //Register value
963  temp |= ENET_MMFR_DATA(data);
964 
965  //Clear MII interrupt flag
966  ENET->EIR = ENET_EIR_MII_MASK;
967  //Start a write operation
968  ENET->MMFR = temp;
969 
970  //Wait for the write to complete
971  while(!(ENET->EIR & ENET_EIR_MII_MASK))
972  {
973  }
974  }
975  else
976  {
977  //The MAC peripheral only supports standard Clause 22 opcodes
978  }
979 }
980 
981 
982 /**
983  * @brief Read PHY register
984  * @param[in] opcode Access type (2 bits)
985  * @param[in] phyAddr PHY address (5 bits)
986  * @param[in] regAddr Register address (5 bits)
987  * @return Register value
988  **/
989 
990 uint16_t mimxrt1050EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
991  uint8_t regAddr)
992 {
993  uint16_t data;
994  uint32_t temp;
995 
996  //Valid opcode?
997  if(opcode == SMI_OPCODE_READ)
998  {
999  //Set up a read operation
1000  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
1001  //PHY address
1002  temp |= ENET_MMFR_PA(phyAddr);
1003  //Register address
1004  temp |= ENET_MMFR_RA(regAddr);
1005 
1006  //Clear MII interrupt flag
1007  ENET->EIR = ENET_EIR_MII_MASK;
1008  //Start a read operation
1009  ENET->MMFR = temp;
1010 
1011  //Wait for the read to complete
1012  while(!(ENET->EIR & ENET_EIR_MII_MASK))
1013  {
1014  }
1015 
1016  //Get register value
1017  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
1018  }
1019  else
1020  {
1021  //The MAC peripheral only supports standard Clause 22 opcodes
1022  data = 0;
1023  }
1024 
1025  //Return the value of the PHY register
1026  return data;
1027 }
1028 
1029 
1030 /**
1031  * @brief CRC calculation
1032  * @param[in] data Pointer to the data over which to calculate the CRC
1033  * @param[in] length Number of bytes to process
1034  * @return Resulting CRC value
1035  **/
1036 
1037 uint32_t mimxrt1050EthCalcCrc(const void *data, size_t length)
1038 {
1039  uint_t i;
1040  uint_t j;
1041 
1042  //Point to the data over which to calculate the CRC
1043  const uint8_t *p = (uint8_t *) data;
1044  //CRC preset value
1045  uint32_t crc = 0xFFFFFFFF;
1046 
1047  //Loop through data
1048  for(i = 0; i < length; i++)
1049  {
1050  //Update CRC value
1051  crc ^= p[i];
1052  //The message is processed bit by bit
1053  for(j = 0; j < 8; j++)
1054  {
1055  if(crc & 0x00000001)
1056  crc = (crc >> 1) ^ 0xEDB88320;
1057  else
1058  crc = crc >> 1;
1059  }
1060  }
1061 
1062  //Return CRC value
1063  return crc;
1064 }
void mimxrt1050EthEnableIrq(NetInterface *interface)
Enable interrupts.
MacAddr addr
MAC address.
Definition: ethernet.h:222
#define ENET_RBD0_L
#define ENET_RBD0_W
#define ENET_RBD0_OV
void mimxrt1050EthDisableIrq(NetInterface *interface)
Disable interrupts.
TCP/IP stack core.
error_t mimxrt1050EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Debugging facilities.
uint8_t p
Definition: ndp.h:298
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
#define ENET_TBD2_INT
#define txBuffer
void mimxrt1050EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void mimxrt1050EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t mimxrt1050EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define sleep(delay)
Definition: os_port.h:128
#define SMI_OPCODE_READ
Definition: nic.h:63
uint32_t mimxrt1050EthCalcCrc(const void *data, size_t length)
CRC calculation.
#define ENET_RBD0_LG
__start_packed struct @108 MacAddr
MAC address.
const NicDriver mimxrt1050EthDriver
i.MX RT1050 Ethernet MAC driver
#define TRUE
Definition: os_port.h:50
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define ENET_RBD0_E
error_t mimxrt1050EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define ENET_TBD0_R
#define ENET_RBD0_NO
uint8_t opcode
Definition: dns_common.h:172
#define ENET_TBD0_DATA_LENGTH
#define MIMXRT1050_ETH_RX_BUFFER_COUNT
#define ENET_RBD0_CR
void mimxrt1050EthEventHandler(NetInterface *interface)
i.MX RT1050 Ethernet MAC event handler
#define MIMXRT1050_ETH_TX_BUFFER_COUNT
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
NIC driver.
Definition: nic.h:179
#define MIMXRT1050_ETH_TX_BUFFER_SIZE
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t mimxrt1050EthReceivePacket(NetInterface *interface)
Receive a packet.
#define MIN(a, b)
Definition: os_port.h:62
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
error_t mimxrt1050EthInit(NetInterface *interface)
i.MX RT1050 Ethernet MAC initialization
#define TRACE_INFO(...)
Definition: debug.h:94
#define ENET_TBD0_TC
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
Ethernet interface.
Definition: nic.h:79
#define ENET_RBD2_INT
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
void mimxrt1050EthInitGpio(NetInterface *interface)
OsEvent netEvent
Definition: net.c:74
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define ENET_RBD0_DATA_LENGTH
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
unsigned int uint_t
Definition: compiler_port.h:45
void mimxrt1050EthTick(NetInterface *interface)
i.MX RT1050 Ethernet MAC timer handler
uint8_t data[]
Definition: dtls_misc.h:169
uint16_t mimxrt1050EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define NetInterface
Definition: net.h:36
uint8_t value[]
Definition: dtls_misc.h:143
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
#define osExitIsr(flag)
#define MIMXRT1050_ETH_IRQ_PRIORITY_GROUPING
#define osEnterIsr()
i.MX RT1050 Ethernet MAC controller
#define MIMXRT1050_ETH_IRQ_SUB_PRIORITY
#define ENET_TBD0_L
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define MIMXRT1050_ETH_IRQ_GROUP_PRIORITY
#define ENET_TBD0_W
#define ENET_RBD0_TR
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
#define MIMXRT1050_ETH_RX_BUFFER_SIZE
MAC filter table entry.
Definition: ethernet.h:220
#define TRACE_DEBUG(...)
Definition: debug.h:106