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31 #ifndef _MPFSXXX_ETH2_DRIVER_H
32 #define _MPFSXXX_ETH2_DRIVER_H
35 #ifndef MPFSXXX_ETH2_TX_BUFFER_COUNT
36 #define MPFSXXX_ETH2_TX_BUFFER_COUNT 16
37 #elif (MPFSXXX_ETH2_TX_BUFFER_COUNT < 1)
38 #error MPFSXXX_ETH2_TX_BUFFER_COUNT parameter is not valid
42 #ifndef MPFSXXX_ETH2_TX_BUFFER_SIZE
43 #define MPFSXXX_ETH2_TX_BUFFER_SIZE 1536
44 #elif (MPFSXXX_ETH2_TX_BUFFER_SIZE != 1536)
45 #error MPFSXXX_ETH2_TX_BUFFER_SIZE parameter is not valid
49 #ifndef MPFSXXX_ETH2_RX_BUFFER_COUNT
50 #define MPFSXXX_ETH2_RX_BUFFER_COUNT 16
51 #elif (MPFSXXX_ETH2_RX_BUFFER_COUNT < 12)
52 #error MPFSXXX_ETH2_RX_BUFFER_COUNT parameter is not valid
56 #ifndef MPFSXXX_ETH2_RX_BUFFER_SIZE
57 #define MPFSXXX_ETH2_RX_BUFFER_SIZE 1536
58 #elif (MPFSXXX_ETH2_RX_BUFFER_SIZE != 1536)
59 #error MPFSXXX_ETH2_RX_BUFFER_SIZE parameter is not valid
63 #ifndef MPFSXXX_ETH2_DUMMY_BUFFER_COUNT
64 #define MPFSXXX_ETH2_DUMMY_BUFFER_COUNT 2
65 #elif (MPFSXXX_ETH2_DUMMY_BUFFER_COUNT < 1)
66 #error MPFSXXX_ETH2_DUMMY_BUFFER_COUNT parameter is not valid
70 #ifndef MPFSXXX_ETH2_DUMMY_BUFFER_SIZE
71 #define MPFSXXX_ETH2_DUMMY_BUFFER_SIZE 128
72 #elif (MPFSXXX_ETH2_DUMMY_BUFFER_SIZE != 128)
73 #error MPFSXXX_ETH2_DUMMY_BUFFER_SIZE parameter is not valid
77 #ifndef MPFSXXX_ETH2_IRQ_PRIORITY
78 #define MPFSXXX_ETH2_IRQ_PRIORITY 7
79 #elif (MPFSXXX_ETH2_IRQ_PRIORITY < 0)
80 #error MPFSXXX_ETH2_IRQ_PRIORITY parameter is not valid
84 #ifndef MPFSXXX_ETH2_RAM_SECTION
85 #define MPFSXXX_ETH2_RAM_SECTION ".ram_no_cache"
89 #define MAC1 ((MAC_TypeDef *) 0x20112000)
92 #define MAC_TX_USED 0x80000000
93 #define MAC_TX_WRAP 0x40000000
94 #define MAC_TX_RLE_ERROR 0x20000000
95 #define MAC_TX_UNDERRUN_ERROR 0x10000000
96 #define MAC_TX_AHB_ERROR 0x08000000
97 #define MAC_TX_LATE_COL_ERROR 0x04000000
98 #define MAC_TX_CHECKSUM_ERROR 0x00700000
99 #define MAC_TX_NO_CRC 0x00010000
100 #define MAC_TX_LAST 0x00008000
101 #define MAC_TX_LENGTH 0x00003FFF
104 #define MAC_RX_ADDRESS 0xFFFFFFFC
105 #define MAC_RX_WRAP 0x00000002
106 #define MAC_RX_OWNERSHIP 0x00000001
107 #define MAC_RX_BROADCAST 0x80000000
108 #define MAC_RX_MULTICAST_HASH 0x40000000
109 #define MAC_RX_UNICAST_HASH 0x20000000
110 #define MAC_RX_SAR 0x08000000
111 #define MAC_RX_SAR_MASK 0x06000000
112 #define MAC_RX_TYPE_ID 0x01000000
113 #define MAC_RX_SNAP 0x01000000
114 #define MAC_RX_TYPE_ID_MASK 0x00C00000
115 #define MAC_RX_CHECKSUM_VALID 0x00C00000
116 #define MAC_RX_VLAN_TAG 0x00200000
117 #define MAC_RX_PRIORITY_TAG 0x00100000
118 #define MAC_RX_VLAN_PRIORITY 0x000E0000
119 #define MAC_RX_CFI 0x00010000
120 #define MAC_RX_EOF 0x00008000
121 #define MAC_RX_SOF 0x00004000
122 #define MAC_RX_LENGTH_MSB 0x00002000
123 #define MAC_RX_BAD_FCS 0x00002000
124 #define MAC_RX_LENGTH 0x00001FFF
void mpfsxxxEth2EventHandler(NetInterface *interface)
MPFSxxx Ethernet MAC event handler.
error_t mpfsxxxEth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void mpfsxxxEth2DisableIrq(NetInterface *interface)
Disable interrupts.
Structure describing a buffer that spans multiple chunks.
void mpfsxxxEth2Tick(NetInterface *interface)
MPFSxxx Ethernet MAC timer handler.
error_t mpfsxxxEth2ReceivePacket(NetInterface *interface)
Receive a packet.
const NicDriver mpfsxxxEth2Driver
MPFSxxx Ethernet MAC driver (MAC1 instance)
void mpfsxxxEth2InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
Transmit buffer descriptor.
void mpfsxxxEth2EnableIrq(NetInterface *interface)
Enable interrupts.
error_t mpfsxxxEth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Receive buffer descriptor.
void mpfsxxxEth2InitGpio(NetInterface *interface)
GPIO configuration.
error_t mpfsxxxEth2Init(NetInterface *interface)
MPFSxxx Ethernet MAC initialization.
error_t mpfsxxxEth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint16_t mpfsxxxEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void mpfsxxxEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.