msp432e4_eth_driver.h
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1 /**
2  * @file msp432e4_eth_driver.h
3  * @brief MSP432E4 Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _MSP432E4_ETH_DRIVER_H
32 #define _MSP432E4_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef MSP432E4_ETH_TX_BUFFER_COUNT
39  #define MSP432E4_ETH_TX_BUFFER_COUNT 3
40 #elif (MSP432E4_ETH_TX_BUFFER_COUNT < 1)
41  #error MSP432E4_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef MSP432E4_ETH_TX_BUFFER_SIZE
46  #define MSP432E4_ETH_TX_BUFFER_SIZE 1536
47 #elif (MSP432E4_ETH_TX_BUFFER_SIZE != 1536)
48  #error MSP432E4_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef MSP432E4_ETH_RX_BUFFER_COUNT
53  #define MSP432E4_ETH_RX_BUFFER_COUNT 6
54 #elif (MSP432E4_ETH_RX_BUFFER_COUNT < 1)
55  #error MSP432E4_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef MSP432E4_ETH_RX_BUFFER_SIZE
60  #define MSP432E4_ETH_RX_BUFFER_SIZE 1536
61 #elif (MSP432E4_ETH_RX_BUFFER_SIZE != 1536)
62  #error MSP432E4_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef MSP432E4_ETH_IRQ_PRIORITY_GROUPING
67  #define MSP432E4_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (MSP432E4_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error MSP432E4_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt priority
73 #ifndef MSP432E4_ETH_IRQ_PRIORITY
74  #define MSP432E4_ETH_IRQ_PRIORITY 192
75 #elif (MSP432E4_ETH_IRQ_PRIORITY < 0)
76  #error MSP432E4_ETH_IRQ_PRIORITY parameter is not valid
77 #endif
78 
79 //DMABUSMOD register
80 #define EMAC_DMABUSMOD_RPBL_1 (1 << EMAC_DMABUSMOD_RPBL_S)
81 #define EMAC_DMABUSMOD_RPBL_2 (2 << EMAC_DMABUSMOD_RPBL_S)
82 #define EMAC_DMABUSMOD_RPBL_4 (4 << EMAC_DMABUSMOD_RPBL_S)
83 #define EMAC_DMABUSMOD_RPBL_8 (8 << EMAC_DMABUSMOD_RPBL_S)
84 #define EMAC_DMABUSMOD_RPBL_16 (16 << EMAC_DMABUSMOD_RPBL_S)
85 #define EMAC_DMABUSMOD_RPBL_32 (32 << EMAC_DMABUSMOD_RPBL_S)
86 
87 #define EMAC_DMABUSMOD_PR_1_1 (0 << EMAC_DMABUSMOD_PR_S)
88 #define EMAC_DMABUSMOD_PR_2_1 (1 << EMAC_DMABUSMOD_PR_S)
89 #define EMAC_DMABUSMOD_PR_3_1 (2 << EMAC_DMABUSMOD_PR_S)
90 #define EMAC_DMABUSMOD_PR_4_1 (3 << EMAC_DMABUSMOD_PR_S)
91 
92 #define EMAC_DMABUSMOD_PBL_1 (1 << EMAC_DMABUSMOD_PBL_S)
93 #define EMAC_DMABUSMOD_PBL_2 (2 << EMAC_DMABUSMOD_PBL_S)
94 #define EMAC_DMABUSMOD_PBL_4 (4 << EMAC_DMABUSMOD_PBL_S)
95 #define EMAC_DMABUSMOD_PBL_8 (8 << EMAC_DMABUSMOD_PBL_S)
96 #define EMAC_DMABUSMOD_PBL_16 (16 << EMAC_DMABUSMOD_PBL_S)
97 #define EMAC_DMABUSMOD_PBL_32 (32 << EMAC_DMABUSMOD_PBL_S)
98 
99 //Transmit DMA descriptor flags
100 #define EMAC_TDES0_OWN 0x80000000
101 #define EMAC_TDES0_IC 0x40000000
102 #define EMAC_TDES0_LS 0x20000000
103 #define EMAC_TDES0_FS 0x10000000
104 #define EMAC_TDES0_DC 0x08000000
105 #define EMAC_TDES0_DP 0x04000000
106 #define EMAC_TDES0_TTSE 0x02000000
107 #define EMAC_TDES0_CRCR 0x01000000
108 #define EMAC_TDES0_CIC 0x00C00000
109 #define EMAC_TDES0_TER 0x00200000
110 #define EMAC_TDES0_TCH 0x00100000
111 #define EMAC_TDES0_VLIC 0x000C0000
112 #define EMAC_TDES0_TTSS 0x00020000
113 #define EMAC_TDES0_IHE 0x00010000
114 #define EMAC_TDES0_ES 0x00008000
115 #define EMAC_TDES0_JT 0x00004000
116 #define EMAC_TDES0_FF 0x00002000
117 #define EMAC_TDES0_IPE 0x00001000
118 #define EMAC_TDES0_LCA 0x00000800
119 #define EMAC_TDES0_NC 0x00000400
120 #define EMAC_TDES0_LCO 0x00000200
121 #define EMAC_TDES0_EC 0x00000100
122 #define EMAC_TDES0_VF 0x00000080
123 #define EMAC_TDES0_CC 0x00000078
124 #define EMAC_TDES0_ED 0x00000004
125 #define EMAC_TDES0_UF 0x00000002
126 #define EMAC_TDES0_DB 0x00000001
127 #define EMAC_TDES1_SAIC 0xE0000000
128 #define EMAC_TDES1_TBS2 0x1FFF0000
129 #define EMAC_TDES1_TBS1 0x00001FFF
130 #define EMAC_TDES2_TBAP1 0xFFFFFFFF
131 #define EMAC_TDES3_TBAP2 0xFFFFFFFF
132 #define EMAC_TDES6_TTSL 0xFFFFFFFF
133 #define EMAC_TDES7_TTSH 0xFFFFFFFF
134 
135 //Receive DMA descriptor flags
136 #define EMAC_RDES0_OWN 0x80000000
137 #define EMAC_RDES0_AFM 0x40000000
138 #define EMAC_RDES0_FL 0x3FFF0000
139 #define EMAC_RDES0_ES 0x00008000
140 #define EMAC_RDES0_DE 0x00004000
141 #define EMAC_RDES0_SAF 0x00002000
142 #define EMAC_RDES0_LE 0x00001000
143 #define EMAC_RDES0_OE 0x00000800
144 #define EMAC_RDES0_VLAN 0x00000400
145 #define EMAC_RDES0_FS 0x00000200
146 #define EMAC_RDES0_LS 0x00000100
147 #define EMAC_RDES0_TSA_GF 0x00000080
148 #define EMAC_RDES0_LCO 0x00000040
149 #define EMAC_RDES0_FT 0x00000020
150 #define EMAC_RDES0_RWT 0x00000010
151 #define EMAC_RDES0_RE 0x00000008
152 #define EMAC_RDES0_DBE 0x00000004
153 #define EMAC_RDES0_CE 0x00000002
154 #define EMAC_RDES0_ESA 0x00000001
155 #define EMAC_RDES1_DIC 0x80000000
156 #define EMAC_RDES1_RBS2 0x1FFF0000
157 #define EMAC_RDES1_RER 0x00008000
158 #define EMAC_RDES1_RCH 0x00004000
159 #define EMAC_RDES1_RBS1 0x00001FFF
160 #define EMAC_RDES2_RBAP1 0xFFFFFFFF
161 #define EMAC_RDES3_RBAP2 0xFFFFFFFF
162 #define EMAC_RDES4_TSD 0x00004000
163 #define EMAC_RDES4_PV 0x00002000
164 #define EMAC_RDES4_PFT 0x00001000
165 #define EMAC_RDES4_PMT 0x00000F00
166 #define EMAC_RDES4_IPV6PR 0x00000080
167 #define EMAC_RDES4_IPV4PR 0x00000040
168 #define EMAC_RDES4_IPCB 0x00000020
169 #define EMAC_RDES4_IPPE 0x00000010
170 #define EMAC_RDES4_IPHE 0x00000008
171 #define EMAC_RDES4_IPPT 0x00000007
172 #define EMAC_RDES6_RTSL 0xFFFFFFFF
173 #define EMAC_RDES7_RTSH 0xFFFFFFFF
174 
175 //C++ guard
176 #ifdef __cplusplus
177 extern "C" {
178 #endif
179 
180 
181 /**
182  * @brief Enhanced TX DMA descriptor
183  **/
184 
185 typedef struct
186 {
187  uint32_t tdes0;
188  uint32_t tdes1;
189  uint32_t tdes2;
190  uint32_t tdes3;
191  uint32_t tdes4;
192  uint32_t tdes5;
193  uint32_t tdes6;
194  uint32_t tdes7;
196 
197 
198 /**
199  * @brief Enhanced RX DMA descriptor
200  **/
201 
202 typedef struct
203 {
204  uint32_t rdes0;
205  uint32_t rdes1;
206  uint32_t rdes2;
207  uint32_t rdes3;
208  uint32_t rdes4;
209  uint32_t rdes5;
210  uint32_t rdes6;
211  uint32_t rdes7;
213 
214 
215 //MSP432E4 Ethernet MAC driver
216 extern const NicDriver msp432e4EthDriver;
217 
218 //MSP432E4 Ethernet MAC related functions
220 void msp432e4EthInitGpio(NetInterface *interface);
221 void msp432e4EthInitDmaDesc(NetInterface *interface);
222 
223 void msp432e4EthTick(NetInterface *interface);
224 
225 void msp432e4EthEnableIrq(NetInterface *interface);
226 void msp432e4EthDisableIrq(NetInterface *interface);
227 void msp432e4EthEventHandler(NetInterface *interface);
228 
230  const NetBuffer *buffer, size_t offset);
231 
233 
235 
236 void msp432e4EthWritePhyReg(uint8_t regAddr, uint16_t data);
237 uint16_t msp432e4EthReadPhyReg(uint8_t regAddr);
238 void msp432e4EthDumpPhyReg(void);
239 
240 uint32_t msp432e4EthCalcCrc(const void *data, size_t length);
241 
242 //C++ guard
243 #ifdef __cplusplus
244 }
245 #endif
246 
247 #endif
uint8_t length
Definition: dtls_misc.h:149
Enhanced TX DMA descriptor.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void msp432e4EthWritePhyReg(uint8_t regAddr, uint16_t data)
Write PHY register.
void msp432e4EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
void msp432e4EthDumpPhyReg(void)
Dump PHY registers for debugging purpose.
const NicDriver msp432e4EthDriver
MSP432E4 Ethernet MAC driver.
uint16_t regAddr
error_t msp432e4EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
error_t msp432e4EthInit(NetInterface *interface)
MSP432E4 Ethernet MAC initialization.
void msp432e4EthTick(NetInterface *interface)
MSP432E4 Ethernet MAC timer handler.
uint16_t msp432e4EthReadPhyReg(uint8_t regAddr)
Read PHY register.
error_t msp432e4EthReceivePacket(NetInterface *interface)
Receive a packet.
Network interface controller abstraction layer.
void msp432e4EthEventHandler(NetInterface *interface)
MSP432E4 Ethernet MAC event handler.
void msp432e4EthInitGpio(NetInterface *interface)
error_t msp432e4EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
Enhanced RX DMA descriptor.
uint32_t msp432e4EthCalcCrc(const void *data, size_t length)
CRC calculation.
void msp432e4EthDisableIrq(NetInterface *interface)
Disable interrupts.
void msp432e4EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.