pic32mz_eth_driver.h
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1 /**
2  * @file pic32mz_eth_driver.h
3  * @brief PIC32MZ Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _PIC32MZ_ETH_DRIVER_H
30 #define _PIC32MZ_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef PIC32MZ_ETH_TX_BUFFER_COUNT
37  #define PIC32MZ_ETH_TX_BUFFER_COUNT 3
38 #elif (PIC32MZ_ETH_TX_BUFFER_COUNT < 1)
39  #error PIC32MZ_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef PIC32MZ_ETH_TX_BUFFER_SIZE
44  #define PIC32MZ_ETH_TX_BUFFER_SIZE 1536
45 #elif (PIC32MZ_ETH_TX_BUFFER_SIZE != 1536)
46  #error PIC32MZ_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef PIC32MZ_ETH_RX_BUFFER_COUNT
51  #define PIC32MZ_ETH_RX_BUFFER_COUNT 6
52 #elif (PIC32MZ_ETH_RX_BUFFER_COUNT < 1)
53  #error PIC32MZ_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef PIC32MZ_ETH_RX_BUFFER_SIZE
58  #define PIC32MZ_ETH_RX_BUFFER_SIZE 1536
59 #elif (PIC32MZ_ETH_RX_BUFFER_SIZE != 1536)
60  #error PIC32MZ_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Ethernet interrupt priority
64 #ifndef PIC32MZ_ETH_IRQ_PRIORITY
65  #define PIC32MZ_ETH_IRQ_PRIORITY 2
66 #elif (PIC32MZ_ETH_IRQ_PRIORITY < 0)
67  #error PIC32MZ_ETH_IRQ_PRIORITY parameter is not valid
68 #endif
69 
70 //Ethernet interrupt subpriority
71 #ifndef PIC32MZ_ETH_IRQ_SUB_PRIORITY
72  #define PIC32MZ_ETH_IRQ_SUB_PRIORITY 0
73 #elif (PIC32MZ_ETH_IRQ_SUB_PRIORITY < 0)
74  #error PIC32MZ_ETH_IRQ_SUB_PRIORITY parameter is not valid
75 #endif
76 
77 //EMAC1MCFG register
78 #define _EMAC1MCFG_CLKSEL_DIV4 (0 << _EMAC1MCFG_CLKSEL_POSITION)
79 #define _EMAC1MCFG_CLKSEL_DIV6 (2 << _EMAC1MCFG_CLKSEL_POSITION)
80 #define _EMAC1MCFG_CLKSEL_DIV8 (3 << _EMAC1MCFG_CLKSEL_POSITION)
81 #define _EMAC1MCFG_CLKSEL_DIV10 (4 << _EMAC1MCFG_CLKSEL_POSITION)
82 #define _EMAC1MCFG_CLKSEL_DIV14 (5 << _EMAC1MCFG_CLKSEL_POSITION)
83 #define _EMAC1MCFG_CLKSEL_DIV20 (6 << _EMAC1MCFG_CLKSEL_POSITION)
84 #define _EMAC1MCFG_CLKSEL_DIV28 (7 << _EMAC1MCFG_CLKSEL_POSITION)
85 #define _EMAC1MCFG_CLKSEL_DIV40 (8 << _EMAC1MCFG_CLKSEL_POSITION)
86 #define _EMAC1MCFG_CLKSEL_DIV48 (9 << _EMAC1MCFG_CLKSEL_POSITION)
87 #define _EMAC1MCFG_CLKSEL_DIV50 (10 << _EMAC1MCFG_CLKSEL_POSITION)
88 
89 //Transmit buffer descriptor flags
90 #define ETH_TX_CTRL_SOP 0x80000000
91 #define ETH_TX_CTRL_EOP 0x40000000
92 #define ETH_TX_CTRL_BYTE_COUNT 0x07FF0000
93 #define ETH_TX_CTRL_NPV 0x00000100
94 #define ETH_TX_CTRL_EOWN 0x00000080
95 #define ETH_TX_STATUS1_VLAN 0x00080000
96 #define ETH_TX_STATUS1_BACKPRESSURE 0x00040000
97 #define ETH_TX_STATUS1_PAUSE 0x00020000
98 #define ETH_TX_STATUS1_CONTROL 0x00010000
99 #define ETH_TX_STATUS1_TOTAL_BYTES 0x0000FFFF
100 #define ETH_TX_STATUS2_UNDERRUN 0x80000000
101 #define ETH_TX_STATUS2_GIANT 0x40000000
102 #define ETH_TX_STATUS2_LATE_COL 0x20000000
103 #define ETH_TX_STATUS2_MAX_COL 0x10000000
104 #define ETH_TX_STATUS2_EXCESSIVE_DEFER 0x08000000
105 #define ETH_TX_STATUS2_PACKET_DEFER 0x04000000
106 #define ETH_TX_STATUS2_BROADCAST 0x02000000
107 #define ETH_TX_STATUS2_MULTICAST 0x01000000
108 #define ETH_TX_STATUS2_DONE 0x00800000
109 #define ETH_TX_STATUS2_LEN_OUT_OF_RANGE 0x00400000
110 #define ETH_TX_STATUS2_LEN_CHECK_ERROR 0x00200000
111 #define ETH_TX_STATUS2_CRC_ERROR 0x00100000
112 #define ETH_TX_STATUS2_COL_COUNT 0x000F0000
113 #define ETH_TX_STATUS2_BYTE_COUNT 0x0000FFFF
114 
115 //Receive buffer descriptor flags
116 #define ETH_RX_CTRL_SOP 0x80000000
117 #define ETH_RX_CTRL_EOP 0x40000000
118 #define ETH_RX_CTRL_BYTE_COUNT 0x07FF0000
119 #define ETH_RX_CTRL_NPV 0x00000100
120 #define ETH_RX_CTRL_EOWN 0x00000080
121 #define ETH_RX_STATUS1_MULTICAST_MATCH 0x80000000
122 #define ETH_RX_STATUS1_BROADCAST_MATCH 0x40000000
123 #define ETH_RX_STATUS1_UNICAST_MATCH 0x20000000
124 #define ETH_RX_STATUS1_PATTERN_MATCH 0x10000000
125 #define ETH_RX_STATUS1_MAGIC_PACKET_MATCH 0x08000000
126 #define ETH_RX_STATUS1_HASH_TABLE_MATCH 0x04000000
127 #define ETH_RX_STATUS1_NOT_MATCH 0x02000000
128 #define ETH_RX_STATUS1_RUNT_PACKET 0x01000000
129 #define ETH_RX_STATUS1_PACKET_CHECKSUM 0x0000FFFF
130 #define ETH_RX_STATUS2_VLAN 0x40000000
131 #define ETH_RX_STATUS2_UNKNOWN_OP_CODE 0x20000000
132 #define ETH_RX_STATUS2_PAUSE 0x10000000
133 #define ETH_RX_STATUS2_CONTROL 0x08000000
134 #define ETH_RX_STATUS2_DRIBBLE_NIBBLE 0x04000000
135 #define ETH_RX_STATUS2_BROADCAST 0x02000000
136 #define ETH_RX_STATUS2_MULTICAST 0x01000000
137 #define ETH_RX_STATUS2_OK 0x00800000
138 #define ETH_RX_STATUS2_LEN_OUT_OF_RANGE 0x00400000
139 #define ETH_RX_STATUS2_LEN_CHECK_ERROR 0x00200000
140 #define ETH_RX_STATUS2_CRC_ERROR 0x00100000
141 #define ETH_RX_STATUS2_CODE_VIOLATION 0x00080000
142 #define ETH_RX_STATUS2_CARRIER_EVENT 0x00040000
143 #define ETH_RX_STATUS2_RXDV_EVENT 0x00020000
144 #define ETH_RX_STATUS2_LONG_EVENT 0x00010000
145 #define ETH_RX_STATUS2_BYTE_COUNT 0x0000FFFF
146 
147 //C++ guard
148 #ifdef __cplusplus
149  extern "C" {
150 #endif
151 
152 
153 /**
154  * @brief TX buffer descriptor
155  **/
156 
157 typedef struct
158 {
159  uint32_t control;
160  uint32_t address;
161  uint32_t status1;
162  uint32_t status2;
163  uint32_t next;
165 
166 
167 /**
168  * @brief RX buffer descriptor
169  **/
170 
171 typedef struct
172 {
173  uint32_t control;
174  uint32_t address;
175  uint32_t status1;
176  uint32_t status2;
177  uint32_t next;
179 
180 
181 //PIC32MZ Ethernet MAC driver
182 extern const NicDriver pic32mzEthDriver;
183 
184 //PIC32MZ Ethernet MAC related functions
186 void pic32mzEthInitGpio(NetInterface *interface);
187 void pic32mzEthInitBufferDesc(NetInterface *interface);
188 
189 void pic32mzEthTick(NetInterface *interface);
190 
191 void pic32mzEthEnableIrq(NetInterface *interface);
192 void pic32mzEthDisableIrq(NetInterface *interface);
193 void pic32mzEthIrqHandler(void);
194 void pic32mzEthEventHandler(NetInterface *interface);
195 
197  const NetBuffer *buffer, size_t offset);
198 
200 
203 
204 void pic32mzEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
205 uint16_t pic32mzEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
206 
207 uint32_t pic32mzEthCalcCrc(const void *data, size_t length);
208 
209 //C++ guard
210 #ifdef __cplusplus
211  }
212 #endif
213 
214 #endif
error_t pic32mzEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void pic32mzEthEnableIrq(NetInterface *interface)
Enable interrupts.
void pic32mzEthDisableIrq(NetInterface *interface)
Disable interrupts.
uint32_t pic32mzEthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t pic32mzEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t pic32mzEthInit(NetInterface *interface)
PIC32MZ Ethernet MAC initialization.
void pic32mzEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t pic32mzEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint16_t pic32mzEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void pic32mzEthTick(NetInterface *interface)
PIC32MZ Ethernet MAC timer handler.
RX buffer descriptor.
NIC driver.
Definition: nic.h:161
TX buffer descriptor.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void pic32mzEthEventHandler(NetInterface *interface)
PIC32MZ Ethernet MAC event handler.
uint16_t regAddr
error_t pic32mzEthReceivePacket(NetInterface *interface)
Receive a packet.
error_t
Error codes.
Definition: error.h:40
void pic32mzEthInitGpio(NetInterface *interface)
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
const NicDriver pic32mzEthDriver
PIC32MZ Ethernet MAC driver.
void pic32mzEthIrqHandler(void)
PIC32MZ Ethernet MAC interrupt service routine.
uint8_t length
Definition: dtls_misc.h:140
Network interface controller abstraction layer.
void pic32mzEthInitBufferDesc(NetInterface *interface)
Initialize DMA descriptor lists.