s5d9_eth_driver.h
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1 /**
2  * @file s5d9_eth_driver.h
3  * @brief Renesas Synergy S5D9 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 #ifndef _S5D9_ETH_DRIVER_H
32 #define _S5D9_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef S5D9_ETH_TX_BUFFER_COUNT
39  #define S5D9_ETH_TX_BUFFER_COUNT 3
40 #elif (S5D9_ETH_TX_BUFFER_COUNT < 1)
41  #error S5D9_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef S5D9_ETH_TX_BUFFER_SIZE
46  #define S5D9_ETH_TX_BUFFER_SIZE 1536
47 #elif (S5D9_ETH_TX_BUFFER_SIZE != 1536)
48  #error S5D9_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef S5D9_ETH_RX_BUFFER_COUNT
53  #define S5D9_ETH_RX_BUFFER_COUNT 6
54 #elif (S5D9_ETH_RX_BUFFER_COUNT < 1)
55  #error S5D9_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef S5D9_ETH_RX_BUFFER_SIZE
60  #define S5D9_ETH_RX_BUFFER_SIZE 1536
61 #elif (S5D9_ETH_RX_BUFFER_SIZE != 1536)
62  #error S5D9_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef S5D9_ETH_IRQ_PRIORITY_GROUPING
67  #define S5D9_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (S5D9_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error S5D9_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef S5D9_ETH_IRQ_GROUP_PRIORITY
74  #define S5D9_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (S5D9_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error S5D9_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef S5D9_ETH_IRQ_SUB_PRIORITY
81  #define S5D9_ETH_IRQ_SUB_PRIORITY 0
82 #elif (S5D9_ETH_IRQ_SUB_PRIORITY < 0)
83  #error S5D9_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //EESR register
87 #define EDMAC_EESR_TWB 0x40000000
88 #define EDMAC_EESR_TABT 0x04000000
89 #define EDMAC_EESR_RABT 0x02000000
90 #define EDMAC_EESR_RFCOF 0x01000000
91 #define EDMAC_EESR_ADE 0x00800000
92 #define EDMAC_EESR_ECI 0x00400000
93 #define EDMAC_EESR_TC 0x00200000
94 #define EDMAC_EESR_TDE 0x00100000
95 #define EDMAC_EESR_TFUF 0x00080000
96 #define EDMAC_EESR_FR 0x00040000
97 #define EDMAC_EESR_RDE 0x00020000
98 #define EDMAC_EESR_RFOF 0x00010000
99 #define EDMAC_EESR_CND 0x00000800
100 #define EDMAC_EESR_DLC 0x00000400
101 #define EDMAC_EESR_CD 0x00000200
102 #define EDMAC_EESR_TRO 0x00000100
103 #define EDMAC_EESR_RMAF 0x00000080
104 #define EDMAC_EESR_RRF 0x00000010
105 #define EDMAC_EESR_RTLF 0x00000008
106 #define EDMAC_EESR_RTSF 0x00000004
107 #define EDMAC_EESR_PRE 0x00000002
108 #define EDMAC_EESR_CERF 0x00000001
109 
110 //Transmit DMA descriptor flags
111 #define EDMAC_TD0_TACT 0x80000000
112 #define EDMAC_TD0_TDLE 0x40000000
113 #define EDMAC_TD0_TFP_SOF 0x20000000
114 #define EDMAC_TD0_TFP_EOF 0x10000000
115 #define EDMAC_TD0_TFE 0x08000000
116 #define EDMAC_TD0_TWBI 0x04000000
117 #define EDMAC_TD0_TFS_MASK 0x0000010F
118 #define EDMAC_TD0_TFS_TABT 0x00000100
119 #define EDMAC_TD0_TFS_CND 0x00000008
120 #define EDMAC_TD0_TFS_DLC 0x00000004
121 #define EDMAC_TD0_TFS_CD 0x00000002
122 #define EDMAC_TD0_TFS_TRO 0x00000001
123 #define EDMAC_TD1_TBL 0xFFFF0000
124 #define EDMAC_TD2_TBA 0xFFFFFFFF
125 
126 //Receive DMA descriptor flags
127 #define EDMAC_RD0_RACT 0x80000000
128 #define EDMAC_RD0_RDLE 0x40000000
129 #define EDMAC_RD0_RFP_SOF 0x20000000
130 #define EDMAC_RD0_RFP_EOF 0x10000000
131 #define EDMAC_RD0_RFE 0x08000000
132 #define EDMAC_RD0_RFS_MASK 0x0000039F
133 #define EDMAC_RD0_RFS_RFOF 0x00000200
134 #define EDMAC_RD0_RFS_RABT 0x00000100
135 #define EDMAC_RD0_RFS_RMAF 0x00000080
136 #define EDMAC_RD0_RFS_RRF 0x00000010
137 #define EDMAC_RD0_RFS_RTLF 0x00000008
138 #define EDMAC_RD0_RFS_RTSF 0x00000004
139 #define EDMAC_RD0_RFS_PRE 0x00000002
140 #define EDMAC_RD0_RFS_CERF 0x00000001
141 #define EDMAC_RD1_RBL 0xFFFF0000
142 #define EDMAC_RD1_RFL 0x0000FFFF
143 #define EDMAC_RD2_RBA 0xFFFFFFFF
144 
145 //C++ guard
146 #ifdef __cplusplus
147  extern "C" {
148 #endif
149 
150 
151 /**
152  * @brief Transmit DMA descriptor
153  **/
154 
155 typedef struct
156 {
157  uint32_t td0;
158  uint32_t td1;
159  uint32_t td2;
160  uint32_t padding;
161 } S5d9TxDmaDesc;
162 
163 
164 /**
165  * @brief Receive DMA descriptor
166  **/
167 
168 typedef struct
169 {
170  uint32_t rd0;
171  uint32_t rd1;
172  uint32_t rd2;
173  uint32_t padding;
174 } S5d9RxDmaDesc;
175 
176 
177 //S5D9 Ethernet MAC driver
178 extern const NicDriver s5d9EthDriver;
179 
180 //S5D9 Ethernet MAC related functions
181 error_t s5d9EthInit(NetInterface *interface);
182 void s5d9EthInitGpio(NetInterface *interface);
183 void s5d9EthInitDmaDesc(NetInterface *interface);
184 
185 void s5d9EthTick(NetInterface *interface);
186 
187 void s5d9EthEnableIrq(NetInterface *interface);
188 void s5d9EthDisableIrq(NetInterface *interface);
189 void s5d9EthEventHandler(NetInterface *interface);
190 
192  const NetBuffer *buffer, size_t offset);
193 
195 
198 
199 void s5d9EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
200  uint8_t regAddr, uint16_t data);
201 
202 uint16_t s5d9EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
203  uint8_t regAddr);
204 
205 void s5d9EthWriteSmi(uint32_t data, uint_t length);
206 uint32_t s5d9EthReadSmi(uint_t length);
207 
208 //C++ guard
209 #ifdef __cplusplus
210  }
211 #endif
212 
213 #endif
void s5d9EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t s5d9EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t s5d9EthInit(NetInterface *interface)
S5D9 Ethernet MAC initialization.
Receive DMA descriptor.
error_t s5d9EthReceivePacket(NetInterface *interface)
Receive a packet.
void s5d9EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t s5d9EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Transmit DMA descriptor.
void s5d9EthEnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t opcode
Definition: dns_common.h:172
void s5d9EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void s5d9EthEventHandler(NetInterface *interface)
S5D9 Ethernet MAC event handler.
uint32_t s5d9EthReadSmi(uint_t length)
SMI read operation.
NIC driver.
Definition: nic.h:179
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void s5d9EthInitGpio(NetInterface *interface)
uint16_t regAddr
const NicDriver s5d9EthDriver
S5D9 Ethernet MAC driver.
error_t
Error codes.
Definition: error.h:42
unsigned int uint_t
Definition: compiler_port.h:45
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint16_t s5d9EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t s5d9EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint8_t length
Definition: dtls_misc.h:142
Network interface controller abstraction layer.
void s5d9EthTick(NetInterface *interface)
S5D9 Ethernet MAC timer handler.
void s5d9EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.