Data Structures | Macros | Functions | Variables
s7g2_eth1_driver.h File Reference

Renesas Synergy S7G2 Ethernet MAC driver (ETHERC0 instance) More...

#include "core/nic.h"

Go to the source code of this file.

Data Structures

struct  S7g2Eth1TxDmaDesc
 Transmit DMA descriptor. More...
 
struct  S7g2Eth1RxDmaDesc
 Receive DMA descriptor. More...
 

Macros

#define S7G2_ETH1_TX_BUFFER_COUNT   3
 
#define S7G2_ETH1_TX_BUFFER_SIZE   1536
 
#define S7G2_ETH1_RX_BUFFER_COUNT   6
 
#define S7G2_ETH1_RX_BUFFER_SIZE   1536
 
#define S7G2_ETH1_IRQ_PRIORITY_GROUPING   3
 
#define S7G2_ETH1_IRQ_GROUP_PRIORITY   12
 
#define S7G2_ETH1_IRQ_SUB_PRIORITY   0
 
#define ETHERC_ECMR_TPC   0x00100000
 
#define ETHERC_ECMR_ZPF   0x00080000
 
#define ETHERC_ECMR_PFR   0x00040000
 
#define ETHERC_ECMR_RXF   0x00020000
 
#define ETHERC_ECMR_TXF   0x00010000
 
#define ETHERC_ECMR_PRCEF   0x00001000
 
#define ETHERC_ECMR_MPDE   0x00000200
 
#define ETHERC_ECMR_RE   0x00000040
 
#define ETHERC_ECMR_TE   0x00000020
 
#define ETHERC_ECMR_ILB   0x00000008
 
#define ETHERC_ECMR_RTM   0x00000004
 
#define ETHERC_ECMR_DM   0x00000002
 
#define ETHERC_ECMR_PRM   0x00000001
 
#define ETHERC_PIR_MDI   0x00000008
 
#define ETHERC_PIR_MDO   0x00000004
 
#define ETHERC_PIR_MMD   0x00000002
 
#define ETHERC_PIR_MDC   0x00000001
 
#define EDMAC_EDMR_DE   0x00000040
 
#define EDMAC_EDMR_DL   0x00000030
 
#define EDMAC_EDMR_DL_16   0x00000000
 
#define EDMAC_EDMR_DL_32   0x00000010
 
#define EDMAC_EDMR_DL_64   0x00000020
 
#define EDMAC_EDMR_SWR   0x00000001
 
#define EDMAC_EDTRR_TR   0x00000001
 
#define EDMAC_EDRRR_RR   0x00000001
 
#define EDMAC_EESR_TWB   0x40000000
 
#define EDMAC_EESR_TABT   0x04000000
 
#define EDMAC_EESR_RABT   0x02000000
 
#define EDMAC_EESR_RFCOF   0x01000000
 
#define EDMAC_EESR_ADE   0x00800000
 
#define EDMAC_EESR_ECI   0x00400000
 
#define EDMAC_EESR_TC   0x00200000
 
#define EDMAC_EESR_TDE   0x00100000
 
#define EDMAC_EESR_TFUF   0x00080000
 
#define EDMAC_EESR_FR   0x00040000
 
#define EDMAC_EESR_RDE   0x00020000
 
#define EDMAC_EESR_RFOF   0x00010000
 
#define EDMAC_EESR_CND   0x00000800
 
#define EDMAC_EESR_DLC   0x00000400
 
#define EDMAC_EESR_CD   0x00000200
 
#define EDMAC_EESR_TRO   0x00000100
 
#define EDMAC_EESR_RMAF   0x00000080
 
#define EDMAC_EESR_RRF   0x00000010
 
#define EDMAC_EESR_RTLF   0x00000008
 
#define EDMAC_EESR_RTSF   0x00000004
 
#define EDMAC_EESR_PRE   0x00000002
 
#define EDMAC_EESR_CERF   0x00000001
 
#define EDMAC_EESIPR_TWBIP   0x40000000
 
#define EDMAC_EESIPR_TABTIP   0x04000000
 
#define EDMAC_EESIPR_RABTIP   0x02000000
 
#define EDMAC_EESIPR_RFCOFIP   0x01000000
 
#define EDMAC_EESIPR_ADEIP   0x00800000
 
#define EDMAC_EESIPR_ECIIP   0x00400000
 
#define EDMAC_EESIPR_TCIP   0x00200000
 
#define EDMAC_EESIPR_TDEIP   0x00100000
 
#define EDMAC_EESIPR_TFUFIP   0x00080000
 
#define EDMAC_EESIPR_FRIP   0x00040000
 
#define EDMAC_EESIPR_RDEIP   0x00020000
 
#define EDMAC_EESIPR_RFOFIP   0x00010000
 
#define EDMAC_EESIPR_CNDIP   0x00000800
 
#define EDMAC_EESIPR_DLCIP   0x00000400
 
#define EDMAC_EESIPR_CDIP   0x00000200
 
#define EDMAC_EESIPR_TROIP   0x00000100
 
#define EDMAC_EESIPR_RMAFIP   0x00000080
 
#define EDMAC_EESIPR_RRFIP   0x00000010
 
#define EDMAC_EESIPR_RTLFIP   0x00000008
 
#define EDMAC_EESIPR_RTSFIP   0x00000004
 
#define EDMAC_EESIPR_PREIP   0x00000002
 
#define EDMAC_EESIPR_CERFIP   0x00000001
 
#define EDMAC_FDR_TFD   0x00001F00
 
#define EDMAC_FDR_TFD_2048   0x00000700
 
#define EDMAC_FDR_RFD   0x0000001F
 
#define EDMAC_FDR_RFD_4096   0x0000000F
 
#define EDMAC_RMCR_RNR   0x00000001
 
#define EDMAC_TRIMD_TIM   0x00000010
 
#define EDMAC_TRIMD_TIS   0x00000001
 
#define EDMAC_TD0_TACT   0x80000000
 
#define EDMAC_TD0_TDLE   0x40000000
 
#define EDMAC_TD0_TFP_SOF   0x20000000
 
#define EDMAC_TD0_TFP_EOF   0x10000000
 
#define EDMAC_TD0_TFE   0x08000000
 
#define EDMAC_TD0_TWBI   0x04000000
 
#define EDMAC_TD0_TFS_MASK   0x0000010F
 
#define EDMAC_TD0_TFS_TABT   0x00000100
 
#define EDMAC_TD0_TFS_CND   0x00000008
 
#define EDMAC_TD0_TFS_DLC   0x00000004
 
#define EDMAC_TD0_TFS_CD   0x00000002
 
#define EDMAC_TD0_TFS_TRO   0x00000001
 
#define EDMAC_TD1_TBL   0xFFFF0000
 
#define EDMAC_TD2_TBA   0xFFFFFFFF
 
#define EDMAC_RD0_RACT   0x80000000
 
#define EDMAC_RD0_RDLE   0x40000000
 
#define EDMAC_RD0_RFP_SOF   0x20000000
 
#define EDMAC_RD0_RFP_EOF   0x10000000
 
#define EDMAC_RD0_RFE   0x08000000
 
#define EDMAC_RD0_RFS_MASK   0x0000039F
 
#define EDMAC_RD0_RFS_RFOF   0x00000200
 
#define EDMAC_RD0_RFS_RABT   0x00000100
 
#define EDMAC_RD0_RFS_RMAF   0x00000080
 
#define EDMAC_RD0_RFS_RRF   0x00000010
 
#define EDMAC_RD0_RFS_RTLF   0x00000008
 
#define EDMAC_RD0_RFS_RTSF   0x00000004
 
#define EDMAC_RD0_RFS_PRE   0x00000002
 
#define EDMAC_RD0_RFS_CERF   0x00000001
 
#define EDMAC_RD1_RBL   0xFFFF0000
 
#define EDMAC_RD1_RFL   0x0000FFFF
 
#define EDMAC_RD2_RBA   0xFFFFFFFF
 

Functions

error_t s7g2Eth1Init (NetInterface *interface)
 S7G2 Ethernet MAC initialization. More...
 
void s7g2Eth1InitGpio (NetInterface *interface)
 GPIO configuration. More...
 
void s7g2Eth1InitDmaDesc (NetInterface *interface)
 Initialize DMA descriptor lists. More...
 
void s7g2Eth1Tick (NetInterface *interface)
 S7G2 Ethernet MAC timer handler. More...
 
void s7g2Eth1EnableIrq (NetInterface *interface)
 Enable interrupts. More...
 
void s7g2Eth1DisableIrq (NetInterface *interface)
 Disable interrupts. More...
 
void s7g2Eth1EventHandler (NetInterface *interface)
 S7G2 Ethernet MAC event handler. More...
 
error_t s7g2Eth1SendPacket (NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
 Send a packet. More...
 
error_t s7g2Eth1ReceivePacket (NetInterface *interface)
 Receive a packet. More...
 
error_t s7g2Eth1UpdateMacAddrFilter (NetInterface *interface)
 Configure MAC address filtering. More...
 
error_t s7g2Eth1UpdateMacConfig (NetInterface *interface)
 Adjust MAC configuration parameters for proper operation. More...
 
void s7g2Eth1WritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
 Write PHY register. More...
 
uint16_t s7g2Eth1ReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
 Read PHY register. More...
 
void s7g2Eth1WriteSmi (uint32_t data, uint_t length)
 SMI write operation. More...
 
uint32_t s7g2Eth1ReadSmi (uint_t length)
 SMI read operation. More...
 

Variables

const NicDriver s7g2Eth1Driver
 S7G2 Ethernet MAC driver (ETHERC0 instance) More...
 

Detailed Description

Renesas Synergy S7G2 Ethernet MAC driver (ETHERC0 instance)

License

SPDX-License-Identifier: GPL-2.0-or-later

Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author
Oryx Embedded SARL (www.oryx-embedded.com)
Version
2.4.4

Definition in file s7g2_eth1_driver.h.

Macro Definition Documentation

◆ EDMAC_EDMR_DE

#define EDMAC_EDMR_DE   0x00000040

Definition at line 108 of file s7g2_eth1_driver.h.

◆ EDMAC_EDMR_DL

#define EDMAC_EDMR_DL   0x00000030

Definition at line 109 of file s7g2_eth1_driver.h.

◆ EDMAC_EDMR_DL_16

#define EDMAC_EDMR_DL_16   0x00000000

Definition at line 110 of file s7g2_eth1_driver.h.

◆ EDMAC_EDMR_DL_32

#define EDMAC_EDMR_DL_32   0x00000010

Definition at line 111 of file s7g2_eth1_driver.h.

◆ EDMAC_EDMR_DL_64

#define EDMAC_EDMR_DL_64   0x00000020

Definition at line 112 of file s7g2_eth1_driver.h.

◆ EDMAC_EDMR_SWR

#define EDMAC_EDMR_SWR   0x00000001

Definition at line 113 of file s7g2_eth1_driver.h.

◆ EDMAC_EDRRR_RR

#define EDMAC_EDRRR_RR   0x00000001

Definition at line 119 of file s7g2_eth1_driver.h.

◆ EDMAC_EDTRR_TR

#define EDMAC_EDTRR_TR   0x00000001

Definition at line 116 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_ADEIP

#define EDMAC_EESIPR_ADEIP   0x00800000

Definition at line 150 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_CDIP

#define EDMAC_EESIPR_CDIP   0x00000200

Definition at line 160 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_CERFIP

#define EDMAC_EESIPR_CERFIP   0x00000001

Definition at line 167 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_CNDIP

#define EDMAC_EESIPR_CNDIP   0x00000800

Definition at line 158 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_DLCIP

#define EDMAC_EESIPR_DLCIP   0x00000400

Definition at line 159 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_ECIIP

#define EDMAC_EESIPR_ECIIP   0x00400000

Definition at line 151 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_FRIP

#define EDMAC_EESIPR_FRIP   0x00040000

Definition at line 155 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_PREIP

#define EDMAC_EESIPR_PREIP   0x00000002

Definition at line 166 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_RABTIP

#define EDMAC_EESIPR_RABTIP   0x02000000

Definition at line 148 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_RDEIP

#define EDMAC_EESIPR_RDEIP   0x00020000

Definition at line 156 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_RFCOFIP

#define EDMAC_EESIPR_RFCOFIP   0x01000000

Definition at line 149 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_RFOFIP

#define EDMAC_EESIPR_RFOFIP   0x00010000

Definition at line 157 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_RMAFIP

#define EDMAC_EESIPR_RMAFIP   0x00000080

Definition at line 162 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_RRFIP

#define EDMAC_EESIPR_RRFIP   0x00000010

Definition at line 163 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_RTLFIP

#define EDMAC_EESIPR_RTLFIP   0x00000008

Definition at line 164 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_RTSFIP

#define EDMAC_EESIPR_RTSFIP   0x00000004

Definition at line 165 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_TABTIP

#define EDMAC_EESIPR_TABTIP   0x04000000

Definition at line 147 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_TCIP

#define EDMAC_EESIPR_TCIP   0x00200000

Definition at line 152 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_TDEIP

#define EDMAC_EESIPR_TDEIP   0x00100000

Definition at line 153 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_TFUFIP

#define EDMAC_EESIPR_TFUFIP   0x00080000

Definition at line 154 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_TROIP

#define EDMAC_EESIPR_TROIP   0x00000100

Definition at line 161 of file s7g2_eth1_driver.h.

◆ EDMAC_EESIPR_TWBIP

#define EDMAC_EESIPR_TWBIP   0x40000000

Definition at line 146 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_ADE

#define EDMAC_EESR_ADE   0x00800000

Definition at line 126 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_CD

#define EDMAC_EESR_CD   0x00000200

Definition at line 136 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_CERF

#define EDMAC_EESR_CERF   0x00000001

Definition at line 143 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_CND

#define EDMAC_EESR_CND   0x00000800

Definition at line 134 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_DLC

#define EDMAC_EESR_DLC   0x00000400

Definition at line 135 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_ECI

#define EDMAC_EESR_ECI   0x00400000

Definition at line 127 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_FR

#define EDMAC_EESR_FR   0x00040000

Definition at line 131 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_PRE

#define EDMAC_EESR_PRE   0x00000002

Definition at line 142 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_RABT

#define EDMAC_EESR_RABT   0x02000000

Definition at line 124 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_RDE

#define EDMAC_EESR_RDE   0x00020000

Definition at line 132 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_RFCOF

#define EDMAC_EESR_RFCOF   0x01000000

Definition at line 125 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_RFOF

#define EDMAC_EESR_RFOF   0x00010000

Definition at line 133 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_RMAF

#define EDMAC_EESR_RMAF   0x00000080

Definition at line 138 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_RRF

#define EDMAC_EESR_RRF   0x00000010

Definition at line 139 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_RTLF

#define EDMAC_EESR_RTLF   0x00000008

Definition at line 140 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_RTSF

#define EDMAC_EESR_RTSF   0x00000004

Definition at line 141 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_TABT

#define EDMAC_EESR_TABT   0x04000000

Definition at line 123 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_TC

#define EDMAC_EESR_TC   0x00200000

Definition at line 128 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_TDE

#define EDMAC_EESR_TDE   0x00100000

Definition at line 129 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_TFUF

#define EDMAC_EESR_TFUF   0x00080000

Definition at line 130 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_TRO

#define EDMAC_EESR_TRO   0x00000100

Definition at line 137 of file s7g2_eth1_driver.h.

◆ EDMAC_EESR_TWB

#define EDMAC_EESR_TWB   0x40000000

Definition at line 122 of file s7g2_eth1_driver.h.

◆ EDMAC_FDR_RFD

#define EDMAC_FDR_RFD   0x0000001F

Definition at line 172 of file s7g2_eth1_driver.h.

◆ EDMAC_FDR_RFD_4096

#define EDMAC_FDR_RFD_4096   0x0000000F

Definition at line 173 of file s7g2_eth1_driver.h.

◆ EDMAC_FDR_TFD

#define EDMAC_FDR_TFD   0x00001F00

Definition at line 170 of file s7g2_eth1_driver.h.

◆ EDMAC_FDR_TFD_2048

#define EDMAC_FDR_TFD_2048   0x00000700

Definition at line 171 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RACT

#define EDMAC_RD0_RACT   0x80000000

Definition at line 199 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RDLE

#define EDMAC_RD0_RDLE   0x40000000

Definition at line 200 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFE

#define EDMAC_RD0_RFE   0x08000000

Definition at line 203 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFP_EOF

#define EDMAC_RD0_RFP_EOF   0x10000000

Definition at line 202 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFP_SOF

#define EDMAC_RD0_RFP_SOF   0x20000000

Definition at line 201 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFS_CERF

#define EDMAC_RD0_RFS_CERF   0x00000001

Definition at line 212 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFS_MASK

#define EDMAC_RD0_RFS_MASK   0x0000039F

Definition at line 204 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFS_PRE

#define EDMAC_RD0_RFS_PRE   0x00000002

Definition at line 211 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFS_RABT

#define EDMAC_RD0_RFS_RABT   0x00000100

Definition at line 206 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFS_RFOF

#define EDMAC_RD0_RFS_RFOF   0x00000200

Definition at line 205 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFS_RMAF

#define EDMAC_RD0_RFS_RMAF   0x00000080

Definition at line 207 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFS_RRF

#define EDMAC_RD0_RFS_RRF   0x00000010

Definition at line 208 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFS_RTLF

#define EDMAC_RD0_RFS_RTLF   0x00000008

Definition at line 209 of file s7g2_eth1_driver.h.

◆ EDMAC_RD0_RFS_RTSF

#define EDMAC_RD0_RFS_RTSF   0x00000004

Definition at line 210 of file s7g2_eth1_driver.h.

◆ EDMAC_RD1_RBL

#define EDMAC_RD1_RBL   0xFFFF0000

Definition at line 213 of file s7g2_eth1_driver.h.

◆ EDMAC_RD1_RFL

#define EDMAC_RD1_RFL   0x0000FFFF

Definition at line 214 of file s7g2_eth1_driver.h.

◆ EDMAC_RD2_RBA

#define EDMAC_RD2_RBA   0xFFFFFFFF

Definition at line 215 of file s7g2_eth1_driver.h.

◆ EDMAC_RMCR_RNR

#define EDMAC_RMCR_RNR   0x00000001

Definition at line 176 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TACT

#define EDMAC_TD0_TACT   0x80000000

Definition at line 183 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TDLE

#define EDMAC_TD0_TDLE   0x40000000

Definition at line 184 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TFE

#define EDMAC_TD0_TFE   0x08000000

Definition at line 187 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TFP_EOF

#define EDMAC_TD0_TFP_EOF   0x10000000

Definition at line 186 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TFP_SOF

#define EDMAC_TD0_TFP_SOF   0x20000000

Definition at line 185 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TFS_CD

#define EDMAC_TD0_TFS_CD   0x00000002

Definition at line 193 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TFS_CND

#define EDMAC_TD0_TFS_CND   0x00000008

Definition at line 191 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TFS_DLC

#define EDMAC_TD0_TFS_DLC   0x00000004

Definition at line 192 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TFS_MASK

#define EDMAC_TD0_TFS_MASK   0x0000010F

Definition at line 189 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TFS_TABT

#define EDMAC_TD0_TFS_TABT   0x00000100

Definition at line 190 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TFS_TRO

#define EDMAC_TD0_TFS_TRO   0x00000001

Definition at line 194 of file s7g2_eth1_driver.h.

◆ EDMAC_TD0_TWBI

#define EDMAC_TD0_TWBI   0x04000000

Definition at line 188 of file s7g2_eth1_driver.h.

◆ EDMAC_TD1_TBL

#define EDMAC_TD1_TBL   0xFFFF0000

Definition at line 195 of file s7g2_eth1_driver.h.

◆ EDMAC_TD2_TBA

#define EDMAC_TD2_TBA   0xFFFFFFFF

Definition at line 196 of file s7g2_eth1_driver.h.

◆ EDMAC_TRIMD_TIM

#define EDMAC_TRIMD_TIM   0x00000010

Definition at line 179 of file s7g2_eth1_driver.h.

◆ EDMAC_TRIMD_TIS

#define EDMAC_TRIMD_TIS   0x00000001

Definition at line 180 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_DM

#define ETHERC_ECMR_DM   0x00000002

Definition at line 98 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_ILB

#define ETHERC_ECMR_ILB   0x00000008

Definition at line 96 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_MPDE

#define ETHERC_ECMR_MPDE   0x00000200

Definition at line 93 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_PFR

#define ETHERC_ECMR_PFR   0x00040000

Definition at line 89 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_PRCEF

#define ETHERC_ECMR_PRCEF   0x00001000

Definition at line 92 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_PRM

#define ETHERC_ECMR_PRM   0x00000001

Definition at line 99 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_RE

#define ETHERC_ECMR_RE   0x00000040

Definition at line 94 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_RTM

#define ETHERC_ECMR_RTM   0x00000004

Definition at line 97 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_RXF

#define ETHERC_ECMR_RXF   0x00020000

Definition at line 90 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_TE

#define ETHERC_ECMR_TE   0x00000020

Definition at line 95 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_TPC

#define ETHERC_ECMR_TPC   0x00100000

Definition at line 87 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_TXF

#define ETHERC_ECMR_TXF   0x00010000

Definition at line 91 of file s7g2_eth1_driver.h.

◆ ETHERC_ECMR_ZPF

#define ETHERC_ECMR_ZPF   0x00080000

Definition at line 88 of file s7g2_eth1_driver.h.

◆ ETHERC_PIR_MDC

#define ETHERC_PIR_MDC   0x00000001

Definition at line 105 of file s7g2_eth1_driver.h.

◆ ETHERC_PIR_MDI

#define ETHERC_PIR_MDI   0x00000008

Definition at line 102 of file s7g2_eth1_driver.h.

◆ ETHERC_PIR_MDO

#define ETHERC_PIR_MDO   0x00000004

Definition at line 103 of file s7g2_eth1_driver.h.

◆ ETHERC_PIR_MMD

#define ETHERC_PIR_MMD   0x00000002

Definition at line 104 of file s7g2_eth1_driver.h.

◆ S7G2_ETH1_IRQ_GROUP_PRIORITY

#define S7G2_ETH1_IRQ_GROUP_PRIORITY   12

Definition at line 74 of file s7g2_eth1_driver.h.

◆ S7G2_ETH1_IRQ_PRIORITY_GROUPING

#define S7G2_ETH1_IRQ_PRIORITY_GROUPING   3

Definition at line 67 of file s7g2_eth1_driver.h.

◆ S7G2_ETH1_IRQ_SUB_PRIORITY

#define S7G2_ETH1_IRQ_SUB_PRIORITY   0

Definition at line 81 of file s7g2_eth1_driver.h.

◆ S7G2_ETH1_RX_BUFFER_COUNT

#define S7G2_ETH1_RX_BUFFER_COUNT   6

Definition at line 53 of file s7g2_eth1_driver.h.

◆ S7G2_ETH1_RX_BUFFER_SIZE

#define S7G2_ETH1_RX_BUFFER_SIZE   1536

Definition at line 60 of file s7g2_eth1_driver.h.

◆ S7G2_ETH1_TX_BUFFER_COUNT

#define S7G2_ETH1_TX_BUFFER_COUNT   3

Definition at line 39 of file s7g2_eth1_driver.h.

◆ S7G2_ETH1_TX_BUFFER_SIZE

#define S7G2_ETH1_TX_BUFFER_SIZE   1536

Definition at line 46 of file s7g2_eth1_driver.h.

Function Documentation

◆ s7g2Eth1DisableIrq()

void s7g2Eth1DisableIrq ( NetInterface *  interface)

Disable interrupts.

Parameters
[in]interfaceUnderlying network interface

Definition at line 411 of file s7g2_eth1_driver.c.

◆ s7g2Eth1EnableIrq()

void s7g2Eth1EnableIrq ( NetInterface *  interface)

Enable interrupts.

Parameters
[in]interfaceUnderlying network interface

Definition at line 383 of file s7g2_eth1_driver.c.

◆ s7g2Eth1EventHandler()

void s7g2Eth1EventHandler ( NetInterface *  interface)

S7G2 Ethernet MAC event handler.

Parameters
[in]interfaceUnderlying network interface

Definition at line 491 of file s7g2_eth1_driver.c.

◆ s7g2Eth1Init()

error_t s7g2Eth1Init ( NetInterface *  interface)

S7G2 Ethernet MAC initialization.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 115 of file s7g2_eth1_driver.c.

◆ s7g2Eth1InitDmaDesc()

void s7g2Eth1InitDmaDesc ( NetInterface *  interface)

Initialize DMA descriptor lists.

Parameters
[in]interfaceUnderlying network interface

Definition at line 302 of file s7g2_eth1_driver.c.

◆ s7g2Eth1InitGpio()

void s7g2Eth1InitGpio ( NetInterface *  interface)

GPIO configuration.

Parameters
[in]interfaceUnderlying network interface

Definition at line 220 of file s7g2_eth1_driver.c.

◆ s7g2Eth1ReadPhyReg()

uint16_t s7g2Eth1ReadPhyReg ( uint8_t  opcode,
uint8_t  phyAddr,
uint8_t  regAddr 
)

Read PHY register.

Parameters
[in]opcodeAccess type (2 bits)
[in]phyAddrPHY address (5 bits)
[in]regAddrRegister address (5 bits)
Returns
Register value

Definition at line 800 of file s7g2_eth1_driver.c.

◆ s7g2Eth1ReadSmi()

uint32_t s7g2Eth1ReadSmi ( uint_t  length)

SMI read operation.

Parameters
[in]lengthNumber of bits to be read
Returns
Data resulting from the MDIO read operation

Definition at line 873 of file s7g2_eth1_driver.c.

◆ s7g2Eth1ReceivePacket()

error_t s7g2Eth1ReceivePacket ( NetInterface *  interface)

Receive a packet.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 584 of file s7g2_eth1_driver.c.

◆ s7g2Eth1SendPacket()

error_t s7g2Eth1SendPacket ( NetInterface *  interface,
const NetBuffer *  buffer,
size_t  offset,
NetTxAncillary *  ancillary 
)

Send a packet.

Parameters
[in]interfaceUnderlying network interface
[in]bufferMulti-part buffer containing the data to send
[in]offsetOffset to the first data byte
[in]ancillaryAdditional options passed to the stack along with the packet
Returns
Error code

Definition at line 516 of file s7g2_eth1_driver.c.

◆ s7g2Eth1Tick()

void s7g2Eth1Tick ( NetInterface *  interface)

S7G2 Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters
[in]interfaceUnderlying network interface

Definition at line 358 of file s7g2_eth1_driver.c.

◆ s7g2Eth1UpdateMacAddrFilter()

error_t s7g2Eth1UpdateMacAddrFilter ( NetInterface *  interface)

Configure MAC address filtering.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 662 of file s7g2_eth1_driver.c.

◆ s7g2Eth1UpdateMacConfig()

error_t s7g2Eth1UpdateMacConfig ( NetInterface *  interface)

Adjust MAC configuration parameters for proper operation.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 727 of file s7g2_eth1_driver.c.

◆ s7g2Eth1WritePhyReg()

void s7g2Eth1WritePhyReg ( uint8_t  opcode,
uint8_t  phyAddr,
uint8_t  regAddr,
uint16_t  data 
)

Write PHY register.

Parameters
[in]opcodeAccess type (2 bits)
[in]phyAddrPHY address (5 bits)
[in]regAddrRegister address (5 bits)
[in]dataRegister value

Definition at line 770 of file s7g2_eth1_driver.c.

◆ s7g2Eth1WriteSmi()

void s7g2Eth1WriteSmi ( uint32_t  data,
uint_t  length 
)

SMI write operation.

Parameters
[in]dataRaw data to be written
[in]lengthNumber of bits to be written

Definition at line 833 of file s7g2_eth1_driver.c.

Variable Documentation

◆ s7g2Eth1Driver

const NicDriver s7g2Eth1Driver
extern

S7G2 Ethernet MAC driver (ETHERC0 instance)

Definition at line 88 of file s7g2_eth1_driver.c.