sama5d3_geth_driver.h
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1 /**
2  * @file sama5d3_geth_driver.h
3  * @brief SAMA5D3 Gigabit Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 #ifndef _SAMA5D3_GETH_DRIVER_H
32 #define _SAMA5D3_GETH_DRIVER_H
33 
34 //Number of TX buffers
35 #ifndef SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT
36  #define SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT 2
37 #elif (SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT != 2)
38  #error SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT parameter is not valid
39 #endif
40 
41 //TX buffer size
42 #ifndef SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE
43  #define SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE 1536
44 #elif (SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE != 1536)
45  #error SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE parameter is not valid
46 #endif
47 
48 //Number of RX buffers
49 #ifndef SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT
50  #define SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT 96
51 #elif (SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT < 12)
52  #error SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT parameter is not valid
53 #endif
54 
55 //RX buffer size
56 #ifndef SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE
57  #define SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE 128
58 #elif (SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE != 128)
59  #error SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE parameter is not valid
60 #endif
61 
62 //Gigabit Ethernet interrupt priority
63 #ifndef SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY
64  #define SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY 0
65 #elif (SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY < 0)
66  #error SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY parameter is not valid
67 #endif
68 
69 //RGMII signals
70 #define GMAC_RGMII_MASK (PIO_PB18A_G125CK | \
71  PIO_PB17A_GMDIO | PIO_PB16A_GMDC | PIO_PB13A_GRXER | \
72  PIO_PB12A_GRXDV | PIO_PB11A_GRXCK | PIO_PB9A_GTXEN | \
73  PIO_PB8A_GTXCK | PIO_PB7A_GRX3 | PIO_PB6A_GRX2 | \
74  PIO_PB5A_GRX1 | PIO_PB4A_GRX0 | PIO_PB3A_GTX3 | \
75  PIO_PB2A_GTX2 | PIO_PB1A_GTX1 | PIO_PB0A_GTX0)
76 
77 //TX buffer descriptor flags
78 #define GMAC_TX_USED 0x80000000
79 #define GMAC_TX_WRAP 0x40000000
80 #define GMAC_TX_RLE_ERROR 0x20000000
81 #define GMAC_TX_UNDERRUN_ERROR 0x10000000
82 #define GMAC_TX_AHB_ERROR 0x08000000
83 #define GMAC_TX_LATE_COL_ERROR 0x04000000
84 #define GMAC_TX_CHECKSUM_ERROR 0x00700000
85 #define GMAC_TX_NO_CRC 0x00010000
86 #define GMAC_TX_LAST 0x00008000
87 #define GMAC_TX_LENGTH 0x00003FFF
88 
89 //RX buffer descriptor flags
90 #define GMAC_RX_ADDRESS 0xFFFFFFFC
91 #define GMAC_RX_WRAP 0x00000002
92 #define GMAC_RX_OWNERSHIP 0x00000001
93 #define GMAC_RX_BROADCAST 0x80000000
94 #define GMAC_RX_MULTICAST_HASH 0x40000000
95 #define GMAC_RX_UNICAST_HASH 0x20000000
96 #define GMAC_RX_SAR 0x08000000
97 #define GMAC_RX_SAR_MASK 0x06000000
98 #define GMAC_RX_TYPE_ID 0x01000000
99 #define GMAC_RX_SNAP 0x01000000
100 #define GMAC_RX_TYPE_ID_MASK 0x00C00000
101 #define GMAC_RX_CHECKSUM_VALID 0x00C00000
102 #define GMAC_RX_VLAN_TAG 0x00200000
103 #define GMAC_RX_PRIORITY_TAG 0x00100000
104 #define GMAC_RX_VLAN_PRIORITY 0x000E0000
105 #define GMAC_RX_CFI 0x00010000
106 #define GMAC_RX_EOF 0x00008000
107 #define GMAC_RX_SOF 0x00004000
108 #define GMAC_RX_LENGTH_MSB 0x00002000
109 #define GMAC_RX_BAD_FCS 0x00002000
110 #define GMAC_RX_LENGTH 0x00001FFF
111 
112 //C++ guard
113 #ifdef __cplusplus
114  extern "C" {
115 #endif
116 
117 
118 /**
119  * @brief Transmit buffer descriptor
120  **/
121 
122 typedef struct
123 {
124  uint32_t address;
125  uint32_t status;
127 
128 
129 /**
130  * @brief Receive buffer descriptor
131  **/
132 
133 typedef struct
134 {
135  uint32_t address;
136  uint32_t status;
138 
139 
140 //SAMA5D3 Gigabit Ethernet MAC driver
142 
143 //SAMA5D3 Gigabit Ethernet MAC related functions
145 void sama5d3GigabitEthInitGpio(NetInterface *interface);
147 
148 void sama5d3GigabitEthTick(NetInterface *interface);
149 
152 void sama5d3GigabitEthIrqHandler(void);
154 
156  const NetBuffer *buffer, size_t offset);
157 
159 
162 
163 void sama5d3GigabitEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
164  uint8_t regAddr, uint16_t data);
165 
166 uint16_t sama5d3GigabitEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
167  uint8_t regAddr);
168 
169 //C++ guard
170 #ifdef __cplusplus
171  }
172 #endif
173 
174 #endif
Transmit buffer descriptor.
void sama5d3GigabitEthTick(NetInterface *interface)
SAMA5D3 Gigabit Ethernet MAC timer handler.
error_t sama5d3GigabitEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void sama5d3GigabitEthEventHandler(NetInterface *interface)
SAMA5D3 Gigabit Ethernet MAC event handler.
Receive buffer descriptor.
error_t sama5d3GigabitEthInit(NetInterface *interface)
SAMA5D3 Gigabit Ethernet MAC initialization.
void sama5d3GigabitEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint8_t opcode
Definition: dns_common.h:172
error_t sama5d3GigabitEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
error_t sama5d3GigabitEthReceivePacket(NetInterface *interface)
Receive a packet.
error_t sama5d3GigabitEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void sama5d3GigabitEthEnableIrq(NetInterface *interface)
Enable interrupts.
NIC driver.
Definition: nic.h:179
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void sama5d3GigabitEthIrqHandler(void)
SAMA5D3 Gigabit Ethernet MAC interrupt service routine.
void sama5d3GigabitEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint16_t regAddr
const NicDriver sama5d3GigabitEthDriver
SAMA5D3 Gigabit Ethernet MAC driver.
error_t
Error codes.
Definition: error.h:42
uint16_t sama5d3GigabitEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
void sama5d3GigabitEthDisableIrq(NetInterface *interface)
Disable interrupts.
void sama5d3GigabitEthInitGpio(NetInterface *interface)