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31 #ifndef _SAME53_ETH_DRIVER_H
32 #define _SAME53_ETH_DRIVER_H
35 #ifndef SAME53_ETH_TX_BUFFER_COUNT
36 #define SAME53_ETH_TX_BUFFER_COUNT 3
37 #elif (SAME53_ETH_TX_BUFFER_COUNT < 1)
38 #error SAME53_ETH_TX_BUFFER_COUNT parameter is not valid
42 #ifndef SAME53_ETH_TX_BUFFER_SIZE
43 #define SAME53_ETH_TX_BUFFER_SIZE 1536
44 #elif (SAME53_ETH_TX_BUFFER_SIZE != 1536)
45 #error SAME53_ETH_TX_BUFFER_SIZE parameter is not valid
49 #ifndef SAME53_ETH_RX_BUFFER_COUNT
50 #define SAME53_ETH_RX_BUFFER_COUNT 72
51 #elif (SAME53_ETH_RX_BUFFER_COUNT < 12)
52 #error SAME53_ETH_RX_BUFFER_COUNT parameter is not valid
56 #ifndef SAME53_ETH_RX_BUFFER_SIZE
57 #define SAME53_ETH_RX_BUFFER_SIZE 128
58 #elif (SAME53_ETH_RX_BUFFER_SIZE != 128)
59 #error SAME53_ETH_RX_BUFFER_SIZE parameter is not valid
63 #ifndef SAME53_ETH_IRQ_PRIORITY_GROUPING
64 #define SAME53_ETH_IRQ_PRIORITY_GROUPING 4
65 #elif (SAME53_ETH_IRQ_PRIORITY_GROUPING < 0)
66 #error SAME53_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #ifndef SAME53_ETH_IRQ_GROUP_PRIORITY
71 #define SAME53_ETH_IRQ_GROUP_PRIORITY 6
72 #elif (SAME53_ETH_IRQ_GROUP_PRIORITY < 0)
73 #error SAME53_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #ifndef SAME53_ETH_IRQ_SUB_PRIORITY
78 #define SAME53_ETH_IRQ_SUB_PRIORITY 0
79 #elif (SAME53_ETH_IRQ_SUB_PRIORITY < 0)
80 #error SAME53_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #define GMAC_TX_USED 0x80000000
85 #define GMAC_TX_WRAP 0x40000000
86 #define GMAC_TX_RLE_ERROR 0x20000000
87 #define GMAC_TX_UNDERRUN_ERROR 0x10000000
88 #define GMAC_TX_AHB_ERROR 0x08000000
89 #define GMAC_TX_LATE_COL_ERROR 0x04000000
90 #define GMAC_TX_CHECKSUM_ERROR 0x00700000
91 #define GMAC_TX_NO_CRC 0x00010000
92 #define GMAC_TX_LAST 0x00008000
93 #define GMAC_TX_LENGTH 0x00003FFF
96 #define GMAC_RX_ADDRESS 0xFFFFFFFC
97 #define GMAC_RX_WRAP 0x00000002
98 #define GMAC_RX_OWNERSHIP 0x00000001
99 #define GMAC_RX_BROADCAST 0x80000000
100 #define GMAC_RX_MULTICAST_HASH 0x40000000
101 #define GMAC_RX_UNICAST_HASH 0x20000000
102 #define GMAC_RX_SAR 0x08000000
103 #define GMAC_RX_SAR_MASK 0x06000000
104 #define GMAC_RX_TYPE_ID 0x01000000
105 #define GMAC_RX_SNAP 0x01000000
106 #define GMAC_RX_TYPE_ID_MASK 0x00C00000
107 #define GMAC_RX_CHECKSUM_VALID 0x00C00000
108 #define GMAC_RX_VLAN_TAG 0x00200000
109 #define GMAC_RX_PRIORITY_TAG 0x00100000
110 #define GMAC_RX_VLAN_PRIORITY 0x000E0000
111 #define GMAC_RX_CFI 0x00010000
112 #define GMAC_RX_EOF 0x00008000
113 #define GMAC_RX_SOF 0x00004000
114 #define GMAC_RX_LENGTH_MSB 0x00002000
115 #define GMAC_RX_BAD_FCS 0x00002000
116 #define GMAC_RX_LENGTH 0x00001FFF
error_t same53EthInit(NetInterface *interface)
SAME53 Ethernet MAC initialization.
void same53EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void same53EthTick(NetInterface *interface)
SAME53 Ethernet MAC timer handler.
error_t same53EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Transmit buffer descriptor.
Structure describing a buffer that spans multiple chunks.
Receive buffer descriptor.
void same53EthEnableIrq(NetInterface *interface)
Enable interrupts.
void same53EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
error_t same53EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void same53EthEventHandler(NetInterface *interface)
SAME53 Ethernet MAC event handler.
error_t same53EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint16_t same53EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void same53EthInitGpio(NetInterface *interface)
GPIO configuration.
const NicDriver same53EthDriver
SAME53 Ethernet MAC driver.
error_t same53EthReceivePacket(NetInterface *interface)
Receive a packet.
void same53EthDisableIrq(NetInterface *interface)
Disable interrupts.