same70_eth_driver.h
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1 /**
2  * @file same70_eth_driver.h
3  * @brief SAME70 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _SAME70_ETH_DRIVER_H
32 #define _SAME70_ETH_DRIVER_H
33 
34 //Number of TX buffers
35 #ifndef SAME70_ETH_TX_BUFFER_COUNT
36  #define SAME70_ETH_TX_BUFFER_COUNT 4
37 #elif (SAME70_ETH_TX_BUFFER_COUNT < 1)
38  #error SAME70_ETH_TX_BUFFER_COUNT parameter is not valid
39 #endif
40 
41 //TX buffer size
42 #ifndef SAME70_ETH_TX_BUFFER_SIZE
43  #define SAME70_ETH_TX_BUFFER_SIZE 1536
44 #elif (SAME70_ETH_TX_BUFFER_SIZE != 1536)
45  #error SAME70_ETH_TX_BUFFER_SIZE parameter is not valid
46 #endif
47 
48 //Number of RX buffers
49 #ifndef SAME70_ETH_RX_BUFFER_COUNT
50  #define SAME70_ETH_RX_BUFFER_COUNT 96
51 #elif (SAME70_ETH_RX_BUFFER_COUNT < 12)
52  #error SAME70_ETH_RX_BUFFER_COUNT parameter is not valid
53 #endif
54 
55 //RX buffer size
56 #ifndef SAME70_ETH_RX_BUFFER_SIZE
57  #define SAME70_ETH_RX_BUFFER_SIZE 128
58 #elif (SAME70_ETH_RX_BUFFER_SIZE != 128)
59  #error SAME70_ETH_RX_BUFFER_SIZE parameter is not valid
60 #endif
61 
62 //Number of dummy buffers
63 #ifndef SAME70_ETH_DUMMY_BUFFER_COUNT
64  #define SAME70_ETH_DUMMY_BUFFER_COUNT 2
65 #elif (SAME70_ETH_DUMMY_BUFFER_COUNT < 1)
66  #error SAME70_ETH_DUMMY_BUFFER_COUNT parameter is not valid
67 #endif
68 
69 //Dummy buffer size
70 #ifndef SAME70_ETH_DUMMY_BUFFER_SIZE
71  #define SAME70_ETH_DUMMY_BUFFER_SIZE 128
72 #elif (SAME70_ETH_DUMMY_BUFFER_SIZE != 128)
73  #error SAME70_ETH_DUMMY_BUFFER_SIZE parameter is not valid
74 #endif
75 
76 //Interrupt priority grouping
77 #ifndef SAME70_ETH_IRQ_PRIORITY_GROUPING
78  #define SAME70_ETH_IRQ_PRIORITY_GROUPING 4
79 #elif (SAME70_ETH_IRQ_PRIORITY_GROUPING < 0)
80  #error SAME70_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
81 #endif
82 
83 //Ethernet interrupt group priority
84 #ifndef SAME70_ETH_IRQ_GROUP_PRIORITY
85  #define SAME70_ETH_IRQ_GROUP_PRIORITY 6
86 #elif (SAME70_ETH_IRQ_GROUP_PRIORITY < 0)
87  #error SAME70_ETH_IRQ_GROUP_PRIORITY parameter is not valid
88 #endif
89 
90 //Ethernet interrupt subpriority
91 #ifndef SAME70_ETH_IRQ_SUB_PRIORITY
92  #define SAME70_ETH_IRQ_SUB_PRIORITY 0
93 #elif (SAME70_ETH_IRQ_SUB_PRIORITY < 0)
94  #error SAME70_ETH_IRQ_SUB_PRIORITY parameter is not valid
95 #endif
96 
97 //Backward compatibility
98 #ifndef PIO_PD9A_GMDIO
99  #define PIO_PD9A_GMDIO PIO_PD9A_GMAC_GMDIO
100  #define PIO_PD8A_GMDC PIO_PD8A_GMAC_GMDC
101  #define PIO_PD7A_GRXER PIO_PD7A_GMAC_GRXER
102  #define PIO_PD6A_GRX1 PIO_PD6A_GMAC_GRX1
103  #define PIO_PD5A_GRX0 PIO_PD5A_GMAC_GRX0
104  #define PIO_PD4A_GRXDV PIO_PD4A_GMAC_GRXDV
105  #define PIO_PD3A_GTX1 PIO_PD3A_GMAC_GTX1
106  #define PIO_PD2A_GTX0 PIO_PD2A_GMAC_GTX0
107  #define PIO_PD1A_GTXEN PIO_PD1A_GMAC_GTXEN
108  #define PIO_PD0A_GTXCK PIO_PD0A_GMAC_GTXCK
109  #define GMAC_SA GmacSa
110 #endif
111 
112 //RMII signals
113 #define GMAC_RMII_MASK (PIO_PD9A_GMDIO | PIO_PD8A_GMDC | \
114  PIO_PD7A_GRXER | PIO_PD6A_GRX1 | PIO_PD5A_GRX0 | PIO_PD4A_GRXDV | \
115  PIO_PD3A_GTX1 | PIO_PD2A_GTX0 | PIO_PD1A_GTXEN | PIO_PD0A_GTXCK)
116 
117 //TX buffer descriptor flags
118 #define GMAC_TX_USED 0x80000000
119 #define GMAC_TX_WRAP 0x40000000
120 #define GMAC_TX_RLE_ERROR 0x20000000
121 #define GMAC_TX_UNDERRUN_ERROR 0x10000000
122 #define GMAC_TX_AHB_ERROR 0x08000000
123 #define GMAC_TX_LATE_COL_ERROR 0x04000000
124 #define GMAC_TX_CHECKSUM_ERROR 0x00700000
125 #define GMAC_TX_NO_CRC 0x00010000
126 #define GMAC_TX_LAST 0x00008000
127 #define GMAC_TX_LENGTH 0x00003FFF
128 
129 //RX buffer descriptor flags
130 #define GMAC_RX_ADDRESS 0xFFFFFFFC
131 #define GMAC_RX_WRAP 0x00000002
132 #define GMAC_RX_OWNERSHIP 0x00000001
133 #define GMAC_RX_BROADCAST 0x80000000
134 #define GMAC_RX_MULTICAST_HASH 0x40000000
135 #define GMAC_RX_UNICAST_HASH 0x20000000
136 #define GMAC_RX_SAR 0x08000000
137 #define GMAC_RX_SAR_MASK 0x06000000
138 #define GMAC_RX_TYPE_ID 0x01000000
139 #define GMAC_RX_SNAP 0x01000000
140 #define GMAC_RX_TYPE_ID_MASK 0x00C00000
141 #define GMAC_RX_CHECKSUM_VALID 0x00C00000
142 #define GMAC_RX_VLAN_TAG 0x00200000
143 #define GMAC_RX_PRIORITY_TAG 0x00100000
144 #define GMAC_RX_VLAN_PRIORITY 0x000E0000
145 #define GMAC_RX_CFI 0x00010000
146 #define GMAC_RX_EOF 0x00008000
147 #define GMAC_RX_SOF 0x00004000
148 #define GMAC_RX_LENGTH_MSB 0x00002000
149 #define GMAC_RX_BAD_FCS 0x00002000
150 #define GMAC_RX_LENGTH 0x00001FFF
151 
152 //C++ guard
153 #ifdef __cplusplus
154 extern "C" {
155 #endif
156 
157 
158 /**
159  * @brief Transmit buffer descriptor
160  **/
161 
162 typedef struct
163 {
164  uint32_t address;
165  uint32_t status;
167 
168 
169 /**
170  * @brief Receive buffer descriptor
171  **/
172 
173 typedef struct
174 {
175  uint32_t address;
176  uint32_t status;
178 
179 
180 //SAME70 Ethernet MAC driver
181 extern const NicDriver same70EthDriver;
182 
183 //SAME70 Ethernet MAC related functions
185 void same70EthInitGpio(NetInterface *interface);
186 void same70EthInitBufferDesc(NetInterface *interface);
187 
188 void same70EthTick(NetInterface *interface);
189 
190 void same70EthEnableIrq(NetInterface *interface);
191 void same70EthDisableIrq(NetInterface *interface);
192 void same70EthEventHandler(NetInterface *interface);
193 
195  const NetBuffer *buffer, size_t offset);
196 
198 
201 
202 void same70EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
203  uint8_t regAddr, uint16_t data);
204 
205 uint16_t same70EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
206  uint8_t regAddr);
207 
208 //C++ guard
209 #ifdef __cplusplus
210 }
211 #endif
212 
213 #endif
error_t same70EthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t opcode
Definition: dns_common.h:172
const NicDriver same70EthDriver
SAME70 Ethernet MAC driver.
void same70EthTick(NetInterface *interface)
SAME70 Ethernet MAC timer handler.
void same70EthDisableIrq(NetInterface *interface)
Disable interrupts.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void same70EthEventHandler(NetInterface *interface)
SAME70 Ethernet MAC event handler.
void same70EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
error_t
Error codes.
Definition: error.h:42
void same70EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define NetInterface
Definition: net.h:36
uint16_t same70EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Transmit buffer descriptor.
error_t same70EthInit(NetInterface *interface)
SAME70 Ethernet MAC initialization.
void same70EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t same70EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Receive buffer descriptor.
uint16_t regAddr
void same70EthInitGpio(NetInterface *interface)
error_t same70EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t same70EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179