stm32mp13xx_eth2_driver.h
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1 /**
2  * @file stm32mp13xx_eth2_driver.h
3  * @brief STM32MP13 Gigabit Ethernet MAC driver (ETH2 instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.4
29  **/
30 
31 #ifndef _STM32MP13XX_ETH2_DRIVER_H
32 #define _STM32MP13XX_ETH2_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef STM32MP13XX_ETH2_TX_BUFFER_COUNT
39  #define STM32MP13XX_ETH2_TX_BUFFER_COUNT 8
40 #elif (STM32MP13XX_ETH2_TX_BUFFER_COUNT < 1)
41  #error STM32MP13XX_ETH2_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef STM32MP13XX_ETH2_TX_BUFFER_SIZE
46  #define STM32MP13XX_ETH2_TX_BUFFER_SIZE 1536
47 #elif (STM32MP13XX_ETH2_TX_BUFFER_SIZE != 1536)
48  #error STM32MP13XX_ETH2_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef STM32MP13XX_ETH2_RX_BUFFER_COUNT
53  #define STM32MP13XX_ETH2_RX_BUFFER_COUNT 8
54 #elif (STM32MP13XX_ETH2_RX_BUFFER_COUNT < 1)
55  #error STM32MP13XX_ETH2_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef STM32MP13XX_ETH2_RX_BUFFER_SIZE
60  #define STM32MP13XX_ETH2_RX_BUFFER_SIZE 1536
61 #elif (STM32MP13XX_ETH2_RX_BUFFER_SIZE != 1536)
62  #error STM32MP13XX_ETH2_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Ethernet interrupt priority
66 #ifndef STM32MP13XX_ETH2_IRQ_PRIORITY
67  #define STM32MP13XX_ETH2_IRQ_PRIORITY 25
68 #elif (STM32MP13XX_ETH2_IRQ_PRIORITY < 0)
69  #error STM32MP13XX_ETH2_IRQ_PRIORITY parameter is not valid
70 #endif
71 
72 //Name of the section where to place DMA buffers
73 #ifndef STM32MP13XX_ETH2_RAM_SECTION
74  #define STM32MP13XX_ETH2_RAM_SECTION ".sysram"
75 #endif
76 
77 //Register access macros
78 #define ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk)
79 #define ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk)
80 #define ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk)
81 #define ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk)
82 #define ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk)
83 #define ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk)
84 #define ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk)
85 #define ETH_DMAMR_TXPR_Val(n) (((n) << ETH_DMAMR_TXPR_Pos) & ETH_DMAMR_TXPR_Msk)
86 #define ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk)
87 #define ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk)
88 #define ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk)
89 #define ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk)
90 
91 //Transmit normal descriptor (read format)
92 #define ETH_TDES0_BUF1AP 0xFFFFFFFF
93 #define ETH_TDES1_BUF2AP 0xFFFFFFFF
94 #define ETH_TDES2_IOC 0x80000000
95 #define ETH_TDES2_TTSE 0x40000000
96 #define ETH_TDES2_B2L 0x3FFF0000
97 #define ETH_TDES2_VTIR 0x0000C000
98 #define ETH_TDES2_B1L 0x00003FFF
99 #define ETH_TDES3_OWN 0x80000000
100 #define ETH_TDES3_CTXT 0x40000000
101 #define ETH_TDES3_FD 0x20000000
102 #define ETH_TDES3_LD 0x10000000
103 #define ETH_TDES3_CPC 0x0C000000
104 #define ETH_TDES3_SAIC 0x03800000
105 #define ETH_TDES3_THL 0x00780000
106 #define ETH_TDES3_TSE 0x00040000
107 #define ETH_TDES3_CIC 0x00030000
108 #define ETH_TDES3_FL 0x00007FFF
109 
110 //Transmit normal descriptor (write-back format)
111 #define ETH_TDES0_TTSL 0xFFFFFFFF
112 #define ETH_TDES1_TTSH 0xFFFFFFFF
113 #define ETH_TDES3_OWN 0x80000000
114 #define ETH_TDES3_CTXT 0x40000000
115 #define ETH_TDES3_FD 0x20000000
116 #define ETH_TDES3_LD 0x10000000
117 #define ETH_TDES3_TTSS 0x00020000
118 #define ETH_TDES3_ES 0x00008000
119 #define ETH_TDES3_JT 0x00004000
120 #define ETH_TDES3_FF 0x00002000
121 #define ETH_TDES3_PCE 0x00001000
122 #define ETH_TDES3_LOC 0x00000800
123 #define ETH_TDES3_NC 0x00000400
124 #define ETH_TDES3_LC 0x00000200
125 #define ETH_TDES3_EC 0x00000100
126 #define ETH_TDES3_CC 0x000000F0
127 #define ETH_TDES3_ED 0x00000008
128 #define ETH_TDES3_UF 0x00000004
129 #define ETH_TDES3_DB 0x00000002
130 #define ETH_TDES3_IHE 0x00000001
131 
132 //Transmit context descriptor
133 #define ETH_TDES0_TTSL 0xFFFFFFFF
134 #define ETH_TDES1_TTSH 0xFFFFFFFF
135 #define ETH_TDES2_IVT 0xFFFF0000
136 #define ETH_TDES2_MSS 0x00003FFF
137 #define ETH_TDES3_OWN 0x80000000
138 #define ETH_TDES3_CTXT 0x40000000
139 #define ETH_TDES3_OSTC 0x08000000
140 #define ETH_TDES3_TCMSSV 0x04000000
141 #define ETH_TDES3_CDE 0x00800000
142 #define ETH_TDES3_IVLTV 0x00020000
143 #define ETH_TDES3_VLTV 0x00010000
144 #define ETH_TDES3_VT 0x0000FFFF
145 
146 //Receive normal descriptor (read format)
147 #define ETH_RDES0_BUF1AP 0xFFFFFFFF
148 #define ETH_RDES2_BUF2AP 0xFFFFFFFF
149 #define ETH_RDES3_OWN 0x80000000
150 #define ETH_RDES3_IOC 0x40000000
151 #define ETH_RDES3_BUF2V 0x02000000
152 #define ETH_RDES3_BUF1V 0x01000000
153 
154 //Receive normal descriptor (write-back format)
155 #define ETH_RDES0_IVT 0xFFFF0000
156 #define ETH_RDES0_OVT 0x0000FFFF
157 #define ETH_RDES1_OPC 0xFFFF0000
158 #define ETH_RDES1_TD 0x00008000
159 #define ETH_RDES1_TSA 0x00004000
160 #define ETH_RDES1_PV 0x00002000
161 #define ETH_RDES1_PFT 0x00001000
162 #define ETH_RDES1_PMT 0x00000F00
163 #define ETH_RDES1_IPCE 0x00000080
164 #define ETH_RDES1_IPCB 0x00000040
165 #define ETH_RDES1_IPV6 0x00000020
166 #define ETH_RDES1_IPV4 0x00000010
167 #define ETH_RDES1_IPHE 0x00000008
168 #define ETH_RDES1_PT 0x00000007
169 #define ETH_RDES2_L3L4FM 0xE0000000
170 #define ETH_RDES2_L4FM 0x10000000
171 #define ETH_RDES2_L3FM 0x08000000
172 #define ETH_RDES2_MADRM 0x07F80000
173 #define ETH_RDES2_HF 0x00040000
174 #define ETH_RDES2_DAF 0x00020000
175 #define ETH_RDES2_SAF 0x00010000
176 #define ETH_RDES2_VF 0x00008000
177 #define ETH_RDES2_ARPRN 0x00000400
178 #define ETH_RDES3_OWN 0x80000000
179 #define ETH_RDES3_CTXT 0x40000000
180 #define ETH_RDES3_FD 0x20000000
181 #define ETH_RDES3_LD 0x10000000
182 #define ETH_RDES3_RS2V 0x08000000
183 #define ETH_RDES3_RS1V 0x04000000
184 #define ETH_RDES3_RS0V 0x02000000
185 #define ETH_RDES3_CE 0x01000000
186 #define ETH_RDES3_GP 0x00800000
187 #define ETH_RDES3_RWT 0x00400000
188 #define ETH_RDES3_OE 0x00200000
189 #define ETH_RDES3_RE 0x00100000
190 #define ETH_RDES3_DE 0x00080000
191 #define ETH_RDES3_LT 0x00070000
192 #define ETH_RDES3_ES 0x00008000
193 #define ETH_RDES3_PL 0x00007FFF
194 
195 //Receive context descriptor
196 #define ETH_RDES0_RTSL 0xFFFFFFFF
197 #define ETH_RDES1_RTSH 0xFFFFFFFF
198 #define ETH_RDES3_OWN 0x80000000
199 #define ETH_RDES3_CTXT 0x40000000
200 
201 //C++ guard
202 #ifdef __cplusplus
203 extern "C" {
204 #endif
205 
206 
207 /**
208  * @brief Transmit descriptor
209  **/
210 
211 typedef struct
212 {
213  uint32_t tdes0;
214  uint32_t tdes1;
215  uint32_t tdes2;
216  uint32_t tdes3;
218 
219 
220 /**
221  * @brief Receive descriptor
222  **/
223 
224 typedef struct
225 {
226  uint32_t rdes0;
227  uint32_t rdes1;
228  uint32_t rdes2;
229  uint32_t rdes3;
231 
232 
233 //STM32MP13 Ethernet MAC driver (ETH2 instance)
234 extern const NicDriver stm32mp13xxEth2Driver;
235 
236 //STM32MP13 Ethernet MAC related functions
238 void stm32mp13xxEth2InitGpio(NetInterface *interface);
240 
241 void stm32mp13xxEth2Tick(NetInterface *interface);
242 
243 void stm32mp13xxEth2EnableIrq(NetInterface *interface);
244 void stm32mp13xxEth2DisableIrq(NetInterface *interface);
246 
248  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
249 
251 
254 
255 void stm32mp13xxEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr,
256  uint8_t regAddr, uint16_t data);
257 
258 uint16_t stm32mp13xxEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
259  uint8_t regAddr);
260 
261 uint32_t stm32mp13xxEth2CalcCrc(const void *data, size_t length);
262 
263 //C++ guard
264 #ifdef __cplusplus
265 }
266 #endif
267 
268 #endif
error_t stm32mp13xxEth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint8_t opcode
Definition: dns_common.h:188
const NicDriver stm32mp13xxEth2Driver
STM32MP13 Ethernet MAC driver (ETH2 instance)
error_t stm32mp13xxEth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
uint8_t data[]
Definition: ethernet.h:222
error_t
Error codes.
Definition: error.h:43
error_t stm32mp13xxEth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
#define NetInterface
Definition: net.h:36
void stm32mp13xxEth2EventHandler(NetInterface *interface)
STM32MP13 Ethernet MAC event handler.
#define NetTxAncillary
Definition: net_misc.h:36
uint8_t length
Definition: tcp.h:368
void stm32mp13xxEth2DisableIrq(NetInterface *interface)
Disable interrupts.
error_t stm32mp13xxEth2ReceivePacket(NetInterface *interface)
Receive a packet.
uint32_t stm32mp13xxEth2CalcCrc(const void *data, size_t length)
CRC calculation.
void stm32mp13xxEth2InitGpio(NetInterface *interface)
GPIO configuration.
uint16_t regAddr
void stm32mp13xxEth2EnableIrq(NetInterface *interface)
Enable interrupts.
void stm32mp13xxEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Network interface controller abstraction layer.
void stm32mp13xxEth2InitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t stm32mp13xxEth2Init(NetInterface *interface)
STM32MP13 Ethernet MAC initialization.
uint16_t stm32mp13xxEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void stm32mp13xxEth2Tick(NetInterface *interface)
STM32MP13 Ethernet MAC timer handler.
NIC driver.
Definition: nic.h:286