stm32mp2xx_eth2_driver.h
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1 /**
2  * @file stm32mp2xx_eth2_driver.h
3  * @brief STM32MP2 Gigabit Ethernet MAC driver (ETH2 instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.4
29  **/
30 
31 #ifndef _STM32MP2XX_ETH2_DRIVER_H
32 #define _STM32MP2XX_ETH2_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef STM32MP2XX_ETH2_TX_BUFFER_COUNT
39  #define STM32MP2XX_ETH2_TX_BUFFER_COUNT 8
40 #elif (STM32MP2XX_ETH2_TX_BUFFER_COUNT < 1)
41  #error STM32MP2XX_ETH2_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef STM32MP2XX_ETH2_TX_BUFFER_SIZE
46  #define STM32MP2XX_ETH2_TX_BUFFER_SIZE 1536
47 #elif (STM32MP2XX_ETH2_TX_BUFFER_SIZE != 1536)
48  #error STM32MP2XX_ETH2_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef STM32MP2XX_ETH2_RX_BUFFER_COUNT
53  #define STM32MP2XX_ETH2_RX_BUFFER_COUNT 8
54 #elif (STM32MP2XX_ETH2_RX_BUFFER_COUNT < 1)
55  #error STM32MP2XX_ETH2_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef STM32MP2XX_ETH2_RX_BUFFER_SIZE
60  #define STM32MP2XX_ETH2_RX_BUFFER_SIZE 1536
61 #elif (STM32MP2XX_ETH2_RX_BUFFER_SIZE != 1536)
62  #error STM32MP2XX_ETH2_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef STM32MP2XX_ETH2_IRQ_PRIORITY_GROUPING
67  #define STM32MP2XX_ETH2_IRQ_PRIORITY_GROUPING 3
68 #elif (STM32MP2XX_ETH2_IRQ_PRIORITY_GROUPING < 0)
69  #error STM32MP2XX_ETH2_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef STM32MP2XX_ETH2_IRQ_GROUP_PRIORITY
74  #define STM32MP2XX_ETH2_IRQ_GROUP_PRIORITY 12
75 #elif (STM32MP2XX_ETH2_IRQ_GROUP_PRIORITY < 0)
76  #error STM32MP2XX_ETH2_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef STM32MP2XX_ETH2_IRQ_SUB_PRIORITY
81  #define STM32MP2XX_ETH2_IRQ_SUB_PRIORITY 0
82 #elif (STM32MP2XX_ETH2_IRQ_SUB_PRIORITY < 0)
83  #error STM32MP2XX_ETH2_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //Register access macros
87 #define ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk)
88 #define ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk)
89 #define ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk)
90 #define ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk)
91 #define ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk)
92 #define ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk)
93 #define ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk)
94 #define ETH_DMAMR_TXPR_Val(n) (((n) << ETH_DMAMR_TXPR_Pos) & ETH_DMAMR_TXPR_Msk)
95 #define ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk)
96 #define ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk)
97 #define ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk)
98 #define ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk)
99 
100 //Transmit normal descriptor (read format)
101 #define ETH_TDES0_BUF1AP 0xFFFFFFFF
102 #define ETH_TDES1_BUF2AP 0xFFFFFFFF
103 #define ETH_TDES2_IOC 0x80000000
104 #define ETH_TDES2_TTSE 0x40000000
105 #define ETH_TDES2_B2L 0x3FFF0000
106 #define ETH_TDES2_VTIR 0x0000C000
107 #define ETH_TDES2_B1L 0x00003FFF
108 #define ETH_TDES3_OWN 0x80000000
109 #define ETH_TDES3_CTXT 0x40000000
110 #define ETH_TDES3_FD 0x20000000
111 #define ETH_TDES3_LD 0x10000000
112 #define ETH_TDES3_CPC 0x0C000000
113 #define ETH_TDES3_SAIC 0x03800000
114 #define ETH_TDES3_THL 0x00780000
115 #define ETH_TDES3_TSE 0x00040000
116 #define ETH_TDES3_CIC 0x00030000
117 #define ETH_TDES3_FL 0x00007FFF
118 
119 //Transmit normal descriptor (write-back format)
120 #define ETH_TDES0_TTSL 0xFFFFFFFF
121 #define ETH_TDES1_TTSH 0xFFFFFFFF
122 #define ETH_TDES3_OWN 0x80000000
123 #define ETH_TDES3_CTXT 0x40000000
124 #define ETH_TDES3_FD 0x20000000
125 #define ETH_TDES3_LD 0x10000000
126 #define ETH_TDES3_TTSS 0x00020000
127 #define ETH_TDES3_ES 0x00008000
128 #define ETH_TDES3_JT 0x00004000
129 #define ETH_TDES3_FF 0x00002000
130 #define ETH_TDES3_PCE 0x00001000
131 #define ETH_TDES3_LOC 0x00000800
132 #define ETH_TDES3_NC 0x00000400
133 #define ETH_TDES3_LC 0x00000200
134 #define ETH_TDES3_EC 0x00000100
135 #define ETH_TDES3_CC 0x000000F0
136 #define ETH_TDES3_ED 0x00000008
137 #define ETH_TDES3_UF 0x00000004
138 #define ETH_TDES3_DB 0x00000002
139 #define ETH_TDES3_IHE 0x00000001
140 
141 //Transmit context descriptor
142 #define ETH_TDES0_TTSL 0xFFFFFFFF
143 #define ETH_TDES1_TTSH 0xFFFFFFFF
144 #define ETH_TDES2_IVT 0xFFFF0000
145 #define ETH_TDES2_MSS 0x00003FFF
146 #define ETH_TDES3_OWN 0x80000000
147 #define ETH_TDES3_CTXT 0x40000000
148 #define ETH_TDES3_OSTC 0x08000000
149 #define ETH_TDES3_TCMSSV 0x04000000
150 #define ETH_TDES3_CDE 0x00800000
151 #define ETH_TDES3_IVLTV 0x00020000
152 #define ETH_TDES3_VLTV 0x00010000
153 #define ETH_TDES3_VT 0x0000FFFF
154 
155 //Receive normal descriptor (read format)
156 #define ETH_RDES0_BUF1AP 0xFFFFFFFF
157 #define ETH_RDES2_BUF2AP 0xFFFFFFFF
158 #define ETH_RDES3_OWN 0x80000000
159 #define ETH_RDES3_IOC 0x40000000
160 #define ETH_RDES3_BUF2V 0x02000000
161 #define ETH_RDES3_BUF1V 0x01000000
162 
163 //Receive normal descriptor (write-back format)
164 #define ETH_RDES0_IVT 0xFFFF0000
165 #define ETH_RDES0_OVT 0x0000FFFF
166 #define ETH_RDES1_OPC 0xFFFF0000
167 #define ETH_RDES1_TD 0x00008000
168 #define ETH_RDES1_TSA 0x00004000
169 #define ETH_RDES1_PV 0x00002000
170 #define ETH_RDES1_PFT 0x00001000
171 #define ETH_RDES1_PMT 0x00000F00
172 #define ETH_RDES1_IPCE 0x00000080
173 #define ETH_RDES1_IPCB 0x00000040
174 #define ETH_RDES1_IPV6 0x00000020
175 #define ETH_RDES1_IPV4 0x00000010
176 #define ETH_RDES1_IPHE 0x00000008
177 #define ETH_RDES1_PT 0x00000007
178 #define ETH_RDES2_L3L4FM 0xE0000000
179 #define ETH_RDES2_L4FM 0x10000000
180 #define ETH_RDES2_L3FM 0x08000000
181 #define ETH_RDES2_MADRM 0x07F80000
182 #define ETH_RDES2_HF 0x00040000
183 #define ETH_RDES2_DAF 0x00020000
184 #define ETH_RDES2_SAF 0x00010000
185 #define ETH_RDES2_VF 0x00008000
186 #define ETH_RDES2_ARPRN 0x00000400
187 #define ETH_RDES3_OWN 0x80000000
188 #define ETH_RDES3_CTXT 0x40000000
189 #define ETH_RDES3_FD 0x20000000
190 #define ETH_RDES3_LD 0x10000000
191 #define ETH_RDES3_RS2V 0x08000000
192 #define ETH_RDES3_RS1V 0x04000000
193 #define ETH_RDES3_RS0V 0x02000000
194 #define ETH_RDES3_CE 0x01000000
195 #define ETH_RDES3_GP 0x00800000
196 #define ETH_RDES3_RWT 0x00400000
197 #define ETH_RDES3_OE 0x00200000
198 #define ETH_RDES3_RE 0x00100000
199 #define ETH_RDES3_DE 0x00080000
200 #define ETH_RDES3_LT 0x00070000
201 #define ETH_RDES3_ES 0x00008000
202 #define ETH_RDES3_PL 0x00007FFF
203 
204 //Receive context descriptor
205 #define ETH_RDES0_RTSL 0xFFFFFFFF
206 #define ETH_RDES1_RTSH 0xFFFFFFFF
207 #define ETH_RDES3_OWN 0x80000000
208 #define ETH_RDES3_CTXT 0x40000000
209 
210 //C++ guard
211 #ifdef __cplusplus
212 extern "C" {
213 #endif
214 
215 
216 /**
217  * @brief Transmit descriptor
218  **/
219 
220 typedef struct
221 {
222  uint32_t tdes0;
223  uint32_t tdes1;
224  uint32_t tdes2;
225  uint32_t tdes3;
227 
228 
229 /**
230  * @brief Receive descriptor
231  **/
232 
233 typedef struct
234 {
235  uint32_t rdes0;
236  uint32_t rdes1;
237  uint32_t rdes2;
238  uint32_t rdes3;
240 
241 
242 //STM32MP2 Ethernet MAC driver (ETH2 instance)
243 extern const NicDriver stm32mp2xxEth2Driver;
244 
245 //STM32MP2 Ethernet MAC related functions
247 void stm32mp2xxEth2InitGpio(NetInterface *interface);
248 void stm32mp2xxEth2InitDmaDesc(NetInterface *interface);
249 
250 void stm32mp2xxEth2Tick(NetInterface *interface);
251 
252 void stm32mp2xxEth2EnableIrq(NetInterface *interface);
253 void stm32mp2xxEth2DisableIrq(NetInterface *interface);
255 
257  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
258 
260 
263 
264 void stm32mp2xxEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr,
265  uint8_t regAddr, uint16_t data);
266 
267 uint16_t stm32mp2xxEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
268  uint8_t regAddr);
269 
270 uint32_t stm32mp2xxEth2CalcCrc(const void *data, size_t length);
271 
272 //C++ guard
273 #ifdef __cplusplus
274 }
275 #endif
276 
277 #endif
uint8_t opcode
Definition: dns_common.h:188
error_t stm32mp2xxEth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
uint8_t data[]
Definition: ethernet.h:222
void stm32mp2xxEth2Tick(NetInterface *interface)
STM32MP2 Ethernet MAC timer handler.
void stm32mp2xxEth2EventHandler(NetInterface *interface)
STM32MP2 Ethernet MAC event handler.
error_t
Error codes.
Definition: error.h:43
void stm32mp2xxEth2DisableIrq(NetInterface *interface)
Disable interrupts.
void stm32mp2xxEth2InitGpio(NetInterface *interface)
GPIO configuration.
#define NetInterface
Definition: net.h:36
error_t stm32mp2xxEth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define NetTxAncillary
Definition: net_misc.h:36
uint8_t length
Definition: tcp.h:368
void stm32mp2xxEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t stm32mp2xxEth2ReceivePacket(NetInterface *interface)
Receive a packet.
error_t stm32mp2xxEth2Init(NetInterface *interface)
STM32MP2 Ethernet MAC initialization.
uint16_t regAddr
void stm32mp2xxEth2InitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
Network interface controller abstraction layer.
const NicDriver stm32mp2xxEth2Driver
STM32MP2 Ethernet MAC driver (ETH2 instance)
void stm32mp2xxEth2EnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t stm32mp2xxEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
NIC driver.
Definition: nic.h:286
error_t stm32mp2xxEth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint32_t stm32mp2xxEth2CalcCrc(const void *data, size_t length)
CRC calculation.