Infineon AURIX TriCore TC3xx Ethernet MAC driver. More...

#include "core/nic.h"

Data Structures
struct	Tc3xxTxDmaDesc
	Transmit DMA descriptor. More...

struct	Tc3xxRxDmaDesc
	Receive DMA descriptor. More...

Macros
#define	TC3XX_ETH_TX_BUFFER_COUNT 3

#define	TC3XX_ETH_TX_BUFFER_SIZE 1536

#define	TC3XX_ETH_RX_BUFFER_COUNT 6

#define	TC3XX_ETH_RX_BUFFER_SIZE 1536

#define	TC3XX_ETH_IRQ_PRIORITY 10

#define	ETH_DMA_CH_STATUS_REB 0x00380000

#define	ETH_DMA_CH_STATUS_TEB 0x00070000

#define	ETH_DMA_CH_STATUS_NIS 0x00008000

#define	ETH_DMA_CH_STATUS_AIS 0x00004000

#define	ETH_DMA_CH_STATUS_CDE 0x00002000

#define	ETH_DMA_CH_STATUS_FBE 0x00001000

#define	ETH_DMA_CH_STATUS_ERI 0x00000800

#define	ETH_DMA_CH_STATUS_ETI 0x00000400

#define	ETH_DMA_CH_STATUS_RWT 0x00000200

#define	ETH_DMA_CH_STATUS_RPS 0x00000100

#define	ETH_DMA_CH_STATUS_RBU 0x00000080

#define	ETH_DMA_CH_STATUS_RI 0x00000040

#define	ETH_DMA_CH_STATUS_TBU 0x00000004

#define	ETH_DMA_CH_STATUS_TPS 0x00000002

#define	ETH_DMA_CH_STATUS_TI 0x00000001

#define	ETH_DMA_CH_INTERRUPT_ENABLE_NIE 0x00008000

#define	ETH_DMA_CH_INTERRUPT_ENABLE_AIE 0x00004000

#define	ETH_DMA_CH_INTERRUPT_ENABLE_CDEE 0x00002000

#define	ETH_DMA_CH_INTERRUPT_ENABLE_FBEE 0x00001000

#define	ETH_DMA_CH_INTERRUPT_ENABLE_ERIE 0x00000800

#define	ETH_DMA_CH_INTERRUPT_ENABLE_ETIE 0x00000400

#define	ETH_DMA_CH_INTERRUPT_ENABLE_RWTE 0x00000200

#define	ETH_DMA_CH_INTERRUPT_ENABLE_RSE 0x00000100

#define	ETH_DMA_CH_INTERRUPT_ENABLE_RBUE 0x00000080

#define	ETH_DMA_CH_INTERRUPT_ENABLE_RIE 0x00000040

#define	ETH_DMA_CH_INTERRUPT_ENABLE_TBUE 0x00000004

#define	ETH_DMA_CH_INTERRUPT_ENABLE_TXSE 0x00000002

#define	ETH_DMA_CH_INTERRUPT_ENABLE_TIE 0x00000001

#define	ETH_MAC_ADDRESS_HIGH_AE 0x80000000

#define	ETH_MAC_ADDRESS_HIGH_SA 0x40000000

#define	ETH_MAC_ADDRESS_HIGH_MBC 0x3F000000

#define	ETH_MAC_ADDRESS_HIGH_DCS 0x00030000

#define	ETH_MAC_ADDRESS_HIGH_ADDRHI 0x0000FFFF

#define	ETH_TDES0_BUF1AP 0xFFFFFFFF

#define	ETH_TDES1_BUF2AP 0xFFFFFFFF

#define	ETH_TDES2_IOC 0x80000000

#define	ETH_TDES2_TTSE 0x40000000

#define	ETH_TDES2_B2L 0x3FFF0000

#define	ETH_TDES2_B1L 0x00003FFF

#define	ETH_TDES3_OWN 0x80000000

#define	ETH_TDES3_CTXT 0x40000000

#define	ETH_TDES3_FD 0x20000000

#define	ETH_TDES3_LD 0x10000000

#define	ETH_TDES3_CPC 0x0C000000

#define	ETH_TDES3_SLOTNUM 0x00780000

#define	ETH_TDES3_CIC 0x00030000

#define	ETH_TDES3_FL 0x00007FFF

#define	ETH_TDES0_TTSL 0xFFFFFFFF

#define	ETH_TDES1_TTSH 0xFFFFFFFF

#define	ETH_TDES3_OWN 0x80000000

#define	ETH_TDES3_CTXT 0x40000000

#define	ETH_TDES3_FD 0x20000000

#define	ETH_TDES3_LD 0x10000000

#define	ETH_TDES3_TTSS 0x00020000

#define	ETH_TDES3_ES 0x00008000

#define	ETH_TDES3_JT 0x00004000

#define	ETH_TDES3_FF 0x00002000

#define	ETH_TDES3_PCE 0x00001000

#define	ETH_TDES3_LOC 0x00000800

#define	ETH_TDES3_NC 0x00000400

#define	ETH_TDES3_LC 0x00000200

#define	ETH_TDES3_EC 0x00000100

#define	ETH_TDES3_CC 0x000000F0

#define	ETH_TDES3_ED 0x00000008

#define	ETH_TDES3_UF 0x00000004

#define	ETH_TDES3_DB 0x00000002

#define	ETH_TDES3_IHE 0x00000001

#define	ETH_RDES0_BUF1AP 0xFFFFFFFF

#define	ETH_RDES2_BUF2AP 0xFFFFFFFF

#define	ETH_RDES3_OWN 0x80000000

#define	ETH_RDES3_IOC 0x40000000

#define	ETH_RDES3_BUF2V 0x02000000

#define	ETH_RDES3_BUF1V 0x01000000

#define	ETH_RDES1_OPC 0xFFFF0000

#define	ETH_RDES1_TD 0x00008000

#define	ETH_RDES1_TSA 0x00004000

#define	ETH_RDES1_PV 0x00002000

#define	ETH_RDES1_PFT 0x00001000

#define	ETH_RDES1_PMT 0x00000F00

#define	ETH_RDES1_IPCE 0x00000080

#define	ETH_RDES1_IPCB 0x00000040

#define	ETH_RDES1_IPV6 0x00000020

#define	ETH_RDES1_IPV4 0x00000010

#define	ETH_RDES1_IPHE 0x00000008

#define	ETH_RDES1_PT 0x00000007

#define	ETH_RDES2_MADRM 0x07F80000

#define	ETH_RDES2_DAF 0x00020000

#define	ETH_RDES2_SAF 0x00010000

#define	ETH_RDES3_OWN 0x80000000

#define	ETH_RDES3_CTXT 0x40000000

#define	ETH_RDES3_FD 0x20000000

#define	ETH_RDES3_LD 0x10000000

#define	ETH_RDES3_RS2V 0x08000000

#define	ETH_RDES3_RS1V 0x04000000

#define	ETH_RDES3_RS0V 0x02000000

#define	ETH_RDES3_CE 0x01000000

#define	ETH_RDES3_GP 0x00800000

#define	ETH_RDES3_RWT 0x00400000

#define	ETH_RDES3_OE 0x00200000

#define	ETH_RDES3_RE 0x00100000

#define	ETH_RDES3_DE 0x00080000

#define	ETH_RDES3_LT 0x00070000

#define	ETH_RDES3_ES 0x00008000

#define	ETH_RDES3_PL 0x00007FFF

#define	ETH_CPU_ID() (_mfcr(CPU_CORE_ID) & IFX_CPU_CORE_ID_CORE_ID_MSK)

#define	ETH_GLOBAL_DSPR_ADDR(address)

Functions
error_t	tc3xxEthInit (NetInterface *interface)
	TC3xx Ethernet MAC initialization. More...

void	tc3xxEthInitGpio (NetInterface *interface)
	GPIO configuration. More...

void	tc3xxEthInitDmaDesc (NetInterface *interface)
	Initialize DMA descriptor lists. More...

void	tc3xxEthTick (NetInterface *interface)
	TC3xx Ethernet MAC timer handler. More...

void	tc3xxEthEnableIrq (NetInterface *interface)
	Enable interrupts. More...

void	tc3xxEthDisableIrq (NetInterface *interface)
	Disable interrupts. More...

void	tc3xxEthIrqHandler (int_t arg)
	TC3xx Ethernet MAC interrupt service routine. More...

void	tc3xxEthEventHandler (NetInterface *interface)
	TC3xx Ethernet MAC event handler. More...

error_t	tc3xxEthSendPacket (NetInterface interface, const NetBuffer buffer, size_t offset, NetTxAncillary *ancillary)
	Send a packet. More...

error_t	tc3xxEthReceivePacket (NetInterface *interface)
	Receive a packet. More...

error_t	tc3xxEthUpdateMacAddrFilter (NetInterface *interface)
	Configure MAC address filtering. More...

error_t	tc3xxEthUpdateMacConfig (NetInterface *interface)
	Adjust MAC configuration parameters for proper operation. More...

void	tc3xxEthWritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
	Write PHY register. More...

uint16_t	tc3xxEthReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
	Read PHY register. More...

Variables
const NicDriver	tc3xxEthDriver
	TC3xx Ethernet MAC driver. More...

Detailed Description

Infineon AURIX TriCore TC3xx Ethernet MAC driver.

License

SPDX-License-Identifier: GPL-2.0-or-later

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author: Oryx Embedded SARL (www.oryx-embedded.com)

Version: 2.4.4

Definition in file tc3xx_eth_driver.h.

Macro Definition Documentation

◆ ETH_CPU_ID

#define ETH_CPU_ID ( ) (_mfcr(CPU_CORE_ID) & IFX_CPU_CORE_ID_CORE_ID_MSK)

Definition at line 191 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_AIE

#define ETH_DMA_CH_INTERRUPT_ENABLE_AIE 0x00004000

Definition at line 91 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_CDEE

#define ETH_DMA_CH_INTERRUPT_ENABLE_CDEE 0x00002000

Definition at line 92 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_ERIE

#define ETH_DMA_CH_INTERRUPT_ENABLE_ERIE 0x00000800

Definition at line 94 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_ETIE

#define ETH_DMA_CH_INTERRUPT_ENABLE_ETIE 0x00000400

Definition at line 95 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_FBEE

#define ETH_DMA_CH_INTERRUPT_ENABLE_FBEE 0x00001000

Definition at line 93 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_NIE

#define ETH_DMA_CH_INTERRUPT_ENABLE_NIE 0x00008000

Definition at line 90 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_RBUE

#define ETH_DMA_CH_INTERRUPT_ENABLE_RBUE 0x00000080

Definition at line 98 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_RIE

#define ETH_DMA_CH_INTERRUPT_ENABLE_RIE 0x00000040

Definition at line 99 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_RSE

#define ETH_DMA_CH_INTERRUPT_ENABLE_RSE 0x00000100

Definition at line 97 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_RWTE

#define ETH_DMA_CH_INTERRUPT_ENABLE_RWTE 0x00000200

Definition at line 96 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_TBUE

#define ETH_DMA_CH_INTERRUPT_ENABLE_TBUE 0x00000004

Definition at line 100 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_TIE

#define ETH_DMA_CH_INTERRUPT_ENABLE_TIE 0x00000001

Definition at line 102 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_INTERRUPT_ENABLE_TXSE

#define ETH_DMA_CH_INTERRUPT_ENABLE_TXSE 0x00000002

Definition at line 101 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_AIS

#define ETH_DMA_CH_STATUS_AIS 0x00004000

Definition at line 76 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_CDE

#define ETH_DMA_CH_STATUS_CDE 0x00002000

Definition at line 77 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_ERI

#define ETH_DMA_CH_STATUS_ERI 0x00000800

Definition at line 79 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_ETI

#define ETH_DMA_CH_STATUS_ETI 0x00000400

Definition at line 80 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_FBE

#define ETH_DMA_CH_STATUS_FBE 0x00001000

Definition at line 78 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_NIS

#define ETH_DMA_CH_STATUS_NIS 0x00008000

Definition at line 75 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_RBU

#define ETH_DMA_CH_STATUS_RBU 0x00000080

Definition at line 83 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_REB

#define ETH_DMA_CH_STATUS_REB 0x00380000

Definition at line 73 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_RI

#define ETH_DMA_CH_STATUS_RI 0x00000040

Definition at line 84 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_RPS

#define ETH_DMA_CH_STATUS_RPS 0x00000100

Definition at line 82 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_RWT

#define ETH_DMA_CH_STATUS_RWT 0x00000200

Definition at line 81 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_TBU

#define ETH_DMA_CH_STATUS_TBU 0x00000004

Definition at line 85 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_TEB

#define ETH_DMA_CH_STATUS_TEB 0x00070000

Definition at line 74 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_TI

#define ETH_DMA_CH_STATUS_TI 0x00000001

Definition at line 87 of file tc3xx_eth_driver.h.

◆ ETH_DMA_CH_STATUS_TPS

#define ETH_DMA_CH_STATUS_TPS 0x00000002

Definition at line 86 of file tc3xx_eth_driver.h.

◆ ETH_GLOBAL_DSPR_ADDR

#define ETH_GLOBAL_DSPR_ADDR ( address )

Value:

   ((((uint32_t) (address) & 0xF0000000) == 0xD0000000) ? \
   ((((uint32_t) (address) & 0x000FFFFF) | 0x70000000) - (ETH_CPU_ID() * 0x10000000)) : \
   (uint32_t) (address))

Definition at line 194 of file tc3xx_eth_driver.h.

◆ ETH_MAC_ADDRESS_HIGH_ADDRHI

#define ETH_MAC_ADDRESS_HIGH_ADDRHI 0x0000FFFF

Definition at line 109 of file tc3xx_eth_driver.h.

◆ ETH_MAC_ADDRESS_HIGH_AE

#define ETH_MAC_ADDRESS_HIGH_AE 0x80000000

Definition at line 105 of file tc3xx_eth_driver.h.

◆ ETH_MAC_ADDRESS_HIGH_DCS

#define ETH_MAC_ADDRESS_HIGH_DCS 0x00030000

Definition at line 108 of file tc3xx_eth_driver.h.

◆ ETH_MAC_ADDRESS_HIGH_MBC

#define ETH_MAC_ADDRESS_HIGH_MBC 0x3F000000

Definition at line 107 of file tc3xx_eth_driver.h.

◆ ETH_MAC_ADDRESS_HIGH_SA

#define ETH_MAC_ADDRESS_HIGH_SA 0x40000000

Definition at line 106 of file tc3xx_eth_driver.h.

◆ ETH_RDES0_BUF1AP

#define ETH_RDES0_BUF1AP 0xFFFFFFFF

Definition at line 150 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_IPCB

#define ETH_RDES1_IPCB 0x00000040

Definition at line 165 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_IPCE

#define ETH_RDES1_IPCE 0x00000080

Definition at line 164 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_IPHE

#define ETH_RDES1_IPHE 0x00000008

Definition at line 168 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_IPV4

#define ETH_RDES1_IPV4 0x00000010

Definition at line 167 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_IPV6

#define ETH_RDES1_IPV6 0x00000020

Definition at line 166 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_OPC

#define ETH_RDES1_OPC 0xFFFF0000

Definition at line 158 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_PFT

#define ETH_RDES1_PFT 0x00001000

Definition at line 162 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_PMT

#define ETH_RDES1_PMT 0x00000F00

Definition at line 163 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_PT

#define ETH_RDES1_PT 0x00000007

Definition at line 169 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_PV

#define ETH_RDES1_PV 0x00002000

Definition at line 161 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_TD

#define ETH_RDES1_TD 0x00008000

Definition at line 159 of file tc3xx_eth_driver.h.

◆ ETH_RDES1_TSA

#define ETH_RDES1_TSA 0x00004000

Definition at line 160 of file tc3xx_eth_driver.h.

◆ ETH_RDES2_BUF2AP

#define ETH_RDES2_BUF2AP 0xFFFFFFFF

Definition at line 151 of file tc3xx_eth_driver.h.

◆ ETH_RDES2_DAF

#define ETH_RDES2_DAF 0x00020000

Definition at line 171 of file tc3xx_eth_driver.h.

◆ ETH_RDES2_MADRM

#define ETH_RDES2_MADRM 0x07F80000

Definition at line 170 of file tc3xx_eth_driver.h.

◆ ETH_RDES2_SAF

#define ETH_RDES2_SAF 0x00010000

Definition at line 172 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_BUF1V

#define ETH_RDES3_BUF1V 0x01000000

Definition at line 155 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_BUF2V

#define ETH_RDES3_BUF2V 0x02000000

Definition at line 154 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_CE

#define ETH_RDES3_CE 0x01000000

Definition at line 180 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_CTXT

#define ETH_RDES3_CTXT 0x40000000

Definition at line 174 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_DE

#define ETH_RDES3_DE 0x00080000

Definition at line 185 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_ES

#define ETH_RDES3_ES 0x00008000

Definition at line 187 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_FD

#define ETH_RDES3_FD 0x20000000

Definition at line 175 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_GP

#define ETH_RDES3_GP 0x00800000

Definition at line 181 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_IOC

#define ETH_RDES3_IOC 0x40000000

Definition at line 153 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_LD

#define ETH_RDES3_LD 0x10000000

Definition at line 176 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_LT

#define ETH_RDES3_LT 0x00070000

Definition at line 186 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_OE

#define ETH_RDES3_OE 0x00200000

Definition at line 183 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_OWN [1/2]

#define ETH_RDES3_OWN 0x80000000

Definition at line 173 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_OWN [2/2]

#define ETH_RDES3_OWN 0x80000000

Definition at line 173 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_PL

#define ETH_RDES3_PL 0x00007FFF

Definition at line 188 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_RE

#define ETH_RDES3_RE 0x00100000

Definition at line 184 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_RS0V

#define ETH_RDES3_RS0V 0x02000000

Definition at line 179 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_RS1V

#define ETH_RDES3_RS1V 0x04000000

Definition at line 178 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_RS2V

#define ETH_RDES3_RS2V 0x08000000

Definition at line 177 of file tc3xx_eth_driver.h.

◆ ETH_RDES3_RWT

#define ETH_RDES3_RWT 0x00400000

Definition at line 182 of file tc3xx_eth_driver.h.

◆ ETH_TDES0_BUF1AP

#define ETH_TDES0_BUF1AP 0xFFFFFFFF

Definition at line 112 of file tc3xx_eth_driver.h.

◆ ETH_TDES0_TTSL

#define ETH_TDES0_TTSL 0xFFFFFFFF

Definition at line 128 of file tc3xx_eth_driver.h.

◆ ETH_TDES1_BUF2AP

#define ETH_TDES1_BUF2AP 0xFFFFFFFF

Definition at line 113 of file tc3xx_eth_driver.h.

◆ ETH_TDES1_TTSH

#define ETH_TDES1_TTSH 0xFFFFFFFF

Definition at line 129 of file tc3xx_eth_driver.h.

◆ ETH_TDES2_B1L

#define ETH_TDES2_B1L 0x00003FFF

Definition at line 117 of file tc3xx_eth_driver.h.

◆ ETH_TDES2_B2L

#define ETH_TDES2_B2L 0x3FFF0000

Definition at line 116 of file tc3xx_eth_driver.h.

◆ ETH_TDES2_IOC

#define ETH_TDES2_IOC 0x80000000

Definition at line 114 of file tc3xx_eth_driver.h.

◆ ETH_TDES2_TTSE

#define ETH_TDES2_TTSE 0x40000000

Definition at line 115 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_CC

#define ETH_TDES3_CC 0x000000F0

Definition at line 143 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_CIC

#define ETH_TDES3_CIC 0x00030000

Definition at line 124 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_CPC

#define ETH_TDES3_CPC 0x0C000000

Definition at line 122 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_CTXT [1/2]

#define ETH_TDES3_CTXT 0x40000000

Definition at line 131 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_CTXT [2/2]

#define ETH_TDES3_CTXT 0x40000000

Definition at line 131 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_DB

#define ETH_TDES3_DB 0x00000002

Definition at line 146 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_EC

#define ETH_TDES3_EC 0x00000100

Definition at line 142 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_ED

#define ETH_TDES3_ED 0x00000008

Definition at line 144 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_ES

#define ETH_TDES3_ES 0x00008000

Definition at line 135 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_FD [1/2]

#define ETH_TDES3_FD 0x20000000

Definition at line 132 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_FD [2/2]

#define ETH_TDES3_FD 0x20000000

Definition at line 132 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_FF

#define ETH_TDES3_FF 0x00002000

Definition at line 137 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_FL

#define ETH_TDES3_FL 0x00007FFF

Definition at line 125 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_IHE

#define ETH_TDES3_IHE 0x00000001

Definition at line 147 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_JT

#define ETH_TDES3_JT 0x00004000

Definition at line 136 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_LC

#define ETH_TDES3_LC 0x00000200

Definition at line 141 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_LD [1/2]

#define ETH_TDES3_LD 0x10000000

Definition at line 133 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_LD [2/2]

#define ETH_TDES3_LD 0x10000000

Definition at line 133 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_LOC

#define ETH_TDES3_LOC 0x00000800

Definition at line 139 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_NC

#define ETH_TDES3_NC 0x00000400

Definition at line 140 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_OWN [1/2]

#define ETH_TDES3_OWN 0x80000000

Definition at line 130 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_OWN [2/2]

#define ETH_TDES3_OWN 0x80000000

Definition at line 130 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_PCE

#define ETH_TDES3_PCE 0x00001000

Definition at line 138 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_SLOTNUM

#define ETH_TDES3_SLOTNUM 0x00780000

Definition at line 123 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_TTSS

#define ETH_TDES3_TTSS 0x00020000

Definition at line 134 of file tc3xx_eth_driver.h.

◆ ETH_TDES3_UF

#define ETH_TDES3_UF 0x00000004

Definition at line 145 of file tc3xx_eth_driver.h.

◆ TC3XX_ETH_IRQ_PRIORITY

#define TC3XX_ETH_IRQ_PRIORITY 10

Definition at line 67 of file tc3xx_eth_driver.h.

◆ TC3XX_ETH_RX_BUFFER_COUNT

#define TC3XX_ETH_RX_BUFFER_COUNT 6

Definition at line 53 of file tc3xx_eth_driver.h.

◆ TC3XX_ETH_RX_BUFFER_SIZE

#define TC3XX_ETH_RX_BUFFER_SIZE 1536

Definition at line 60 of file tc3xx_eth_driver.h.

◆ TC3XX_ETH_TX_BUFFER_COUNT

#define TC3XX_ETH_TX_BUFFER_COUNT 3

Definition at line 39 of file tc3xx_eth_driver.h.

◆ TC3XX_ETH_TX_BUFFER_SIZE

#define TC3XX_ETH_TX_BUFFER_SIZE 1536

Definition at line 46 of file tc3xx_eth_driver.h.

Function Documentation

◆ tc3xxEthDisableIrq()

void tc3xxEthDisableIrq ( NetInterface * interface )

Disable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 525 of file tc3xx_eth_driver.c.

◆ tc3xxEthEnableIrq()

void tc3xxEthEnableIrq ( NetInterface * interface )

Enable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 497 of file tc3xx_eth_driver.c.

◆ tc3xxEthEventHandler()

void tc3xxEthEventHandler ( NetInterface * interface )

TC3xx Ethernet MAC event handler.

Parameters

[in] interface Underlying network interface

Definition at line 606 of file tc3xx_eth_driver.c.

◆ tc3xxEthInit()

error_t tc3xxEthInit ( NetInterface * interface )

TC3xx Ethernet MAC initialization.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 119 of file tc3xx_eth_driver.c.

◆ tc3xxEthInitDmaDesc()

void tc3xxEthInitDmaDesc ( NetInterface * interface )

Initialize DMA descriptor lists.

Parameters

[in] interface Underlying network interface

Definition at line 421 of file tc3xx_eth_driver.c.

◆ tc3xxEthInitGpio()

void tc3xxEthInitGpio ( NetInterface * interface )

GPIO configuration.

Parameters

[in] interface Underlying network interface

Definition at line 297 of file tc3xx_eth_driver.c.

◆ tc3xxEthIrqHandler()

void tc3xxEthIrqHandler ( int_t arg )

TC3xx Ethernet MAC interrupt service routine.

Parameters

arg	Unused parameter

Definition at line 553 of file tc3xx_eth_driver.c.

◆ tc3xxEthReadPhyReg()

uint16_t tc3xxEthReadPhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr
	)

Read PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)

Returns: Register value

Definition at line 934 of file tc3xx_eth_driver.c.

◆ tc3xxEthReceivePacket()

error_t tc3xxEthReceivePacket ( NetInterface * interface )

Receive a packet.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 697 of file tc3xx_eth_driver.c.

◆ tc3xxEthSendPacket()

error_t tc3xxEthSendPacket	(	NetInterface *	interface,
		const NetBuffer *	buffer,
		size_t	offset,
		NetTxAncillary *	ancillary
	)

Send a packet.

Parameters

[in]	interface	Underlying network interface
[in]	buffer	Multi-part buffer containing the data to send
[in]	offset	Offset to the first data byte
[in]	ancillary	Additional options passed to the stack along with the packet

Returns: Error code

Definition at line 631 of file tc3xx_eth_driver.c.

◆ tc3xxEthTick()

void tc3xxEthTick ( NetInterface * interface )

TC3xx Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters

[in] interface Underlying network interface

Definition at line 472 of file tc3xx_eth_driver.c.

◆ tc3xxEthUpdateMacAddrFilter()

error_t tc3xxEthUpdateMacAddrFilter ( NetInterface * interface )

Configure MAC address filtering.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 776 of file tc3xx_eth_driver.c.

◆ tc3xxEthUpdateMacConfig()

error_t tc3xxEthUpdateMacConfig ( NetInterface * interface )

Adjust MAC configuration parameters for proper operation.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 842 of file tc3xx_eth_driver.c.

◆ tc3xxEthWritePhyReg()

void tc3xxEthWritePhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr,
		uint16_t	data
	)

Write PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)
[in]	data	Register value

Definition at line 894 of file tc3xx_eth_driver.c.

Variable Documentation

◆ tc3xxEthDriver

const NicDriver tc3xxEthDriver

extern

TC3xx Ethernet MAC driver.

Definition at line 92 of file tc3xx_eth_driver.c.

Data Structures

Macros

Functions

Variables

Detailed Description

License

Macro Definition Documentation

◆ ETH_CPU_ID

◆ ETH_DMA_CH_INTERRUPT_ENABLE_AIE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_CDEE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_ERIE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_ETIE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_FBEE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_NIE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_RBUE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_RIE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_RSE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_RWTE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_TBUE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_TIE

◆ ETH_DMA_CH_INTERRUPT_ENABLE_TXSE

◆ ETH_DMA_CH_STATUS_AIS

◆ ETH_DMA_CH_STATUS_CDE

◆ ETH_DMA_CH_STATUS_ERI

◆ ETH_DMA_CH_STATUS_ETI

◆ ETH_DMA_CH_STATUS_FBE

◆ ETH_DMA_CH_STATUS_NIS

◆ ETH_DMA_CH_STATUS_RBU

◆ ETH_DMA_CH_STATUS_REB

◆ ETH_DMA_CH_STATUS_RI

◆ ETH_DMA_CH_STATUS_RPS

◆ ETH_DMA_CH_STATUS_RWT

◆ ETH_DMA_CH_STATUS_TBU

◆ ETH_DMA_CH_STATUS_TEB

◆ ETH_DMA_CH_STATUS_TI

◆ ETH_DMA_CH_STATUS_TPS

◆ ETH_GLOBAL_DSPR_ADDR

◆ ETH_MAC_ADDRESS_HIGH_ADDRHI

◆ ETH_MAC_ADDRESS_HIGH_AE

◆ ETH_MAC_ADDRESS_HIGH_DCS

◆ ETH_MAC_ADDRESS_HIGH_MBC

◆ ETH_MAC_ADDRESS_HIGH_SA

◆ ETH_RDES0_BUF1AP

◆ ETH_RDES1_IPCB

◆ ETH_RDES1_IPCE

◆ ETH_RDES1_IPHE

◆ ETH_RDES1_IPV4

◆ ETH_RDES1_IPV6

◆ ETH_RDES1_OPC

◆ ETH_RDES1_PFT

◆ ETH_RDES1_PMT

◆ ETH_RDES1_PT

◆ ETH_RDES1_PV

◆ ETH_RDES1_TD

◆ ETH_RDES1_TSA

◆ ETH_RDES2_BUF2AP

◆ ETH_RDES2_DAF

◆ ETH_RDES2_MADRM

◆ ETH_RDES2_SAF

◆ ETH_RDES3_BUF1V

◆ ETH_RDES3_BUF2V

◆ ETH_RDES3_CE

◆ ETH_RDES3_CTXT

◆ ETH_RDES3_DE

◆ ETH_RDES3_ES

◆ ETH_RDES3_FD

◆ ETH_RDES3_GP

◆ ETH_RDES3_IOC

◆ ETH_RDES3_LD

◆ ETH_RDES3_LT

◆ ETH_RDES3_OE

◆ ETH_RDES3_OWN [1/2]

◆ ETH_RDES3_OWN [2/2]

◆ ETH_RDES3_PL

◆ ETH_RDES3_RE

◆ ETH_RDES3_RS0V

◆ ETH_RDES3_RS1V

◆ ETH_RDES3_RS2V

◆ ETH_RDES3_RWT

◆ ETH_TDES0_BUF1AP