xmc4800_eth_driver.h
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1 /**
2  * @file xmc4800_eth_driver.h
3  * @brief Infineon XMC4800 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _XMC4800_ETH_DRIVER_H
32 #define _XMC4800_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef XMC4800_ETH_TX_BUFFER_COUNT
39  #define XMC4800_ETH_TX_BUFFER_COUNT 3
40 #elif (XMC4800_ETH_TX_BUFFER_COUNT < 1)
41  #error XMC4800_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef XMC4800_ETH_TX_BUFFER_SIZE
46  #define XMC4800_ETH_TX_BUFFER_SIZE 1536
47 #elif (XMC4800_ETH_TX_BUFFER_SIZE != 1536)
48  #error XMC4800_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef XMC4800_ETH_RX_BUFFER_COUNT
53  #define XMC4800_ETH_RX_BUFFER_COUNT 6
54 #elif (XMC4800_ETH_RX_BUFFER_COUNT < 1)
55  #error XMC4800_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef XMC4800_ETH_RX_BUFFER_SIZE
60  #define XMC4800_ETH_RX_BUFFER_SIZE 1536
61 #elif (XMC4800_ETH_RX_BUFFER_SIZE != 1536)
62  #error XMC4800_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef XMC4800_ETH_IRQ_PRIORITY_GROUPING
67  #define XMC4800_ETH_IRQ_PRIORITY_GROUPING 1
68 #elif (XMC4800_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error XMC4800_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef XMC4800_ETH_IRQ_GROUP_PRIORITY
74  #define XMC4800_ETH_IRQ_GROUP_PRIORITY 48
75 #elif (XMC4800_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error XMC4800_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef XMC4800_ETH_IRQ_SUB_PRIORITY
81  #define XMC4800_ETH_IRQ_SUB_PRIORITY 0
82 #elif (XMC4800_ETH_IRQ_SUB_PRIORITY < 0)
83  #error XMC4800_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //ETH0_CON
87 #define ETH_CON_MDIO_A (0 << ETH_CON_MDIO_Pos)
88 #define ETH_CON_MDIO_B (1 << ETH_CON_MDIO_Pos)
89 #define ETH_CON_MDIO_C (2 << ETH_CON_MDIO_Pos)
90 #define ETH_CON_MDIO_D (3 << ETH_CON_MDIO_Pos)
91 
92 #define ETH_CON_CLK_TX_A (0 << ETH_CON_CLK_TX_Pos)
93 #define ETH_CON_CLK_TX_B (1 << ETH_CON_CLK_TX_Pos)
94 #define ETH_CON_CLK_TX_C (2 << ETH_CON_CLK_TX_Pos)
95 #define ETH_CON_CLK_TX_D (3 << ETH_CON_CLK_TX_Pos)
96 
97 #define ETH_CON_COL_A (0 << ETH_CON_COL_Pos)
98 #define ETH_CON_COL_B (1 << ETH_CON_COL_Pos)
99 #define ETH_CON_COL_C (2 << ETH_CON_COL_Pos)
100 #define ETH_CON_COL_D (3 << ETH_CON_COL_Pos)
101 
102 #define ETH_CON_RXER_A (0 << ETH_CON_RXER_Pos)
103 #define ETH_CON_RXER_B (1 << ETH_CON_RXER_Pos)
104 #define ETH_CON_RXER_C (2 << ETH_CON_RXER_Pos)
105 #define ETH_CON_RXER_D (3 << ETH_CON_RXER_Pos)
106 
107 #define ETH_CON_CRS_A (0 << ETH_CON_CRS_Pos)
108 #define ETH_CON_CRS_B (1 << ETH_CON_CRS_Pos)
109 #define ETH_CON_CRS_C (2 << ETH_CON_CRS_Pos)
110 #define ETH_CON_CRS_D (3 << ETH_CON_CRS_Pos)
111 
112 #define ETH_CON_CRS_DV_A (0 << ETH_CON_CRS_DV_Pos)
113 #define ETH_CON_CRS_DV_B (1 << ETH_CON_CRS_DV_Pos)
114 #define ETH_CON_CRS_DV_C (2 << ETH_CON_CRS_DV_Pos)
115 #define ETH_CON_CRS_DV_D (3 << ETH_CON_CRS_DV_Pos)
116 
117 #define ETH_CON_CLK_RMII_A (0 << ETH_CON_CLK_RMII_Pos)
118 #define ETH_CON_CLK_RMII_B (1 << ETH_CON_CLK_RMII_Pos)
119 #define ETH_CON_CLK_RMII_C (2 << ETH_CON_CLK_RMII_Pos)
120 #define ETH_CON_CLK_RMII_D (3 << ETH_CON_CLK_RMII_Pos)
121 
122 #define ETH_CON_RXD3_A (0 << ETH_CON_RXD3_Pos)
123 #define ETH_CON_RXD3_B (1 << ETH_CON_RXD3_Pos)
124 #define ETH_CON_RXD3_C (2 << ETH_CON_RXD3_Pos)
125 #define ETH_CON_RXD3_D (3 << ETH_CON_RXD3_Pos)
126 
127 #define ETH_CON_RXD2_A (0 << ETH_CON_RXD2_Pos)
128 #define ETH_CON_RXD2_B (1 << ETH_CON_RXD2_Pos)
129 #define ETH_CON_RXD2_C (2 << ETH_CON_RXD2_Pos)
130 #define ETH_CON_RXD2_D (3 << ETH_CON_RXD2_Pos)
131 
132 #define ETH_CON_RXD1_A (0 << ETH_CON_RXD1_Pos)
133 #define ETH_CON_RXD1_B (1 << ETH_CON_RXD1_Pos)
134 #define ETH_CON_RXD1_C (2 << ETH_CON_RXD1_Pos)
135 #define ETH_CON_RXD1_D (3 << ETH_CON_RXD1_Pos)
136 
137 #define ETH_CON_RXD0_A (0 << ETH_CON_RXD0_Pos)
138 #define ETH_CON_RXD0_B (1 << ETH_CON_RXD0_Pos)
139 #define ETH_CON_RXD0_C (2 << ETH_CON_RXD0_Pos)
140 #define ETH_CON_RXD0_D (3 << ETH_CON_RXD0_Pos)
141 
142 //ETH0_MAC_CONFIGURATION register
143 #define ETH_MAC_CONFIGURATION_RESERVED15_Msk (1 << 15)
144 
145 //ETH0_GMII_ADDRESS register
146 #define ETH_GMII_ADDRESS_CR_DIV42 (0 << ETH_GMII_ADDRESS_CR_Pos)
147 #define ETH_GMII_ADDRESS_CR_DIV62 (1 << ETH_GMII_ADDRESS_CR_Pos)
148 #define ETH_GMII_ADDRESS_CR_DIV16 (2 << ETH_GMII_ADDRESS_CR_Pos)
149 #define ETH_GMII_ADDRESS_CR_DIV26 (3 << ETH_GMII_ADDRESS_CR_Pos)
150 #define ETH_GMII_ADDRESS_CR_DIV102 (4 << ETH_GMII_ADDRESS_CR_Pos)
151 #define ETH_GMII_ADDRESS_CR_DIV124 (5 << ETH_GMII_ADDRESS_CR_Pos)
152 
153 //ETH0_BUS_MODE register
154 #define ETH_BUS_MODE_RPBL_1 (1 << ETH_BUS_MODE_RPBL_Pos)
155 #define ETH_BUS_MODE_RPBL_2 (2 << ETH_BUS_MODE_RPBL_Pos)
156 #define ETH_BUS_MODE_RPBL_4 (4 << ETH_BUS_MODE_RPBL_Pos)
157 #define ETH_BUS_MODE_RPBL_8 (8 << ETH_BUS_MODE_RPBL_Pos)
158 #define ETH_BUS_MODE_RPBL_16 (16 << ETH_BUS_MODE_RPBL_Pos)
159 #define ETH_BUS_MODE_RPBL_32 (32 << ETH_BUS_MODE_RPBL_Pos)
160 
161 #define ETH_BUS_MODE_PR_1_1 (0 << ETH_BUS_MODE_PR_Pos)
162 #define ETH_BUS_MODE_PR_2_1 (1 << ETH_BUS_MODE_PR_Pos)
163 #define ETH_BUS_MODE_PR_3_1 (2 << ETH_BUS_MODE_PR_Pos)
164 #define ETH_BUS_MODE_PR_4_1 (3 << ETH_BUS_MODE_PR_Pos)
165 
166 #define ETH_BUS_MODE_PBL_1 (1 << ETH_BUS_MODE_PBL_Pos)
167 #define ETH_BUS_MODE_PBL_2 (2 << ETH_BUS_MODE_PBL_Pos)
168 #define ETH_BUS_MODE_PBL_4 (4 << ETH_BUS_MODE_PBL_Pos)
169 #define ETH_BUS_MODE_PBL_8 (8 << ETH_BUS_MODE_PBL_Pos)
170 #define ETH_BUS_MODE_PBL_16 (16 << ETH_BUS_MODE_PBL_Pos)
171 #define ETH_BUS_MODE_PBL_32 (32 << ETH_BUS_MODE_PBL_Pos)
172 
173 //Transmit DMA descriptor flags
174 #define ETH_TDES0_OWN 0x80000000
175 #define ETH_TDES0_IC 0x40000000
176 #define ETH_TDES0_LS 0x20000000
177 #define ETH_TDES0_FS 0x10000000
178 #define ETH_TDES0_DC 0x08000000
179 #define ETH_TDES0_DP 0x04000000
180 #define ETH_TDES0_TTSE 0x02000000
181 #define ETH_TDES0_CIC 0x00C00000
182 #define ETH_TDES0_TER 0x00200000
183 #define ETH_TDES0_TCH 0x00100000
184 #define ETH_TDES0_TTSS 0x00020000
185 #define ETH_TDES0_IHE 0x00010000
186 #define ETH_TDES0_ES 0x00008000
187 #define ETH_TDES0_JT 0x00004000
188 #define ETH_TDES0_FF 0x00002000
189 #define ETH_TDES0_IPE 0x00001000
190 #define ETH_TDES0_LCA 0x00000800
191 #define ETH_TDES0_NC 0x00000400
192 #define ETH_TDES0_LCO 0x00000200
193 #define ETH_TDES0_EC 0x00000100
194 #define ETH_TDES0_VF 0x00000080
195 #define ETH_TDES0_CC 0x00000078
196 #define ETH_TDES0_ED 0x00000004
197 #define ETH_TDES0_UF 0x00000002
198 #define ETH_TDES0_DB 0x00000001
199 #define ETH_TDES1_TBS2 0x1FFF0000
200 #define ETH_TDES1_TBS1 0x00001FFF
201 #define ETH_TDES2_TBAP1 0xFFFFFFFF
202 #define ETH_TDES3_TBAP2 0xFFFFFFFF
203 
204 //Receive DMA descriptor flags
205 #define ETH_RDES0_OWN 0x80000000
206 #define ETH_RDES0_AFM 0x40000000
207 #define ETH_RDES0_FL 0x3FFF0000
208 #define ETH_RDES0_ES 0x00008000
209 #define ETH_RDES0_DE 0x00004000
210 #define ETH_RDES0_SAF 0x00002000
211 #define ETH_RDES0_LE 0x00001000
212 #define ETH_RDES0_OE 0x00000800
213 #define ETH_RDES0_VLAN 0x00000400
214 #define ETH_RDES0_FS 0x00000200
215 #define ETH_RDES0_LS 0x00000100
216 #define ETH_RDES0_IPCE_GF 0x00000080
217 #define ETH_RDES0_LCO 0x00000040
218 #define ETH_RDES0_FT 0x00000020
219 #define ETH_RDES0_RWT 0x00000010
220 #define ETH_RDES0_RE 0x00000008
221 #define ETH_RDES0_DBE 0x00000004
222 #define ETH_RDES0_CE 0x00000002
223 #define ETH_RDES0_PCE 0x00000001
224 #define ETH_RDES1_DIC 0x80000000
225 #define ETH_RDES1_RBS2 0x1FFF0000
226 #define ETH_RDES1_RER 0x00008000
227 #define ETH_RDES1_RCH 0x00004000
228 #define ETH_RDES1_RBS1 0x00001FFF
229 #define ETH_RDES2_RBAP1 0xFFFFFFFF
230 #define ETH_RDES3_RBAP2 0xFFFFFFFF
231 
232 //C++ guard
233 #ifdef __cplusplus
234 extern "C" {
235 #endif
236 
237 
238 /**
239  * @brief Transmit DMA descriptor
240  **/
241 
242 typedef struct
243 {
244  uint32_t tdes0;
245  uint32_t tdes1;
246  uint32_t tdes2;
247  uint32_t tdes3;
249 
250 
251 /**
252  * @brief Receive DMA descriptor
253  **/
254 
255 typedef struct
256 {
257  uint32_t rdes0;
258  uint32_t rdes1;
259  uint32_t rdes2;
260  uint32_t rdes3;
262 
263 
264 //XMC4800 Ethernet MAC driver
265 extern const NicDriver xmc4800EthDriver;
266 
267 //XMC4800 Ethernet MAC related functions
269 void xmc4800EthInitGpio(NetInterface *interface);
270 void xmc4800EthInitDmaDesc(NetInterface *interface);
271 
272 void xmc4800EthTick(NetInterface *interface);
273 
274 void xmc4800EthEnableIrq(NetInterface *interface);
275 void xmc4800EthDisableIrq(NetInterface *interface);
276 void xmc4800EthEventHandler(NetInterface *interface);
277 
279  const NetBuffer *buffer, size_t offset);
280 
282 
285 
286 void xmc4800EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
287  uint8_t regAddr, uint16_t data);
288 
289 uint16_t xmc4800EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
290  uint8_t regAddr);
291 
292 uint32_t xmc4800EthCalcCrc(const void *data, size_t length);
293 
294 //C++ guard
295 #ifdef __cplusplus
296 }
297 #endif
298 
299 #endif
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
void xmc4800EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t xmc4800EthReceivePacket(NetInterface *interface)
Receive a packet.
uint32_t xmc4800EthCalcCrc(const void *data, size_t length)
CRC calculation.
const NicDriver xmc4800EthDriver
XMC4800 Ethernet MAC driver.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void xmc4800EthInitGpio(NetInterface *interface)
void xmc4800EthTick(NetInterface *interface)
XMC4800 Ethernet MAC timer handler.
error_t
Error codes.
Definition: error.h:42
void xmc4800EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void xmc4800EthEventHandler(NetInterface *interface)
XMC4800 Ethernet MAC event handler.
uint16_t xmc4800EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define NetInterface
Definition: net.h:36
Receive DMA descriptor.
uint16_t regAddr
error_t xmc4800EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
Network interface controller abstraction layer.
Transmit DMA descriptor.
void xmc4800EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t xmc4800EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void xmc4800EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint8_t data[]
Definition: dtls_misc.h:176
error_t xmc4800EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
NIC driver.
Definition: nic.h:179
error_t xmc4800EthInit(NetInterface *interface)
XMC4800 Ethernet MAC initialization.