xmc4800_eth_driver.h
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1 /**
2  * @file xmc4800_eth_driver.h
3  * @brief Infineon XMC4800 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _XMC4800_ETH_DRIVER_H
30 #define _XMC4800_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef XMC4800_ETH_TX_BUFFER_COUNT
37  #define XMC4800_ETH_TX_BUFFER_COUNT 3
38 #elif (XMC4800_ETH_TX_BUFFER_COUNT < 1)
39  #error XMC4800_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef XMC4800_ETH_TX_BUFFER_SIZE
44  #define XMC4800_ETH_TX_BUFFER_SIZE 1536
45 #elif (XMC4800_ETH_TX_BUFFER_SIZE != 1536)
46  #error XMC4800_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef XMC4800_ETH_RX_BUFFER_COUNT
51  #define XMC4800_ETH_RX_BUFFER_COUNT 6
52 #elif (XMC4800_ETH_RX_BUFFER_COUNT < 1)
53  #error XMC4800_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef XMC4800_ETH_RX_BUFFER_SIZE
58  #define XMC4800_ETH_RX_BUFFER_SIZE 1536
59 #elif (XMC4800_ETH_RX_BUFFER_SIZE != 1536)
60  #error XMC4800_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Interrupt priority grouping
64 #ifndef XMC4800_ETH_IRQ_PRIORITY_GROUPING
65  #define XMC4800_ETH_IRQ_PRIORITY_GROUPING 1
66 #elif (XMC4800_ETH_IRQ_PRIORITY_GROUPING < 0)
67  #error XMC4800_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
68 #endif
69 
70 //Ethernet interrupt group priority
71 #ifndef XMC4800_ETH_IRQ_GROUP_PRIORITY
72  #define XMC4800_ETH_IRQ_GROUP_PRIORITY 48
73 #elif (XMC4800_ETH_IRQ_GROUP_PRIORITY < 0)
74  #error XMC4800_ETH_IRQ_GROUP_PRIORITY parameter is not valid
75 #endif
76 
77 //Ethernet interrupt subpriority
78 #ifndef XMC4800_ETH_IRQ_SUB_PRIORITY
79  #define XMC4800_ETH_IRQ_SUB_PRIORITY 0
80 #elif (XMC4800_ETH_IRQ_SUB_PRIORITY < 0)
81  #error XMC4800_ETH_IRQ_SUB_PRIORITY parameter is not valid
82 #endif
83 
84 //ETH0_CON
85 #define ETH_CON_MDIO_A (0 << ETH_CON_MDIO_Pos)
86 #define ETH_CON_MDIO_B (1 << ETH_CON_MDIO_Pos)
87 #define ETH_CON_MDIO_C (2 << ETH_CON_MDIO_Pos)
88 #define ETH_CON_MDIO_D (3 << ETH_CON_MDIO_Pos)
89 
90 #define ETH_CON_CLK_TX_A (0 << ETH_CON_CLK_TX_Pos)
91 #define ETH_CON_CLK_TX_B (1 << ETH_CON_CLK_TX_Pos)
92 #define ETH_CON_CLK_TX_C (2 << ETH_CON_CLK_TX_Pos)
93 #define ETH_CON_CLK_TX_D (3 << ETH_CON_CLK_TX_Pos)
94 
95 #define ETH_CON_COL_A (0 << ETH_CON_COL_Pos)
96 #define ETH_CON_COL_B (1 << ETH_CON_COL_Pos)
97 #define ETH_CON_COL_C (2 << ETH_CON_COL_Pos)
98 #define ETH_CON_COL_D (3 << ETH_CON_COL_Pos)
99 
100 #define ETH_CON_RXER_A (0 << ETH_CON_RXER_Pos)
101 #define ETH_CON_RXER_B (1 << ETH_CON_RXER_Pos)
102 #define ETH_CON_RXER_C (2 << ETH_CON_RXER_Pos)
103 #define ETH_CON_RXER_D (3 << ETH_CON_RXER_Pos)
104 
105 #define ETH_CON_CRS_A (0 << ETH_CON_CRS_Pos)
106 #define ETH_CON_CRS_B (1 << ETH_CON_CRS_Pos)
107 #define ETH_CON_CRS_C (2 << ETH_CON_CRS_Pos)
108 #define ETH_CON_CRS_D (3 << ETH_CON_CRS_Pos)
109 
110 #define ETH_CON_CRS_DV_A (0 << ETH_CON_CRS_DV_Pos)
111 #define ETH_CON_CRS_DV_B (1 << ETH_CON_CRS_DV_Pos)
112 #define ETH_CON_CRS_DV_C (2 << ETH_CON_CRS_DV_Pos)
113 #define ETH_CON_CRS_DV_D (3 << ETH_CON_CRS_DV_Pos)
114 
115 #define ETH_CON_CLK_RMII_A (0 << ETH_CON_CLK_RMII_Pos)
116 #define ETH_CON_CLK_RMII_B (1 << ETH_CON_CLK_RMII_Pos)
117 #define ETH_CON_CLK_RMII_C (2 << ETH_CON_CLK_RMII_Pos)
118 #define ETH_CON_CLK_RMII_D (3 << ETH_CON_CLK_RMII_Pos)
119 
120 #define ETH_CON_RXD3_A (0 << ETH_CON_RXD3_Pos)
121 #define ETH_CON_RXD3_B (1 << ETH_CON_RXD3_Pos)
122 #define ETH_CON_RXD3_C (2 << ETH_CON_RXD3_Pos)
123 #define ETH_CON_RXD3_D (3 << ETH_CON_RXD3_Pos)
124 
125 #define ETH_CON_RXD2_A (0 << ETH_CON_RXD2_Pos)
126 #define ETH_CON_RXD2_B (1 << ETH_CON_RXD2_Pos)
127 #define ETH_CON_RXD2_C (2 << ETH_CON_RXD2_Pos)
128 #define ETH_CON_RXD2_D (3 << ETH_CON_RXD2_Pos)
129 
130 #define ETH_CON_RXD1_A (0 << ETH_CON_RXD1_Pos)
131 #define ETH_CON_RXD1_B (1 << ETH_CON_RXD1_Pos)
132 #define ETH_CON_RXD1_C (2 << ETH_CON_RXD1_Pos)
133 #define ETH_CON_RXD1_D (3 << ETH_CON_RXD1_Pos)
134 
135 #define ETH_CON_RXD0_A (0 << ETH_CON_RXD0_Pos)
136 #define ETH_CON_RXD0_B (1 << ETH_CON_RXD0_Pos)
137 #define ETH_CON_RXD0_C (2 << ETH_CON_RXD0_Pos)
138 #define ETH_CON_RXD0_D (3 << ETH_CON_RXD0_Pos)
139 
140 //ETH0_MAC_CONFIGURATION register
141 #define ETH_MAC_CONFIGURATION_RESERVED15_Msk (1 << 15)
142 
143 //ETH0_GMII_ADDRESS register
144 #define ETH_GMII_ADDRESS_CR_DIV42 (0 << ETH_GMII_ADDRESS_CR_Pos)
145 #define ETH_GMII_ADDRESS_CR_DIV62 (1 << ETH_GMII_ADDRESS_CR_Pos)
146 #define ETH_GMII_ADDRESS_CR_DIV16 (2 << ETH_GMII_ADDRESS_CR_Pos)
147 #define ETH_GMII_ADDRESS_CR_DIV26 (3 << ETH_GMII_ADDRESS_CR_Pos)
148 #define ETH_GMII_ADDRESS_CR_DIV102 (4 << ETH_GMII_ADDRESS_CR_Pos)
149 #define ETH_GMII_ADDRESS_CR_DIV124 (5 << ETH_GMII_ADDRESS_CR_Pos)
150 
151 //ETH0_BUS_MODE register
152 #define ETH_BUS_MODE_RPBL_1 (1 << ETH_BUS_MODE_RPBL_Pos)
153 #define ETH_BUS_MODE_RPBL_2 (2 << ETH_BUS_MODE_RPBL_Pos)
154 #define ETH_BUS_MODE_RPBL_4 (4 << ETH_BUS_MODE_RPBL_Pos)
155 #define ETH_BUS_MODE_RPBL_8 (8 << ETH_BUS_MODE_RPBL_Pos)
156 #define ETH_BUS_MODE_RPBL_16 (16 << ETH_BUS_MODE_RPBL_Pos)
157 #define ETH_BUS_MODE_RPBL_32 (32 << ETH_BUS_MODE_RPBL_Pos)
158 
159 #define ETH_BUS_MODE_PR_1_1 (0 << ETH_BUS_MODE_PR_Pos)
160 #define ETH_BUS_MODE_PR_2_1 (1 << ETH_BUS_MODE_PR_Pos)
161 #define ETH_BUS_MODE_PR_3_1 (2 << ETH_BUS_MODE_PR_Pos)
162 #define ETH_BUS_MODE_PR_4_1 (3 << ETH_BUS_MODE_PR_Pos)
163 
164 #define ETH_BUS_MODE_PBL_1 (1 << ETH_BUS_MODE_PBL_Pos)
165 #define ETH_BUS_MODE_PBL_2 (2 << ETH_BUS_MODE_PBL_Pos)
166 #define ETH_BUS_MODE_PBL_4 (4 << ETH_BUS_MODE_PBL_Pos)
167 #define ETH_BUS_MODE_PBL_8 (8 << ETH_BUS_MODE_PBL_Pos)
168 #define ETH_BUS_MODE_PBL_16 (16 << ETH_BUS_MODE_PBL_Pos)
169 #define ETH_BUS_MODE_PBL_32 (32 << ETH_BUS_MODE_PBL_Pos)
170 
171 //Transmit DMA descriptor flags
172 #define ETH_TDES0_OWN 0x80000000
173 #define ETH_TDES0_IC 0x40000000
174 #define ETH_TDES0_LS 0x20000000
175 #define ETH_TDES0_FS 0x10000000
176 #define ETH_TDES0_DC 0x08000000
177 #define ETH_TDES0_DP 0x04000000
178 #define ETH_TDES0_TTSE 0x02000000
179 #define ETH_TDES0_CIC 0x00C00000
180 #define ETH_TDES0_TER 0x00200000
181 #define ETH_TDES0_TCH 0x00100000
182 #define ETH_TDES0_TTSS 0x00020000
183 #define ETH_TDES0_IHE 0x00010000
184 #define ETH_TDES0_ES 0x00008000
185 #define ETH_TDES0_JT 0x00004000
186 #define ETH_TDES0_FF 0x00002000
187 #define ETH_TDES0_IPE 0x00001000
188 #define ETH_TDES0_LCA 0x00000800
189 #define ETH_TDES0_NC 0x00000400
190 #define ETH_TDES0_LCO 0x00000200
191 #define ETH_TDES0_EC 0x00000100
192 #define ETH_TDES0_VF 0x00000080
193 #define ETH_TDES0_CC 0x00000078
194 #define ETH_TDES0_ED 0x00000004
195 #define ETH_TDES0_UF 0x00000002
196 #define ETH_TDES0_DB 0x00000001
197 #define ETH_TDES1_TBS2 0x1FFF0000
198 #define ETH_TDES1_TBS1 0x00001FFF
199 #define ETH_TDES2_TBAP1 0xFFFFFFFF
200 #define ETH_TDES3_TBAP2 0xFFFFFFFF
201 
202 //Receive DMA descriptor flags
203 #define ETH_RDES0_OWN 0x80000000
204 #define ETH_RDES0_AFM 0x40000000
205 #define ETH_RDES0_FL 0x3FFF0000
206 #define ETH_RDES0_ES 0x00008000
207 #define ETH_RDES0_DE 0x00004000
208 #define ETH_RDES0_SAF 0x00002000
209 #define ETH_RDES0_LE 0x00001000
210 #define ETH_RDES0_OE 0x00000800
211 #define ETH_RDES0_VLAN 0x00000400
212 #define ETH_RDES0_FS 0x00000200
213 #define ETH_RDES0_LS 0x00000100
214 #define ETH_RDES0_IPCE_GF 0x00000080
215 #define ETH_RDES0_LCO 0x00000040
216 #define ETH_RDES0_FT 0x00000020
217 #define ETH_RDES0_RWT 0x00000010
218 #define ETH_RDES0_RE 0x00000008
219 #define ETH_RDES0_DBE 0x00000004
220 #define ETH_RDES0_CE 0x00000002
221 #define ETH_RDES0_PCE 0x00000001
222 #define ETH_RDES1_DIC 0x80000000
223 #define ETH_RDES1_RBS2 0x1FFF0000
224 #define ETH_RDES1_RER 0x00008000
225 #define ETH_RDES1_RCH 0x00004000
226 #define ETH_RDES1_RBS1 0x00001FFF
227 #define ETH_RDES2_RBAP1 0xFFFFFFFF
228 #define ETH_RDES3_RBAP2 0xFFFFFFFF
229 
230 //C++ guard
231 #ifdef __cplusplus
232  extern "C" {
233 #endif
234 
235 
236 /**
237  * @brief Transmit DMA descriptor
238  **/
239 
240 typedef struct
241 {
242  uint32_t tdes0;
243  uint32_t tdes1;
244  uint32_t tdes2;
245  uint32_t tdes3;
247 
248 
249 /**
250  * @brief Receive DMA descriptor
251  **/
252 
253 typedef struct
254 {
255  uint32_t rdes0;
256  uint32_t rdes1;
257  uint32_t rdes2;
258  uint32_t rdes3;
260 
261 
262 //XMC4800 Ethernet MAC driver
263 extern const NicDriver xmc4800EthDriver;
264 
265 //XMC4800 Ethernet MAC related functions
267 void xmc4800EthInitGpio(NetInterface *interface);
268 void xmc4800EthInitDmaDesc(NetInterface *interface);
269 
270 void xmc4800EthTick(NetInterface *interface);
271 
272 void xmc4800EthEnableIrq(NetInterface *interface);
273 void xmc4800EthDisableIrq(NetInterface *interface);
274 void xmc4800EthEventHandler(NetInterface *interface);
275 
277  const NetBuffer *buffer, size_t offset);
278 
280 
283 
284 void xmc4800EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
285 uint16_t xmc4800EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
286 
287 uint32_t xmc4800EthCalcCrc(const void *data, size_t length);
288 
289 //C++ guard
290 #ifdef __cplusplus
291  }
292 #endif
293 
294 #endif
void xmc4800EthDisableIrq(NetInterface *interface)
Disable interrupts.
void xmc4800EthEventHandler(NetInterface *interface)
XMC4800 Ethernet MAC event handler.
error_t xmc4800EthReceivePacket(NetInterface *interface)
Receive a packet.
uint16_t xmc4800EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void xmc4800EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t xmc4800EthInit(NetInterface *interface)
XMC4800 Ethernet MAC initialization.
void xmc4800EthInitGpio(NetInterface *interface)
Receive DMA descriptor.
error_t xmc4800EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void xmc4800EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
error_t xmc4800EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint16_t regAddr
error_t xmc4800EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
const NicDriver xmc4800EthDriver
XMC4800 Ethernet MAC driver.
Transmit DMA descriptor.
uint32_t xmc4800EthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void xmc4800EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint8_t length
Definition: dtls_misc.h:140
void xmc4800EthTick(NetInterface *interface)
XMC4800 Ethernet MAC timer handler.
Network interface controller abstraction layer.