am335x_eth_driver.h File Reference

Sitara AM335x Ethernet MAC controller. More...

#include "core/nic.h"

Go to the source code of this file.

Data Structures

struct  Am335xAleEntry
 ALE table entry. More...
 
struct  _Am335xTxBufferDesc
 TX buffer descriptor. More...
 
struct  _Am335xRxBufferDesc
 RX buffer descriptor. More...
 

Macros

#define AM335X_ETH_TX_BUFFER_COUNT   16
 
#define AM335X_ETH_TX_BUFFER_SIZE   1536
 
#define AM335X_ETH_RX_BUFFER_COUNT   16
 
#define AM335X_ETH_RX_BUFFER_SIZE   1536
 
#define AM335X_ETH_IRQ_PRIORITY   1
 
#define CPSW_CORE0   0
 
#define CPSW_CORE1   1
 
#define CPSW_CORE2   2
 
#define CPSW_PORT0   0
 
#define CPSW_PORT1   1
 
#define CPSW_PORT2   2
 
#define CPSW_CH0   0
 
#define CPSW_CH1   1
 
#define CPSW_CH2   2
 
#define CPSW_CH3   3
 
#define CPSW_CH4   4
 
#define CPSW_CH5   5
 
#define CPSW_CH6   6
 
#define CPSW_CH7   7
 
#define CM_PER_CPGMAC0_CLKCTRL_R   HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL)
 
#define CM_PER_CPSW_CLKSTCTRL_R   HWREG(SOC_PRCM_REGS + CM_PER_CPSW_CLKSTCTRL)
 
#define CONTROL_MAC_ID_LO_R(n)   HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(n))
 
#define CONTROL_MAC_ID_HI_R(n)   HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(n))
 
#define CONTROL_GMII_SEL_R   HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL)
 
#define CONTROL_CONF_GPMC_A_R(n)   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(n))
 
#define CONTROL_CONF_MII1_COL_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL)
 
#define CONTROL_CONF_MII1_CRS_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS)
 
#define CONTROL_CONF_MII1_RXERR_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR)
 
#define CONTROL_CONF_MII1_TXEN_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN)
 
#define CONTROL_CONF_MII1_RXDV_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV)
 
#define CONTROL_CONF_MII1_TXD3_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3)
 
#define CONTROL_CONF_MII1_TXD2_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2)
 
#define CONTROL_CONF_MII1_TXD1_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1)
 
#define CONTROL_CONF_MII1_TXD0_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0)
 
#define CONTROL_CONF_MII1_TXCLK_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK)
 
#define CONTROL_CONF_MII1_RXCLK_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK)
 
#define CONTROL_CONF_MII1_RXD3_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3)
 
#define CONTROL_CONF_MII1_RXD2_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2)
 
#define CONTROL_CONF_MII1_RXD1_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1)
 
#define CONTROL_CONF_MII1_RXD0_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0)
 
#define CONTROL_CONF_RMII1_REFCLK_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK)
 
#define CONTROL_CONF_MDIO_DATA_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA)
 
#define CONTROL_CONF_MDIO_CLK_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK)
 
#define CPSW_ALE_IDVER_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_IDVER)
 
#define CPSW_ALE_CONTROL_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_CONTROL)
 
#define CPSW_ALE_PRESCALE_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PRESCALE)
 
#define CPSW_ALE_UNKNOWN_VLAN_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_UNKNOWN_VLAN)
 
#define CPSW_ALE_TBLCTL_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLCTL)
 
#define CPSW_ALE_TBLW_R(n)   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLW(n))
 
#define CPSW_ALE_PORTCTL_R(n)   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PORTCTL(n))
 
#define CPSW_CPDMA_TX_IDVER_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_IDVER)
 
#define CPSW_CPDMA_TX_CONTROL_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_CONTROL)
 
#define CPSW_CPDMA_TX_TEARDOWN_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_TEARDOWN)
 
#define CPSW_CPDMA_RX_IDVER_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_IDVER)
 
#define CPSW_CPDMA_RX_CONTROL_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_CONTROL)
 
#define CPSW_CPDMA_RX_TEARDOWN_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_TEARDOWN)
 
#define CPSW_CPDMA_CPDMA_SOFT_RESET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_SOFT_RESET)
 
#define CPSW_CPDMA_DMACONTROL_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMACONTROL)
 
#define CPSW_CPDMA_DMASTATUS_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMASTATUS)
 
#define CPSW_CPDMA_RX_BUFFER_OFFSET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_BUFFER_OFFSET)
 
#define CPSW_CPDMA_EMCONTROL_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_EMCONTROL)
 
#define CPSW_CPDMA_TX_PRI_RATE_R(n)   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_PRI_RATE(n))
 
#define CPSW_CPDMA_TX_INTSTAT_RAW_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_RAW)
 
#define CPSW_CPDMA_TX_INTSTAT_MASKED_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_MASKED)
 
#define CPSW_CPDMA_TX_INTMASK_SET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_SET)
 
#define CPSW_CPDMA_TX_INTMASK_CLEAR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_CLEAR)
 
#define CPSW_CPDMA_CPDMA_IN_VECTOR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_IN_VECTOR)
 
#define CPSW_CPDMA_CPDMA_EOI_VECTOR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_EOI_VECTOR)
 
#define CPSW_CPDMA_RX_INTSTAT_RAW_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_RAW)
 
#define CPSW_CPDMA_RX_INTSTAT_MASKED_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_MASKED)
 
#define CPSW_CPDMA_RX_INTMASK_SET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_SET)
 
#define CPSW_CPDMA_RX_INTMASK_CLEAR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_CLEAR)
 
#define CPSW_CPDMA_DMA_INTSTAT_RAW_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_RAW)
 
#define CPSW_CPDMA_DMA_INTSTAT_MASKED_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_MASKED)
 
#define CPSW_CPDMA_DMA_INTMASK_SET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_SET)
 
#define CPSW_CPDMA_DMA_INTMASK_CLEAR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_CLEAR)
 
#define CPSW_CPDMA_RX_PENDTHRESH_R(n)   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_PENDTHRESH(n))
 
#define CPSW_CPDMA_RX_FREEBUFFER_R(n)   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_FREEBUFFER(n))
 
#define CPSW_CPDMA_TX_HDP_R(n)   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_HDP(n))
 
#define CPSW_CPDMA_RX_HDP_R(n)   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_HDP(n))
 
#define CPSW_CPDMA_TX_CP_R(n)   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_CP(n))
 
#define CPSW_CPDMA_RX_CP_R(n)   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_CP(n))
 
#define CPSW_PORT0_CONTROL_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CONTROL)
 
#define CPSW_PORT0_MAX_BLKS_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_MAX_BLKS)
 
#define CPSW_PORT0_BLK_CNT_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_BLK_CNT)
 
#define CPSW_PORT0_TX_IN_CTL_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TX_IN_CTL)
 
#define CPSW_PORT0_PORT_VLAN_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_PORT_VLAN)
 
#define CPSW_PORT0_TX_PRI_MAP_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TX_PRI_MAP)
 
#define CPSW_PORT0_CPDMA_TX_PRI_MAP0_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)
 
#define CPSW_PORT0_CPDMA_RX_CH_MAP0_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)
 
#define CPSW_PORT0_RX_DSCP_PRI_MAP_R(n)   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))
 
#define CPSW_PORT0_TS_SEQ_MTYPE_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TS_SEQ_MTYPE)
 
#define CPSW_PORT0_SA_LO_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SA_LO)
 
#define CPSW_PORT0_SA_HI_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SA_HI)
 
#define CPSW_PORT0_SEND_PERCENT_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SEND_PERCENT)
 
#define CPSW_PORT1_CONTROL_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CONTROL)
 
#define CPSW_PORT1_MAX_BLKS_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_MAX_BLKS)
 
#define CPSW_PORT1_BLK_CNT_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_BLK_CNT)
 
#define CPSW_PORT1_TX_IN_CTL_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TX_IN_CTL)
 
#define CPSW_PORT1_PORT_VLAN_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_PORT_VLAN)
 
#define CPSW_PORT1_TX_PRI_MAP_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TX_PRI_MAP)
 
#define CPSW_PORT1_CPDMA_TX_PRI_MAP0_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)
 
#define CPSW_PORT1_CPDMA_RX_CH_MAP0_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)
 
#define CPSW_PORT1_RX_DSCP_PRI_MAP_R(n)   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))
 
#define CPSW_PORT1_TS_SEQ_MTYPE_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TS_SEQ_MTYPE)
 
#define CPSW_PORT1_SA_LO_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SA_LO)
 
#define CPSW_PORT1_SA_HI_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SA_HI)
 
#define CPSW_PORT1_SEND_PERCENT_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SEND_PERCENT)
 
#define CPSW_PORT2_CONTROL_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CONTROL)
 
#define CPSW_PORT2_MAX_BLKS_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_MAX_BLKS)
 
#define CPSW_PORT2_BLK_CNT_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_BLK_CNT)
 
#define CPSW_PORT2_TX_IN_CTL_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TX_IN_CTL)
 
#define CPSW_PORT2_PORT_VLAN_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_PORT_VLAN)
 
#define CPSW_PORT2_TX_PRI_MAP_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TX_PRI_MAP)
 
#define CPSW_PORT2_CPDMA_TX_PRI_MAP0_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)
 
#define CPSW_PORT2_CPDMA_RX_CH_MAP0_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)
 
#define CPSW_PORT2_RX_DSCP_PRI_MAP_R(n)   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))
 
#define CPSW_PORT2_TS_SEQ_MTYPE_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TS_SEQ_MTYPE)
 
#define CPSW_PORT2_SA_LO_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SA_LO)
 
#define CPSW_PORT2_SA_HI_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SA_HI)
 
#define CPSW_PORT2_SEND_PERCENT_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SEND_PERCENT)
 
#define CPSW_SL1_IDVER_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_IDVER)
 
#define CPSW_SL1_MACCONTROL_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACCONTROL)
 
#define CPSW_SL1_MACSTATUS_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACSTATUS)
 
#define CPSW_SL1_SOFT_RESET_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_SOFT_RESET)
 
#define CPSW_SL1_RX_MAXLEN_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_MAXLEN)
 
#define CPSW_SL1_BOFFTEST_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_BOFFTEST)
 
#define CPSW_SL1_RX_PAUSE_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PAUSE)
 
#define CPSW_SL1_TX_PAUSE_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_PAUSE)
 
#define CPSW_SL1_EMCONTROL_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_EMCONTROL)
 
#define CPSW_SL1_RX_PRI_MAP_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PRI_MAP)
 
#define CPSW_SL1_TX_GAP_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_GAP)
 
#define CPSW_SL2_IDVER_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_IDVER)
 
#define CPSW_SL2_MACCONTROL_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACCONTROL)
 
#define CPSW_SL2_MACSTATUS_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACSTATUS)
 
#define CPSW_SL2_SOFT_RESET_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_SOFT_RESET)
 
#define CPSW_SL2_RX_MAXLEN_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_MAXLEN)
 
#define CPSW_SL2_BOFFTEST_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_BOFFTEST)
 
#define CPSW_SL2_RX_PAUSE_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PAUSE)
 
#define CPSW_SL2_TX_PAUSE_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_PAUSE)
 
#define CPSW_SL2_EMCONTROL_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_EMCONTROL)
 
#define CPSW_SL2_RX_PRI_MAP_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PRI_MAP)
 
#define CPSW_SL2_TX_GAP_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_GAP)
 
#define CPSW_SS_ID_VER_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_ID_VER)
 
#define CPSW_SS_CONTROL_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_CONTROL)
 
#define CPSW_SS_SOFT_RESET_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_RESET)
 
#define CPSW_SS_STAT_PORT_EN_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_STAT_PORT_EN)
 
#define CPSW_SS_PTYPE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_PTYPE)
 
#define CPSW_SS_SOFT_IDLE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_IDLE)
 
#define CPSW_SS_THRU_RATE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_THRU_RATE)
 
#define CPSW_SS_GAP_THRESH_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_GAP_THRESH)
 
#define CPSW_SS_TX_START_WDS_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TX_START_WDS)
 
#define CPSW_SS_FLOW_CONTROL_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_FLOW_CONTROL)
 
#define CPSW_SS_VLAN_LTYPE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_VLAN_LTYPE)
 
#define CPSW_SS_TS_LTYPE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TS_LTYPE)
 
#define CPSW_SS_DLR_LTYPE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_DLR_LTYPE)
 
#define CPSW_WR_IDVER_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_IDVER)
 
#define CPSW_WR_SOFT_RESET_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_SOFT_RESET)
 
#define CPSW_WR_CONTROL_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_CONTROL)
 
#define CPSW_WR_INT_CONTROL_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_INT_CONTROL)
 
#define CPSW_WR_C_RX_THRESH_EN_R(n)   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_THRESH_EN(n))
 
#define CPSW_WR_C_RX_EN_R(n)   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_EN(n))
 
#define CPSW_WR_C_TX_EN_R(n)   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_EN(n))
 
#define CPSW_WR_C_MISC_EN_R(n)   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_EN(n))
 
#define CPSW_WR_C_RX_THRESH_STAT_R(n)   HWREG(SOC_CPSW_WR_REGS +CPSW_WR_C_RX_THRESH_STAT(n))
 
#define CPSW_WR_C_RX_STAT_R(n)   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_STAT(n))
 
#define CPSW_WR_C_TX_STAT_R(n)   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_STAT(n))
 
#define CPSW_WR_C_MISC_STAT_R(n)   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_STAT(n))
 
#define CPSW_WR_C_RX_IMAX_R(n)   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_IMAX(n))
 
#define CPSW_WR_C_TX_IMAX_R(n)   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_IMAX(n))
 
#define CPSW_WR_RGMII_CTL_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_RGMII_CTL)
 
#define MDIO_REVID_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_REVID)
 
#define MDIO_CONTROL_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_CONTROL)
 
#define MDIO_ALIVE_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_ALIVE)
 
#define MDIO_LINK_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINK)
 
#define MDIO_LINKINTRAW_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTRAW)
 
#define MDIO_LINKINTMASKED_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTMASKED)
 
#define MDIO_USERINTRAW_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTRAW)
 
#define MDIO_USERINTMASKED_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKED)
 
#define MDIO_USERINTMASKSET_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKSET)
 
#define MDIO_USERINTMASKCLEAR_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKCLEAR)
 
#define MDIO_USERACCESS0_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERACCESS0)
 
#define MDIO_USERPHYSEL0_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERPHYSEL0)
 
#define MDIO_USERACCESS1_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERACCESS1)
 
#define MDIO_USERPHYSEL1_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERPHYSEL1)
 
#define CONTROL_GMII_SEL_GMII2_SEL_MII   0x00000000
 
#define CONTROL_GMII_SEL_GMII2_SEL_RMII   0x00000004
 
#define CONTROL_GMII_SEL_GMII2_SEL_RGMII   0x00000008
 
#define CONTROL_GMII_SEL_GMII1_SEL_MII   0x00000000
 
#define CONTROL_GMII_SEL_GMII1_SEL_RMII   0x00000001
 
#define CONTROL_GMII_SEL_GMII1_SEL_RGMII   0x00000002
 
#define CPSW_ALE_PORTCTL_PORT_STATE_DISABLED   0x00000000
 
#define CPSW_ALE_PORTCTL_PORT_STATE_BLOCKED   0x00000001
 
#define CPSW_ALE_PORTCTL_PORT_STATE_LEARN   0x00000002
 
#define CPSW_ALE_PORTCTL_PORT_STATE_FORWARD   0x00000003
 
#define CPSW_CPDMA_EOI_VECTOR_RX_THRESH_PULSE   0x00000000
 
#define CPSW_CPDMA_EOI_VECTOR_RX_PULSE   0x00000001
 
#define CPSW_CPDMA_EOI_VECTOR_TX_PULSE   0x00000002
 
#define CPSW_CPDMA_EOI_VECTOR_MISC_PULSE   0x00000003
 
#define CPSW_TX_WORD0_NEXT_DESC_POINTER   0xFFFFFFFF
 
#define CPSW_TX_WORD1_BUFFER_POINTER   0xFFFFFFFF
 
#define CPSW_TX_WORD2_BUFFER_OFFSET   0xFFFF0000
 
#define CPSW_TX_WORD2_BUFFER_LENGTH   0x0000FFFF
 
#define CPSW_TX_WORD3_SOP   0x80000000
 
#define CPSW_TX_WORD3_EOP   0x40000000
 
#define CPSW_TX_WORD3_OWNER   0x20000000
 
#define CPSW_TX_WORD3_EOQ   0x10000000
 
#define CPSW_TX_WORD3_TDOWN_CMPLT   0x08000000
 
#define CPSW_TX_WORD3_PASS_CRC   0x04000000
 
#define CPSW_TX_WORD3_TO_PORT_EN   0x00100000
 
#define CPSW_TX_WORD3_TO_PORT   0x00030000
 
#define CPSW_TX_WORD3_TO_PORT_1   0x00010000
 
#define CPSW_TX_WORD3_TO_PORT_2   0x00020000
 
#define CPSW_TX_WORD3_PACKET_LENGTH   0x000007FF
 
#define CPSW_RX_WORD0_NEXT_DESC_POINTER   0xFFFFFFFF
 
#define CPSW_RX_WORD1_BUFFER_POINTER   0xFFFFFFFF
 
#define CPSW_RX_WORD2_BUFFER_OFFSET   0x07FF0000
 
#define CPSW_RX_WORD2_BUFFER_LENGTH   0x000007FF
 
#define CPSW_RX_WORD3_SOP   0x80000000
 
#define CPSW_RX_WORD3_EOP   0x40000000
 
#define CPSW_RX_WORD3_OWNER   0x20000000
 
#define CPSW_RX_WORD3_EOQ   0x10000000
 
#define CPSW_RX_WORD3_TDOWN_CMPLT   0x08000000
 
#define CPSW_RX_WORD3_PASS_CRC   0x04000000
 
#define CPSW_RX_WORD3_LONG   0x02000000
 
#define CPSW_RX_WORD3_SHORT   0x01000000
 
#define CPSW_RX_WORD3_CONTROL   0x00800000
 
#define CPSW_RX_WORD3_OVERRUN   0x00400000
 
#define CPSW_RX_WORD3_PKT_ERROR   0x00300000
 
#define CPSW_RX_WORD3_RX_VLAN_ENCAP   0x000C0000
 
#define CPSW_RX_WORD3_FROM_PORT   0x00030000
 
#define CPSW_RX_WORD3_FROM_PORT_1   0x00010000
 
#define CPSW_RX_WORD3_FROM_PORT_2   0x00020000
 
#define CPSW_RX_WORD3_PACKET_LENGTH   0x000007FF
 
#define CPSW_ALE_MAX_ENTRIES   1024
 
#define CPSW_ALE_WORD1_ENTRY_TYPE_MASK   (3 << 28)
 
#define CPSW_ALE_WORD1_ENTRY_TYPE_FREE   (0 << 28)
 
#define CPSW_ALE_WORD1_ENTRY_TYPE_ADDR   (1 << 28)
 
#define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN   (2 << 28)
 
#define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN_ADDR   (3 << 28)
 
#define CPSW_ALE_WORD1_MULTICAST   (1 << 8)
 
#define CPSW_ALE_WORD2_DLR_UNICAST   (1 << 5)
 
#define CPSW_ALE_WORD2_PORT_NUMBER_MASK   (3 << 2)
 
#define CPSW_ALE_WORD2_PORT_NUMBER(n)   ((n) << 2)
 
#define CPSW_ALE_WORD2_BLOCK   (1 << 1)
 
#define CPSW_ALE_WORD2_SECURE   (1 << 0)
 
#define CPSW_ALE_WORD1_UNICAST_TYPE_MASK   (3 << 30)
 
#define CPSW_ALE_WORD1_UNICAST_TYPE(n)   ((n) << 30)
 
#define CPSW_ALE_WORD2_PORT_LIST_MASK   (3 << 2)
 
#define CPSW_ALE_WORD2_PORT_LIST(n)   ((n) << 2)
 
#define CPSW_ALE_WORD2_SUPER   (1 << 1)
 
#define CPSW_ALE_WORD1_MCAST_FWD_STATE_MASK   (3 << 30)
 
#define CPSW_ALE_WORD1_MCAST_FWD_STATE(n)   ((n) << 30)
 
#define CPSW_ALE_WORD1_VLAN_ID_MASK   (4095 << 16)
 
#define CPSW_ALE_WORD1_VLAN_ID(n)   ((n) << 16)
 
#define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS_MASK   (7 << 24)
 
#define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS(n)   ((n) << 24)
 
#define CPSW_ALE_WORD0_REG_MCAST_FLOOD_MASK   (7 << 16)
 
#define CPSW_ALE_WORD0_REG_MCAST_FLOOD(n)   ((n) << 16)
 
#define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD_MASK   (7 << 8)
 
#define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD(n)   ((n) << 8)
 
#define CPSW_ALE_WORD0_VLAN_MEMBER_LIST_MASK   (7 << 0)
 
#define CPSW_ALE_WORD0_VLAN_MEMBER_LIST(n)   ((n) << 0)
 

Typedefs

typedef struct _Am335xTxBufferDesc Am335xTxBufferDesc
 TX buffer descriptor. More...
 
typedef struct _Am335xRxBufferDesc Am335xRxBufferDesc
 RX buffer descriptor. More...
 

Functions

error_t am335xEthInitPort1 (NetInterface *interface)
 AM335x Ethernet MAC initialization (port 1) More...
 
error_t am335xEthInitPort2 (NetInterface *interface)
 AM335x Ethernet MAC initialization (port 2) More...
 
void am335xEthInitInstance (NetInterface *interface)
 Initialize CPSW instance. More...
 
void am335xEthInitGpio (NetInterface *interface)
 
void am335xEthInitBufferDesc (NetInterface *interface)
 Initialize buffer descriptor lists. More...
 
void am335xEthTick (NetInterface *interface)
 AM335x Ethernet MAC timer handler. More...
 
void am335xEthEnableIrq (NetInterface *interface)
 Enable interrupts. More...
 
void am335xEthDisableIrq (NetInterface *interface)
 Disable interrupts. More...
 
void am335xEthTxIrqHandler (void)
 Ethernet MAC transmit interrupt. More...
 
void am335xEthRxIrqHandler (void)
 Ethernet MAC receive interrupt. More...
 
void am335xEthEventHandler (NetInterface *interface)
 AM335x Ethernet MAC event handler. More...
 
error_t am335xEthSendPacketPort1 (NetInterface *interface, const NetBuffer *buffer, size_t offset)
 Send a packet (port 1) More...
 
error_t am335xEthSendPacketPort2 (NetInterface *interface, const NetBuffer *buffer, size_t offset)
 Send a packet (port 2) More...
 
error_t am335xEthUpdateMacAddrFilter (NetInterface *interface)
 Configure MAC address filtering. More...
 
error_t am335xEthUpdateMacConfig (NetInterface *interface)
 Adjust MAC configuration parameters for proper operation. More...
 
void am335xEthWritePhyReg (uint8_t phyAddr, uint8_t regAddr, uint16_t data)
 Write PHY register. More...
 
uint16_t am335xEthReadPhyReg (uint8_t phyAddr, uint8_t regAddr)
 Read PHY register. More...
 
void am335xEthWriteEntry (uint_t index, const Am335xAleEntry *entry)
 Write an ALE table entry. More...
 
void am335xEthReadEntry (uint_t index, Am335xAleEntry *entry)
 Read an ALE table entry. More...
 
uint_t am335xEthFindFreeEntry (void)
 Find a free entry in the ALE table. More...
 
uint_t am335xEthFindVlanEntry (uint_t vlanId)
 Search the ALE table for the specified VLAN entry. More...
 
uint_t am335xEthFindVlanAddrEntry (uint_t vlanId, MacAddr *macAddr)
 Search the ALE table for the specified VLAN/address entry. More...
 
error_t am335xEthAddVlanEntry (uint_t port, uint_t vlanId)
 Add a VLAN entry in the ALE table. More...
 
error_t am335xEthAddVlanAddrEntry (uint_t port, uint_t vlanId, MacAddr *macAddr)
 Add a VLAN/address entry in the ALE table. More...
 
error_t am335xEthDeleteVlanAddrEntry (uint_t port, uint_t vlanId, MacAddr *macAddr)
 Remove a VLAN/address entry from the ALE table. More...
 

Variables

const NicDriver am335xEthPort1Driver
 AM335x Ethernet MAC driver (port1) More...
 
const NicDriver am335xEthPort2Driver
 AM335x Ethernet MAC driver (port2) More...
 

Detailed Description

Sitara AM335x Ethernet MAC controller.

License

Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author
Oryx Embedded SARL (www.oryx-embedded.com)
Version
1.9.0

Definition in file am335x_eth_driver.h.

Macro Definition Documentation

◆ AM335X_ETH_IRQ_PRIORITY

#define AM335X_ETH_IRQ_PRIORITY   1

Definition at line 65 of file am335x_eth_driver.h.

◆ AM335X_ETH_RX_BUFFER_COUNT

#define AM335X_ETH_RX_BUFFER_COUNT   16

Definition at line 51 of file am335x_eth_driver.h.

◆ AM335X_ETH_RX_BUFFER_SIZE

#define AM335X_ETH_RX_BUFFER_SIZE   1536

Definition at line 58 of file am335x_eth_driver.h.

◆ AM335X_ETH_TX_BUFFER_COUNT

#define AM335X_ETH_TX_BUFFER_COUNT   16

Definition at line 37 of file am335x_eth_driver.h.

◆ AM335X_ETH_TX_BUFFER_SIZE

#define AM335X_ETH_TX_BUFFER_SIZE   1536

Definition at line 44 of file am335x_eth_driver.h.

◆ CM_PER_CPGMAC0_CLKCTRL_R

#define CM_PER_CPGMAC0_CLKCTRL_R   HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL)

Definition at line 91 of file am335x_eth_driver.h.

◆ CM_PER_CPSW_CLKSTCTRL_R

#define CM_PER_CPSW_CLKSTCTRL_R   HWREG(SOC_PRCM_REGS + CM_PER_CPSW_CLKSTCTRL)

Definition at line 92 of file am335x_eth_driver.h.

◆ CONTROL_CONF_GPMC_A_R

#define CONTROL_CONF_GPMC_A_R (   n)    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(n))

Definition at line 98 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MDIO_CLK_R

#define CONTROL_CONF_MDIO_CLK_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK)

Definition at line 116 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MDIO_DATA_R

#define CONTROL_CONF_MDIO_DATA_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA)

Definition at line 115 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_COL_R

#define CONTROL_CONF_MII1_COL_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL)

Definition at line 99 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_CRS_R

#define CONTROL_CONF_MII1_CRS_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS)

Definition at line 100 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_RXCLK_R

#define CONTROL_CONF_MII1_RXCLK_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK)

Definition at line 109 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_RXD0_R

#define CONTROL_CONF_MII1_RXD0_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0)

Definition at line 113 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_RXD1_R

#define CONTROL_CONF_MII1_RXD1_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1)

Definition at line 112 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_RXD2_R

#define CONTROL_CONF_MII1_RXD2_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2)

Definition at line 111 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_RXD3_R

#define CONTROL_CONF_MII1_RXD3_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3)

Definition at line 110 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_RXDV_R

#define CONTROL_CONF_MII1_RXDV_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV)

Definition at line 103 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_RXERR_R

#define CONTROL_CONF_MII1_RXERR_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR)

Definition at line 101 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_TXCLK_R

#define CONTROL_CONF_MII1_TXCLK_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK)

Definition at line 108 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_TXD0_R

#define CONTROL_CONF_MII1_TXD0_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0)

Definition at line 107 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_TXD1_R

#define CONTROL_CONF_MII1_TXD1_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1)

Definition at line 106 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_TXD2_R

#define CONTROL_CONF_MII1_TXD2_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2)

Definition at line 105 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_TXD3_R

#define CONTROL_CONF_MII1_TXD3_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3)

Definition at line 104 of file am335x_eth_driver.h.

◆ CONTROL_CONF_MII1_TXEN_R

#define CONTROL_CONF_MII1_TXEN_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN)

Definition at line 102 of file am335x_eth_driver.h.

◆ CONTROL_CONF_RMII1_REFCLK_R

#define CONTROL_CONF_RMII1_REFCLK_R   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK)

Definition at line 114 of file am335x_eth_driver.h.

◆ CONTROL_GMII_SEL_GMII1_SEL_MII

#define CONTROL_GMII_SEL_GMII1_SEL_MII   0x00000000

Definition at line 281 of file am335x_eth_driver.h.

◆ CONTROL_GMII_SEL_GMII1_SEL_RGMII

#define CONTROL_GMII_SEL_GMII1_SEL_RGMII   0x00000002

Definition at line 283 of file am335x_eth_driver.h.

◆ CONTROL_GMII_SEL_GMII1_SEL_RMII

#define CONTROL_GMII_SEL_GMII1_SEL_RMII   0x00000001

Definition at line 282 of file am335x_eth_driver.h.

◆ CONTROL_GMII_SEL_GMII2_SEL_MII

#define CONTROL_GMII_SEL_GMII2_SEL_MII   0x00000000

Definition at line 278 of file am335x_eth_driver.h.

◆ CONTROL_GMII_SEL_GMII2_SEL_RGMII

#define CONTROL_GMII_SEL_GMII2_SEL_RGMII   0x00000008

Definition at line 280 of file am335x_eth_driver.h.

◆ CONTROL_GMII_SEL_GMII2_SEL_RMII

#define CONTROL_GMII_SEL_GMII2_SEL_RMII   0x00000004

Definition at line 279 of file am335x_eth_driver.h.

◆ CONTROL_GMII_SEL_R

#define CONTROL_GMII_SEL_R   HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL)

Definition at line 97 of file am335x_eth_driver.h.

◆ CONTROL_MAC_ID_HI_R

#define CONTROL_MAC_ID_HI_R (   n)    HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(n))

Definition at line 96 of file am335x_eth_driver.h.

◆ CONTROL_MAC_ID_LO_R

#define CONTROL_MAC_ID_LO_R (   n)    HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(n))

Definition at line 95 of file am335x_eth_driver.h.

◆ CPSW_ALE_CONTROL_R

#define CPSW_ALE_CONTROL_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_CONTROL)

Definition at line 120 of file am335x_eth_driver.h.

◆ CPSW_ALE_IDVER_R

#define CPSW_ALE_IDVER_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_IDVER)

Definition at line 119 of file am335x_eth_driver.h.

◆ CPSW_ALE_MAX_ENTRIES

#define CPSW_ALE_MAX_ENTRIES   1024

Definition at line 337 of file am335x_eth_driver.h.

◆ CPSW_ALE_PORTCTL_PORT_STATE_BLOCKED

#define CPSW_ALE_PORTCTL_PORT_STATE_BLOCKED   0x00000001

Definition at line 287 of file am335x_eth_driver.h.

◆ CPSW_ALE_PORTCTL_PORT_STATE_DISABLED

#define CPSW_ALE_PORTCTL_PORT_STATE_DISABLED   0x00000000

Definition at line 286 of file am335x_eth_driver.h.

◆ CPSW_ALE_PORTCTL_PORT_STATE_FORWARD

#define CPSW_ALE_PORTCTL_PORT_STATE_FORWARD   0x00000003

Definition at line 289 of file am335x_eth_driver.h.

◆ CPSW_ALE_PORTCTL_PORT_STATE_LEARN

#define CPSW_ALE_PORTCTL_PORT_STATE_LEARN   0x00000002

Definition at line 288 of file am335x_eth_driver.h.

◆ CPSW_ALE_PORTCTL_R

#define CPSW_ALE_PORTCTL_R (   n)    HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PORTCTL(n))

Definition at line 125 of file am335x_eth_driver.h.

◆ CPSW_ALE_PRESCALE_R

#define CPSW_ALE_PRESCALE_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PRESCALE)

Definition at line 121 of file am335x_eth_driver.h.

◆ CPSW_ALE_TBLCTL_R

#define CPSW_ALE_TBLCTL_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLCTL)

Definition at line 123 of file am335x_eth_driver.h.

◆ CPSW_ALE_TBLW_R

#define CPSW_ALE_TBLW_R (   n)    HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLW(n))

Definition at line 124 of file am335x_eth_driver.h.

◆ CPSW_ALE_UNKNOWN_VLAN_R

#define CPSW_ALE_UNKNOWN_VLAN_R   HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_UNKNOWN_VLAN)

Definition at line 122 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS

#define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS (   n)    ((n) << 24)

Definition at line 367 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS_MASK

#define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS_MASK   (7 << 24)

Definition at line 366 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD0_REG_MCAST_FLOOD

#define CPSW_ALE_WORD0_REG_MCAST_FLOOD (   n)    ((n) << 16)

Definition at line 369 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD0_REG_MCAST_FLOOD_MASK

#define CPSW_ALE_WORD0_REG_MCAST_FLOOD_MASK   (7 << 16)

Definition at line 368 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD0_UNREG_MCAST_FLOOD

#define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD (   n)    ((n) << 8)

Definition at line 371 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD0_UNREG_MCAST_FLOOD_MASK

#define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD_MASK   (7 << 8)

Definition at line 370 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD0_VLAN_MEMBER_LIST

#define CPSW_ALE_WORD0_VLAN_MEMBER_LIST (   n)    ((n) << 0)

Definition at line 373 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD0_VLAN_MEMBER_LIST_MASK

#define CPSW_ALE_WORD0_VLAN_MEMBER_LIST_MASK   (7 << 0)

Definition at line 372 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_ENTRY_TYPE_ADDR

#define CPSW_ALE_WORD1_ENTRY_TYPE_ADDR   (1 << 28)

Definition at line 342 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_ENTRY_TYPE_FREE

#define CPSW_ALE_WORD1_ENTRY_TYPE_FREE   (0 << 28)

Definition at line 341 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_ENTRY_TYPE_MASK

#define CPSW_ALE_WORD1_ENTRY_TYPE_MASK   (3 << 28)

Definition at line 340 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_ENTRY_TYPE_VLAN

#define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN   (2 << 28)

Definition at line 343 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_ENTRY_TYPE_VLAN_ADDR

#define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN_ADDR   (3 << 28)

Definition at line 344 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_MCAST_FWD_STATE

#define CPSW_ALE_WORD1_MCAST_FWD_STATE (   n)    ((n) << 30)

Definition at line 361 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_MCAST_FWD_STATE_MASK

#define CPSW_ALE_WORD1_MCAST_FWD_STATE_MASK   (3 << 30)

Definition at line 360 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_MULTICAST

#define CPSW_ALE_WORD1_MULTICAST   (1 << 8)

Definition at line 345 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_UNICAST_TYPE

#define CPSW_ALE_WORD1_UNICAST_TYPE (   n)    ((n) << 30)

Definition at line 354 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_UNICAST_TYPE_MASK

#define CPSW_ALE_WORD1_UNICAST_TYPE_MASK   (3 << 30)

Definition at line 353 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_VLAN_ID

#define CPSW_ALE_WORD1_VLAN_ID (   n)    ((n) << 16)

Definition at line 365 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD1_VLAN_ID_MASK

#define CPSW_ALE_WORD1_VLAN_ID_MASK   (4095 << 16)

Definition at line 364 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD2_BLOCK

#define CPSW_ALE_WORD2_BLOCK   (1 << 1)

Definition at line 351 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD2_DLR_UNICAST

#define CPSW_ALE_WORD2_DLR_UNICAST   (1 << 5)

Definition at line 348 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD2_PORT_LIST

#define CPSW_ALE_WORD2_PORT_LIST (   n)    ((n) << 2)

Definition at line 358 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD2_PORT_LIST_MASK

#define CPSW_ALE_WORD2_PORT_LIST_MASK   (3 << 2)

Definition at line 357 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD2_PORT_NUMBER

#define CPSW_ALE_WORD2_PORT_NUMBER (   n)    ((n) << 2)

Definition at line 350 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD2_PORT_NUMBER_MASK

#define CPSW_ALE_WORD2_PORT_NUMBER_MASK   (3 << 2)

Definition at line 349 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD2_SECURE

#define CPSW_ALE_WORD2_SECURE   (1 << 0)

Definition at line 352 of file am335x_eth_driver.h.

◆ CPSW_ALE_WORD2_SUPER

#define CPSW_ALE_WORD2_SUPER   (1 << 1)

Definition at line 359 of file am335x_eth_driver.h.

◆ CPSW_CH0

#define CPSW_CH0   0

Definition at line 81 of file am335x_eth_driver.h.

◆ CPSW_CH1

#define CPSW_CH1   1

Definition at line 82 of file am335x_eth_driver.h.

◆ CPSW_CH2

#define CPSW_CH2   2

Definition at line 83 of file am335x_eth_driver.h.

◆ CPSW_CH3

#define CPSW_CH3   3

Definition at line 84 of file am335x_eth_driver.h.

◆ CPSW_CH4

#define CPSW_CH4   4

Definition at line 85 of file am335x_eth_driver.h.

◆ CPSW_CH5

#define CPSW_CH5   5

Definition at line 86 of file am335x_eth_driver.h.

◆ CPSW_CH6

#define CPSW_CH6   6

Definition at line 87 of file am335x_eth_driver.h.

◆ CPSW_CH7

#define CPSW_CH7   7

Definition at line 88 of file am335x_eth_driver.h.

◆ CPSW_CORE0

#define CPSW_CORE0   0

Definition at line 71 of file am335x_eth_driver.h.

◆ CPSW_CORE1

#define CPSW_CORE1   1

Definition at line 72 of file am335x_eth_driver.h.

◆ CPSW_CORE2

#define CPSW_CORE2   2

Definition at line 73 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_CPDMA_EOI_VECTOR_R

#define CPSW_CPDMA_CPDMA_EOI_VECTOR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_EOI_VECTOR)

Definition at line 145 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_CPDMA_IN_VECTOR_R

#define CPSW_CPDMA_CPDMA_IN_VECTOR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_IN_VECTOR)

Definition at line 144 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_CPDMA_SOFT_RESET_R

#define CPSW_CPDMA_CPDMA_SOFT_RESET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_SOFT_RESET)

Definition at line 134 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_DMA_INTMASK_CLEAR_R

#define CPSW_CPDMA_DMA_INTMASK_CLEAR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_CLEAR)

Definition at line 153 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_DMA_INTMASK_SET_R

#define CPSW_CPDMA_DMA_INTMASK_SET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_SET)

Definition at line 152 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_DMA_INTSTAT_MASKED_R

#define CPSW_CPDMA_DMA_INTSTAT_MASKED_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_MASKED)

Definition at line 151 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_DMA_INTSTAT_RAW_R

#define CPSW_CPDMA_DMA_INTSTAT_RAW_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_RAW)

Definition at line 150 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_DMACONTROL_R

#define CPSW_CPDMA_DMACONTROL_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMACONTROL)

Definition at line 135 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_DMASTATUS_R

#define CPSW_CPDMA_DMASTATUS_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMASTATUS)

Definition at line 136 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_EMCONTROL_R

#define CPSW_CPDMA_EMCONTROL_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_EMCONTROL)

Definition at line 138 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_EOI_VECTOR_MISC_PULSE

#define CPSW_CPDMA_EOI_VECTOR_MISC_PULSE   0x00000003

Definition at line 295 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_EOI_VECTOR_RX_PULSE

#define CPSW_CPDMA_EOI_VECTOR_RX_PULSE   0x00000001

Definition at line 293 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_EOI_VECTOR_RX_THRESH_PULSE

#define CPSW_CPDMA_EOI_VECTOR_RX_THRESH_PULSE   0x00000000

Definition at line 292 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_EOI_VECTOR_TX_PULSE

#define CPSW_CPDMA_EOI_VECTOR_TX_PULSE   0x00000002

Definition at line 294 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_BUFFER_OFFSET_R

#define CPSW_CPDMA_RX_BUFFER_OFFSET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_BUFFER_OFFSET)

Definition at line 137 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_CONTROL_R

#define CPSW_CPDMA_RX_CONTROL_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_CONTROL)

Definition at line 132 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_CP_R

#define CPSW_CPDMA_RX_CP_R (   n)    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_CP(n))

Definition at line 159 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_FREEBUFFER_R

#define CPSW_CPDMA_RX_FREEBUFFER_R (   n)    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_FREEBUFFER(n))

Definition at line 155 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_HDP_R

#define CPSW_CPDMA_RX_HDP_R (   n)    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_HDP(n))

Definition at line 157 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_IDVER_R

#define CPSW_CPDMA_RX_IDVER_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_IDVER)

Definition at line 131 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_INTMASK_CLEAR_R

#define CPSW_CPDMA_RX_INTMASK_CLEAR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_CLEAR)

Definition at line 149 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_INTMASK_SET_R

#define CPSW_CPDMA_RX_INTMASK_SET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_SET)

Definition at line 148 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_INTSTAT_MASKED_R

#define CPSW_CPDMA_RX_INTSTAT_MASKED_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_MASKED)

Definition at line 147 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_INTSTAT_RAW_R

#define CPSW_CPDMA_RX_INTSTAT_RAW_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_RAW)

Definition at line 146 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_PENDTHRESH_R

#define CPSW_CPDMA_RX_PENDTHRESH_R (   n)    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_PENDTHRESH(n))

Definition at line 154 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_RX_TEARDOWN_R

#define CPSW_CPDMA_RX_TEARDOWN_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_TEARDOWN)

Definition at line 133 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_CONTROL_R

#define CPSW_CPDMA_TX_CONTROL_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_CONTROL)

Definition at line 129 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_CP_R

#define CPSW_CPDMA_TX_CP_R (   n)    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_CP(n))

Definition at line 158 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_HDP_R

#define CPSW_CPDMA_TX_HDP_R (   n)    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_HDP(n))

Definition at line 156 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_IDVER_R

#define CPSW_CPDMA_TX_IDVER_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_IDVER)

Definition at line 128 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_INTMASK_CLEAR_R

#define CPSW_CPDMA_TX_INTMASK_CLEAR_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_CLEAR)

Definition at line 143 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_INTMASK_SET_R

#define CPSW_CPDMA_TX_INTMASK_SET_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_SET)

Definition at line 142 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_INTSTAT_MASKED_R

#define CPSW_CPDMA_TX_INTSTAT_MASKED_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_MASKED)

Definition at line 141 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_INTSTAT_RAW_R

#define CPSW_CPDMA_TX_INTSTAT_RAW_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_RAW)

Definition at line 140 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_PRI_RATE_R

#define CPSW_CPDMA_TX_PRI_RATE_R (   n)    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_PRI_RATE(n))

Definition at line 139 of file am335x_eth_driver.h.

◆ CPSW_CPDMA_TX_TEARDOWN_R

#define CPSW_CPDMA_TX_TEARDOWN_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_TEARDOWN)

Definition at line 130 of file am335x_eth_driver.h.

◆ CPSW_PORT0

#define CPSW_PORT0   0

Definition at line 76 of file am335x_eth_driver.h.

◆ CPSW_PORT0_BLK_CNT_R

#define CPSW_PORT0_BLK_CNT_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_BLK_CNT)

Definition at line 164 of file am335x_eth_driver.h.

◆ CPSW_PORT0_CONTROL_R

#define CPSW_PORT0_CONTROL_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CONTROL)

Definition at line 162 of file am335x_eth_driver.h.

◆ CPSW_PORT0_CPDMA_RX_CH_MAP0_R

#define CPSW_PORT0_CPDMA_RX_CH_MAP0_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)

Definition at line 169 of file am335x_eth_driver.h.

◆ CPSW_PORT0_CPDMA_TX_PRI_MAP0_R

#define CPSW_PORT0_CPDMA_TX_PRI_MAP0_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)

Definition at line 168 of file am335x_eth_driver.h.

◆ CPSW_PORT0_MAX_BLKS_R

#define CPSW_PORT0_MAX_BLKS_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_MAX_BLKS)

Definition at line 163 of file am335x_eth_driver.h.

◆ CPSW_PORT0_PORT_VLAN_R

#define CPSW_PORT0_PORT_VLAN_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_PORT_VLAN)

Definition at line 166 of file am335x_eth_driver.h.

◆ CPSW_PORT0_RX_DSCP_PRI_MAP_R

#define CPSW_PORT0_RX_DSCP_PRI_MAP_R (   n)    HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))

Definition at line 170 of file am335x_eth_driver.h.

◆ CPSW_PORT0_SA_HI_R

#define CPSW_PORT0_SA_HI_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SA_HI)

Definition at line 173 of file am335x_eth_driver.h.

◆ CPSW_PORT0_SA_LO_R

#define CPSW_PORT0_SA_LO_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SA_LO)

Definition at line 172 of file am335x_eth_driver.h.

◆ CPSW_PORT0_SEND_PERCENT_R

#define CPSW_PORT0_SEND_PERCENT_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SEND_PERCENT)

Definition at line 174 of file am335x_eth_driver.h.

◆ CPSW_PORT0_TS_SEQ_MTYPE_R

#define CPSW_PORT0_TS_SEQ_MTYPE_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TS_SEQ_MTYPE)

Definition at line 171 of file am335x_eth_driver.h.

◆ CPSW_PORT0_TX_IN_CTL_R

#define CPSW_PORT0_TX_IN_CTL_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TX_IN_CTL)

Definition at line 165 of file am335x_eth_driver.h.

◆ CPSW_PORT0_TX_PRI_MAP_R

#define CPSW_PORT0_TX_PRI_MAP_R   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TX_PRI_MAP)

Definition at line 167 of file am335x_eth_driver.h.

◆ CPSW_PORT1

#define CPSW_PORT1   1

Definition at line 77 of file am335x_eth_driver.h.

◆ CPSW_PORT1_BLK_CNT_R

#define CPSW_PORT1_BLK_CNT_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_BLK_CNT)

Definition at line 178 of file am335x_eth_driver.h.

◆ CPSW_PORT1_CONTROL_R

#define CPSW_PORT1_CONTROL_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CONTROL)

Definition at line 176 of file am335x_eth_driver.h.

◆ CPSW_PORT1_CPDMA_RX_CH_MAP0_R

#define CPSW_PORT1_CPDMA_RX_CH_MAP0_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)

Definition at line 183 of file am335x_eth_driver.h.

◆ CPSW_PORT1_CPDMA_TX_PRI_MAP0_R

#define CPSW_PORT1_CPDMA_TX_PRI_MAP0_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)

Definition at line 182 of file am335x_eth_driver.h.

◆ CPSW_PORT1_MAX_BLKS_R

#define CPSW_PORT1_MAX_BLKS_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_MAX_BLKS)

Definition at line 177 of file am335x_eth_driver.h.

◆ CPSW_PORT1_PORT_VLAN_R

#define CPSW_PORT1_PORT_VLAN_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_PORT_VLAN)

Definition at line 180 of file am335x_eth_driver.h.

◆ CPSW_PORT1_RX_DSCP_PRI_MAP_R

#define CPSW_PORT1_RX_DSCP_PRI_MAP_R (   n)    HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))

Definition at line 184 of file am335x_eth_driver.h.

◆ CPSW_PORT1_SA_HI_R

#define CPSW_PORT1_SA_HI_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SA_HI)

Definition at line 187 of file am335x_eth_driver.h.

◆ CPSW_PORT1_SA_LO_R

#define CPSW_PORT1_SA_LO_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SA_LO)

Definition at line 186 of file am335x_eth_driver.h.

◆ CPSW_PORT1_SEND_PERCENT_R

#define CPSW_PORT1_SEND_PERCENT_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SEND_PERCENT)

Definition at line 188 of file am335x_eth_driver.h.

◆ CPSW_PORT1_TS_SEQ_MTYPE_R

#define CPSW_PORT1_TS_SEQ_MTYPE_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TS_SEQ_MTYPE)

Definition at line 185 of file am335x_eth_driver.h.

◆ CPSW_PORT1_TX_IN_CTL_R

#define CPSW_PORT1_TX_IN_CTL_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TX_IN_CTL)

Definition at line 179 of file am335x_eth_driver.h.

◆ CPSW_PORT1_TX_PRI_MAP_R

#define CPSW_PORT1_TX_PRI_MAP_R   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TX_PRI_MAP)

Definition at line 181 of file am335x_eth_driver.h.

◆ CPSW_PORT2

#define CPSW_PORT2   2

Definition at line 78 of file am335x_eth_driver.h.

◆ CPSW_PORT2_BLK_CNT_R

#define CPSW_PORT2_BLK_CNT_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_BLK_CNT)

Definition at line 192 of file am335x_eth_driver.h.

◆ CPSW_PORT2_CONTROL_R

#define CPSW_PORT2_CONTROL_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CONTROL)

Definition at line 190 of file am335x_eth_driver.h.

◆ CPSW_PORT2_CPDMA_RX_CH_MAP0_R

#define CPSW_PORT2_CPDMA_RX_CH_MAP0_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)

Definition at line 197 of file am335x_eth_driver.h.

◆ CPSW_PORT2_CPDMA_TX_PRI_MAP0_R

#define CPSW_PORT2_CPDMA_TX_PRI_MAP0_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)

Definition at line 196 of file am335x_eth_driver.h.

◆ CPSW_PORT2_MAX_BLKS_R

#define CPSW_PORT2_MAX_BLKS_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_MAX_BLKS)

Definition at line 191 of file am335x_eth_driver.h.

◆ CPSW_PORT2_PORT_VLAN_R

#define CPSW_PORT2_PORT_VLAN_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_PORT_VLAN)

Definition at line 194 of file am335x_eth_driver.h.

◆ CPSW_PORT2_RX_DSCP_PRI_MAP_R

#define CPSW_PORT2_RX_DSCP_PRI_MAP_R (   n)    HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))

Definition at line 198 of file am335x_eth_driver.h.

◆ CPSW_PORT2_SA_HI_R

#define CPSW_PORT2_SA_HI_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SA_HI)

Definition at line 201 of file am335x_eth_driver.h.

◆ CPSW_PORT2_SA_LO_R

#define CPSW_PORT2_SA_LO_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SA_LO)

Definition at line 200 of file am335x_eth_driver.h.

◆ CPSW_PORT2_SEND_PERCENT_R

#define CPSW_PORT2_SEND_PERCENT_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SEND_PERCENT)

Definition at line 202 of file am335x_eth_driver.h.

◆ CPSW_PORT2_TS_SEQ_MTYPE_R

#define CPSW_PORT2_TS_SEQ_MTYPE_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TS_SEQ_MTYPE)

Definition at line 199 of file am335x_eth_driver.h.

◆ CPSW_PORT2_TX_IN_CTL_R

#define CPSW_PORT2_TX_IN_CTL_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TX_IN_CTL)

Definition at line 193 of file am335x_eth_driver.h.

◆ CPSW_PORT2_TX_PRI_MAP_R

#define CPSW_PORT2_TX_PRI_MAP_R   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TX_PRI_MAP)

Definition at line 195 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD0_NEXT_DESC_POINTER

#define CPSW_RX_WORD0_NEXT_DESC_POINTER   0xFFFFFFFF

Definition at line 315 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD1_BUFFER_POINTER

#define CPSW_RX_WORD1_BUFFER_POINTER   0xFFFFFFFF

Definition at line 316 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD2_BUFFER_LENGTH

#define CPSW_RX_WORD2_BUFFER_LENGTH   0x000007FF

Definition at line 318 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD2_BUFFER_OFFSET

#define CPSW_RX_WORD2_BUFFER_OFFSET   0x07FF0000

Definition at line 317 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_CONTROL

#define CPSW_RX_WORD3_CONTROL   0x00800000

Definition at line 327 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_EOP

#define CPSW_RX_WORD3_EOP   0x40000000

Definition at line 320 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_EOQ

#define CPSW_RX_WORD3_EOQ   0x10000000

Definition at line 322 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_FROM_PORT

#define CPSW_RX_WORD3_FROM_PORT   0x00030000

Definition at line 331 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_FROM_PORT_1

#define CPSW_RX_WORD3_FROM_PORT_1   0x00010000

Definition at line 332 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_FROM_PORT_2

#define CPSW_RX_WORD3_FROM_PORT_2   0x00020000

Definition at line 333 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_LONG

#define CPSW_RX_WORD3_LONG   0x02000000

Definition at line 325 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_OVERRUN

#define CPSW_RX_WORD3_OVERRUN   0x00400000

Definition at line 328 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_OWNER

#define CPSW_RX_WORD3_OWNER   0x20000000

Definition at line 321 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_PACKET_LENGTH

#define CPSW_RX_WORD3_PACKET_LENGTH   0x000007FF

Definition at line 334 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_PASS_CRC

#define CPSW_RX_WORD3_PASS_CRC   0x04000000

Definition at line 324 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_PKT_ERROR

#define CPSW_RX_WORD3_PKT_ERROR   0x00300000

Definition at line 329 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_RX_VLAN_ENCAP

#define CPSW_RX_WORD3_RX_VLAN_ENCAP   0x000C0000

Definition at line 330 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_SHORT

#define CPSW_RX_WORD3_SHORT   0x01000000

Definition at line 326 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_SOP

#define CPSW_RX_WORD3_SOP   0x80000000

Definition at line 319 of file am335x_eth_driver.h.

◆ CPSW_RX_WORD3_TDOWN_CMPLT

#define CPSW_RX_WORD3_TDOWN_CMPLT   0x08000000

Definition at line 323 of file am335x_eth_driver.h.

◆ CPSW_SL1_BOFFTEST_R

#define CPSW_SL1_BOFFTEST_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_BOFFTEST)

Definition at line 210 of file am335x_eth_driver.h.

◆ CPSW_SL1_EMCONTROL_R

#define CPSW_SL1_EMCONTROL_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_EMCONTROL)

Definition at line 213 of file am335x_eth_driver.h.

◆ CPSW_SL1_IDVER_R

#define CPSW_SL1_IDVER_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_IDVER)

Definition at line 205 of file am335x_eth_driver.h.

◆ CPSW_SL1_MACCONTROL_R

#define CPSW_SL1_MACCONTROL_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACCONTROL)

Definition at line 206 of file am335x_eth_driver.h.

◆ CPSW_SL1_MACSTATUS_R

#define CPSW_SL1_MACSTATUS_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACSTATUS)

Definition at line 207 of file am335x_eth_driver.h.

◆ CPSW_SL1_RX_MAXLEN_R

#define CPSW_SL1_RX_MAXLEN_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_MAXLEN)

Definition at line 209 of file am335x_eth_driver.h.

◆ CPSW_SL1_RX_PAUSE_R

#define CPSW_SL1_RX_PAUSE_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PAUSE)

Definition at line 211 of file am335x_eth_driver.h.

◆ CPSW_SL1_RX_PRI_MAP_R

#define CPSW_SL1_RX_PRI_MAP_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PRI_MAP)

Definition at line 214 of file am335x_eth_driver.h.

◆ CPSW_SL1_SOFT_RESET_R

#define CPSW_SL1_SOFT_RESET_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_SOFT_RESET)

Definition at line 208 of file am335x_eth_driver.h.

◆ CPSW_SL1_TX_GAP_R

#define CPSW_SL1_TX_GAP_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_GAP)

Definition at line 215 of file am335x_eth_driver.h.

◆ CPSW_SL1_TX_PAUSE_R

#define CPSW_SL1_TX_PAUSE_R   HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_PAUSE)

Definition at line 212 of file am335x_eth_driver.h.

◆ CPSW_SL2_BOFFTEST_R

#define CPSW_SL2_BOFFTEST_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_BOFFTEST)

Definition at line 222 of file am335x_eth_driver.h.

◆ CPSW_SL2_EMCONTROL_R

#define CPSW_SL2_EMCONTROL_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_EMCONTROL)

Definition at line 225 of file am335x_eth_driver.h.

◆ CPSW_SL2_IDVER_R

#define CPSW_SL2_IDVER_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_IDVER)

Definition at line 217 of file am335x_eth_driver.h.

◆ CPSW_SL2_MACCONTROL_R

#define CPSW_SL2_MACCONTROL_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACCONTROL)

Definition at line 218 of file am335x_eth_driver.h.

◆ CPSW_SL2_MACSTATUS_R

#define CPSW_SL2_MACSTATUS_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACSTATUS)

Definition at line 219 of file am335x_eth_driver.h.

◆ CPSW_SL2_RX_MAXLEN_R

#define CPSW_SL2_RX_MAXLEN_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_MAXLEN)

Definition at line 221 of file am335x_eth_driver.h.

◆ CPSW_SL2_RX_PAUSE_R

#define CPSW_SL2_RX_PAUSE_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PAUSE)

Definition at line 223 of file am335x_eth_driver.h.

◆ CPSW_SL2_RX_PRI_MAP_R

#define CPSW_SL2_RX_PRI_MAP_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PRI_MAP)

Definition at line 226 of file am335x_eth_driver.h.

◆ CPSW_SL2_SOFT_RESET_R

#define CPSW_SL2_SOFT_RESET_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_SOFT_RESET)

Definition at line 220 of file am335x_eth_driver.h.

◆ CPSW_SL2_TX_GAP_R

#define CPSW_SL2_TX_GAP_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_GAP)

Definition at line 227 of file am335x_eth_driver.h.

◆ CPSW_SL2_TX_PAUSE_R

#define CPSW_SL2_TX_PAUSE_R   HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_PAUSE)

Definition at line 224 of file am335x_eth_driver.h.

◆ CPSW_SS_CONTROL_R

#define CPSW_SS_CONTROL_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_CONTROL)

Definition at line 231 of file am335x_eth_driver.h.

◆ CPSW_SS_DLR_LTYPE_R

#define CPSW_SS_DLR_LTYPE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_DLR_LTYPE)

Definition at line 242 of file am335x_eth_driver.h.

◆ CPSW_SS_FLOW_CONTROL_R

#define CPSW_SS_FLOW_CONTROL_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_FLOW_CONTROL)

Definition at line 239 of file am335x_eth_driver.h.

◆ CPSW_SS_GAP_THRESH_R

#define CPSW_SS_GAP_THRESH_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_GAP_THRESH)

Definition at line 237 of file am335x_eth_driver.h.

◆ CPSW_SS_ID_VER_R

#define CPSW_SS_ID_VER_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_ID_VER)

Definition at line 230 of file am335x_eth_driver.h.

◆ CPSW_SS_PTYPE_R

#define CPSW_SS_PTYPE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_PTYPE)

Definition at line 234 of file am335x_eth_driver.h.

◆ CPSW_SS_SOFT_IDLE_R

#define CPSW_SS_SOFT_IDLE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_IDLE)

Definition at line 235 of file am335x_eth_driver.h.

◆ CPSW_SS_SOFT_RESET_R

#define CPSW_SS_SOFT_RESET_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_RESET)

Definition at line 232 of file am335x_eth_driver.h.

◆ CPSW_SS_STAT_PORT_EN_R

#define CPSW_SS_STAT_PORT_EN_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_STAT_PORT_EN)

Definition at line 233 of file am335x_eth_driver.h.

◆ CPSW_SS_THRU_RATE_R

#define CPSW_SS_THRU_RATE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_THRU_RATE)

Definition at line 236 of file am335x_eth_driver.h.

◆ CPSW_SS_TS_LTYPE_R

#define CPSW_SS_TS_LTYPE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TS_LTYPE)

Definition at line 241 of file am335x_eth_driver.h.

◆ CPSW_SS_TX_START_WDS_R

#define CPSW_SS_TX_START_WDS_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TX_START_WDS)

Definition at line 238 of file am335x_eth_driver.h.

◆ CPSW_SS_VLAN_LTYPE_R

#define CPSW_SS_VLAN_LTYPE_R   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_VLAN_LTYPE)

Definition at line 240 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD0_NEXT_DESC_POINTER

#define CPSW_TX_WORD0_NEXT_DESC_POINTER   0xFFFFFFFF

Definition at line 298 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD1_BUFFER_POINTER

#define CPSW_TX_WORD1_BUFFER_POINTER   0xFFFFFFFF

Definition at line 299 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD2_BUFFER_LENGTH

#define CPSW_TX_WORD2_BUFFER_LENGTH   0x0000FFFF

Definition at line 301 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD2_BUFFER_OFFSET

#define CPSW_TX_WORD2_BUFFER_OFFSET   0xFFFF0000

Definition at line 300 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_EOP

#define CPSW_TX_WORD3_EOP   0x40000000

Definition at line 303 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_EOQ

#define CPSW_TX_WORD3_EOQ   0x10000000

Definition at line 305 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_OWNER

#define CPSW_TX_WORD3_OWNER   0x20000000

Definition at line 304 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_PACKET_LENGTH

#define CPSW_TX_WORD3_PACKET_LENGTH   0x000007FF

Definition at line 312 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_PASS_CRC

#define CPSW_TX_WORD3_PASS_CRC   0x04000000

Definition at line 307 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_SOP

#define CPSW_TX_WORD3_SOP   0x80000000

Definition at line 302 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_TDOWN_CMPLT

#define CPSW_TX_WORD3_TDOWN_CMPLT   0x08000000

Definition at line 306 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_TO_PORT

#define CPSW_TX_WORD3_TO_PORT   0x00030000

Definition at line 309 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_TO_PORT_1

#define CPSW_TX_WORD3_TO_PORT_1   0x00010000

Definition at line 310 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_TO_PORT_2

#define CPSW_TX_WORD3_TO_PORT_2   0x00020000

Definition at line 311 of file am335x_eth_driver.h.

◆ CPSW_TX_WORD3_TO_PORT_EN

#define CPSW_TX_WORD3_TO_PORT_EN   0x00100000

Definition at line 308 of file am335x_eth_driver.h.

◆ CPSW_WR_C_MISC_EN_R

#define CPSW_WR_C_MISC_EN_R (   n)    HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_EN(n))

Definition at line 252 of file am335x_eth_driver.h.

◆ CPSW_WR_C_MISC_STAT_R

#define CPSW_WR_C_MISC_STAT_R (   n)    HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_STAT(n))

Definition at line 256 of file am335x_eth_driver.h.

◆ CPSW_WR_C_RX_EN_R

#define CPSW_WR_C_RX_EN_R (   n)    HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_EN(n))

Definition at line 250 of file am335x_eth_driver.h.

◆ CPSW_WR_C_RX_IMAX_R

#define CPSW_WR_C_RX_IMAX_R (   n)    HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_IMAX(n))

Definition at line 257 of file am335x_eth_driver.h.

◆ CPSW_WR_C_RX_STAT_R

#define CPSW_WR_C_RX_STAT_R (   n)    HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_STAT(n))

Definition at line 254 of file am335x_eth_driver.h.

◆ CPSW_WR_C_RX_THRESH_EN_R

#define CPSW_WR_C_RX_THRESH_EN_R (   n)    HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_THRESH_EN(n))

Definition at line 249 of file am335x_eth_driver.h.

◆ CPSW_WR_C_RX_THRESH_STAT_R

#define CPSW_WR_C_RX_THRESH_STAT_R (   n)    HWREG(SOC_CPSW_WR_REGS +CPSW_WR_C_RX_THRESH_STAT(n))

Definition at line 253 of file am335x_eth_driver.h.

◆ CPSW_WR_C_TX_EN_R

#define CPSW_WR_C_TX_EN_R (   n)    HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_EN(n))

Definition at line 251 of file am335x_eth_driver.h.

◆ CPSW_WR_C_TX_IMAX_R

#define CPSW_WR_C_TX_IMAX_R (   n)    HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_IMAX(n))

Definition at line 258 of file am335x_eth_driver.h.

◆ CPSW_WR_C_TX_STAT_R

#define CPSW_WR_C_TX_STAT_R (   n)    HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_STAT(n))

Definition at line 255 of file am335x_eth_driver.h.

◆ CPSW_WR_CONTROL_R

#define CPSW_WR_CONTROL_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_CONTROL)

Definition at line 247 of file am335x_eth_driver.h.

◆ CPSW_WR_IDVER_R

#define CPSW_WR_IDVER_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_IDVER)

Definition at line 245 of file am335x_eth_driver.h.

◆ CPSW_WR_INT_CONTROL_R

#define CPSW_WR_INT_CONTROL_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_INT_CONTROL)

Definition at line 248 of file am335x_eth_driver.h.

◆ CPSW_WR_RGMII_CTL_R

#define CPSW_WR_RGMII_CTL_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_RGMII_CTL)

Definition at line 259 of file am335x_eth_driver.h.

◆ CPSW_WR_SOFT_RESET_R

#define CPSW_WR_SOFT_RESET_R   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_SOFT_RESET)

Definition at line 246 of file am335x_eth_driver.h.

◆ MDIO_ALIVE_R

#define MDIO_ALIVE_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_ALIVE)

Definition at line 264 of file am335x_eth_driver.h.

◆ MDIO_CONTROL_R

#define MDIO_CONTROL_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_CONTROL)

Definition at line 263 of file am335x_eth_driver.h.

◆ MDIO_LINK_R

#define MDIO_LINK_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINK)

Definition at line 265 of file am335x_eth_driver.h.

◆ MDIO_LINKINTMASKED_R

#define MDIO_LINKINTMASKED_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTMASKED)

Definition at line 267 of file am335x_eth_driver.h.

◆ MDIO_LINKINTRAW_R

#define MDIO_LINKINTRAW_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTRAW)

Definition at line 266 of file am335x_eth_driver.h.

◆ MDIO_REVID_R

#define MDIO_REVID_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_REVID)

Definition at line 262 of file am335x_eth_driver.h.

◆ MDIO_USERACCESS0_R

#define MDIO_USERACCESS0_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERACCESS0)

Definition at line 272 of file am335x_eth_driver.h.

◆ MDIO_USERACCESS1_R

#define MDIO_USERACCESS1_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERACCESS1)

Definition at line 274 of file am335x_eth_driver.h.

◆ MDIO_USERINTMASKCLEAR_R

#define MDIO_USERINTMASKCLEAR_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKCLEAR)

Definition at line 271 of file am335x_eth_driver.h.

◆ MDIO_USERINTMASKED_R

#define MDIO_USERINTMASKED_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKED)

Definition at line 269 of file am335x_eth_driver.h.

◆ MDIO_USERINTMASKSET_R

#define MDIO_USERINTMASKSET_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKSET)

Definition at line 270 of file am335x_eth_driver.h.

◆ MDIO_USERINTRAW_R

#define MDIO_USERINTRAW_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTRAW)

Definition at line 268 of file am335x_eth_driver.h.

◆ MDIO_USERPHYSEL0_R

#define MDIO_USERPHYSEL0_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERPHYSEL0)

Definition at line 273 of file am335x_eth_driver.h.

◆ MDIO_USERPHYSEL1_R

#define MDIO_USERPHYSEL1_R   HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERPHYSEL1)

Definition at line 275 of file am335x_eth_driver.h.

Typedef Documentation

◆ Am335xRxBufferDesc

RX buffer descriptor.

◆ Am335xTxBufferDesc

TX buffer descriptor.

Function Documentation

◆ am335xEthAddVlanAddrEntry()

error_t am335xEthAddVlanAddrEntry ( uint_t  port,
uint_t  vlanId,
MacAddr macAddr 
)

Add a VLAN/address entry in the ALE table.

Parameters
[in]portPort number
[in]vlanIdVLAN identifier
[in]macAddrMAC address
Returns
Error code

Definition at line 1693 of file am335x_eth_driver.c.

◆ am335xEthAddVlanEntry()

error_t am335xEthAddVlanEntry ( uint_t  port,
uint_t  vlanId 
)

Add a VLAN entry in the ALE table.

Parameters
[in]portPort number
[in]vlanIdVLAN identifier
Returns
Error code

Definition at line 1633 of file am335x_eth_driver.c.

◆ am335xEthDeleteVlanAddrEntry()

error_t am335xEthDeleteVlanAddrEntry ( uint_t  port,
uint_t  vlanId,
MacAddr macAddr 
)

Remove a VLAN/address entry from the ALE table.

Parameters
[in]portPort number
[in]vlanIdVLAN identifier
[in]macAddrMAC address
Returns
Error code

Definition at line 1764 of file am335x_eth_driver.c.

◆ am335xEthDisableIrq()

void am335xEthDisableIrq ( NetInterface interface)

Disable interrupts.

Parameters
[in]interfaceUnderlying network interface

Definition at line 857 of file am335x_eth_driver.c.

◆ am335xEthEnableIrq()

void am335xEthEnableIrq ( NetInterface interface)

Enable interrupts.

Parameters
[in]interfaceUnderlying network interface

Definition at line 835 of file am335x_eth_driver.c.

◆ am335xEthEventHandler()

void am335xEthEventHandler ( NetInterface interface)

AM335x Ethernet MAC event handler.

Parameters
[in]interfaceUnderlying network interface

Definition at line 1017 of file am335x_eth_driver.c.

◆ am335xEthFindFreeEntry()

uint_t am335xEthFindFreeEntry ( void  )

Find a free entry in the ALE table.

Returns
Index of the first free entry

Definition at line 1506 of file am335x_eth_driver.c.

◆ am335xEthFindVlanAddrEntry()

uint_t am335xEthFindVlanAddrEntry ( uint_t  vlanId,
MacAddr macAddr 
)

Search the ALE table for the specified VLAN/address entry.

Parameters
[in]vlanIdVLAN identifier
[in]macAddrMAC address
Returns
Index of the matching entry

Definition at line 1582 of file am335x_eth_driver.c.

◆ am335xEthFindVlanEntry()

uint_t am335xEthFindVlanEntry ( uint_t  vlanId)

Search the ALE table for the specified VLAN entry.

Parameters
[in]vlanIdVLAN identifier
Returns
Index of the matching entry

Definition at line 1540 of file am335x_eth_driver.c.

◆ am335xEthInitBufferDesc()

void am335xEthInitBufferDesc ( NetInterface interface)

Initialize buffer descriptor lists.

Parameters
[in]interfaceUnderlying network interface

Definition at line 705 of file am335x_eth_driver.c.

◆ am335xEthInitGpio()

void am335xEthInitGpio ( NetInterface interface)

◆ am335xEthInitInstance()

void am335xEthInitInstance ( NetInterface interface)

Initialize CPSW instance.

Parameters
[in]interfaceUnderlying network interface

Definition at line 320 of file am335x_eth_driver.c.

◆ am335xEthInitPort1()

error_t am335xEthInitPort1 ( NetInterface interface)

AM335x Ethernet MAC initialization (port 1)

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 175 of file am335x_eth_driver.c.

◆ am335xEthInitPort2()

error_t am335xEthInitPort2 ( NetInterface interface)

AM335x Ethernet MAC initialization (port 2)

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 248 of file am335x_eth_driver.c.

◆ am335xEthReadEntry()

void am335xEthReadEntry ( uint_t  index,
Am335xAleEntry entry 
)

Read an ALE table entry.

Parameters
[in]indexEntry index
[out]entryPointer to the ALE table entry

Definition at line 1489 of file am335x_eth_driver.c.

◆ am335xEthReadPhyReg()

uint16_t am335xEthReadPhyReg ( uint8_t  phyAddr,
uint8_t  regAddr 
)

Read PHY register.

Parameters
[in]phyAddrPHY address
[in]regAddrRegister address
Returns
Register value

Definition at line 1444 of file am335x_eth_driver.c.

◆ am335xEthRxIrqHandler()

void am335xEthRxIrqHandler ( void  )

Ethernet MAC receive interrupt.

Definition at line 974 of file am335x_eth_driver.c.

◆ am335xEthSendPacketPort1()

error_t am335xEthSendPacketPort1 ( NetInterface interface,
const NetBuffer buffer,
size_t  offset 
)

Send a packet (port 1)

Parameters
[in]interfaceUnderlying network interface
[in]bufferMulti-part buffer containing the data to send
[in]offsetOffset to the first data byte
Returns
Error code

Definition at line 1144 of file am335x_eth_driver.c.

◆ am335xEthSendPacketPort2()

error_t am335xEthSendPacketPort2 ( NetInterface interface,
const NetBuffer buffer,
size_t  offset 
)

Send a packet (port 2)

Parameters
[in]interfaceUnderlying network interface
[in]bufferMulti-part buffer containing the data to send
[in]offsetOffset to the first data byte
Returns
Error code

Definition at line 1229 of file am335x_eth_driver.c.

◆ am335xEthTick()

void am335xEthTick ( NetInterface interface)

AM335x Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters
[in]interfaceUnderlying network interface

Definition at line 811 of file am335x_eth_driver.c.

◆ am335xEthTxIrqHandler()

void am335xEthTxIrqHandler ( void  )

Ethernet MAC transmit interrupt.

Definition at line 878 of file am335x_eth_driver.c.

◆ am335xEthUpdateMacAddrFilter()

error_t am335xEthUpdateMacAddrFilter ( NetInterface interface)

Configure MAC address filtering.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 1312 of file am335x_eth_driver.c.

◆ am335xEthUpdateMacConfig()

error_t am335xEthUpdateMacConfig ( NetInterface interface)

Adjust MAC configuration parameters for proper operation.

Parameters
[in]interfaceUnderlying network interface
Returns
Error code

Definition at line 1364 of file am335x_eth_driver.c.

◆ am335xEthWriteEntry()

void am335xEthWriteEntry ( uint_t  index,
const Am335xAleEntry entry 
)

Write an ALE table entry.

Parameters
[in]indexEntry index
[in]entryPointer to the ALE table entry

Definition at line 1471 of file am335x_eth_driver.c.

◆ am335xEthWritePhyReg()

void am335xEthWritePhyReg ( uint8_t  phyAddr,
uint8_t  regAddr,
uint16_t  data 
)

Write PHY register.

Parameters
[in]phyAddrPHY address
[in]regAddrRegister address
[in]dataRegister value

Definition at line 1417 of file am335x_eth_driver.c.

Variable Documentation

◆ am335xEthPort1Driver

const NicDriver am335xEthPort1Driver

AM335x Ethernet MAC driver (port1)

Definition at line 123 of file am335x_eth_driver.c.

◆ am335xEthPort2Driver

const NicDriver am335xEthPort2Driver

AM335x Ethernet MAC driver (port2)

Definition at line 148 of file am335x_eth_driver.c.