am335x_eth_driver.h
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1 /**
2  * @file am335x_eth_driver.h
3  * @brief Sitara AM335x Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _AM335X_ETH_DRIVER_H
30 #define _AM335X_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef AM335X_ETH_TX_BUFFER_COUNT
37  #define AM335X_ETH_TX_BUFFER_COUNT 16
38 #elif (AM335X_ETH_TX_BUFFER_COUNT < 1)
39  #error AM335X_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef AM335X_ETH_TX_BUFFER_SIZE
44  #define AM335X_ETH_TX_BUFFER_SIZE 1536
45 #elif (AM335X_ETH_TX_BUFFER_SIZE != 1536)
46  #error AM335X_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef AM335X_ETH_RX_BUFFER_COUNT
51  #define AM335X_ETH_RX_BUFFER_COUNT 16
52 #elif (AM335X_ETH_RX_BUFFER_COUNT < 1)
53  #error AM335X_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef AM335X_ETH_RX_BUFFER_SIZE
58  #define AM335X_ETH_RX_BUFFER_SIZE 1536
59 #elif (AM335X_ETH_RX_BUFFER_SIZE != 1536)
60  #error AM335X_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Ethernet interrupt priority
64 #ifndef AM335X_ETH_IRQ_PRIORITY
65  #define AM335X_ETH_IRQ_PRIORITY 1
66 #elif (AM335X_ETH_IRQ_PRIORITY < 0)
67  #error AM335X_ETH_IRQ_PRIORITY parameter is not valid
68 #endif
69 
70 //CPSW cores
71 #define CPSW_CORE0 0
72 #define CPSW_CORE1 1
73 #define CPSW_CORE2 2
74 
75 //CPSW ports
76 #define CPSW_PORT0 0
77 #define CPSW_PORT1 1
78 #define CPSW_PORT2 2
79 
80 //CPSW channels
81 #define CPSW_CH0 0
82 #define CPSW_CH1 1
83 #define CPSW_CH2 2
84 #define CPSW_CH3 3
85 #define CPSW_CH4 4
86 #define CPSW_CH5 5
87 #define CPSW_CH6 6
88 #define CPSW_CH7 7
89 
90 //PRCM registers
91 #define CM_PER_CPGMAC0_CLKCTRL_R HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL)
92 #define CM_PER_CPSW_CLKSTCTRL_R HWREG(SOC_PRCM_REGS + CM_PER_CPSW_CLKSTCTRL)
93 
94 //CONTROL registers
95 #define CONTROL_MAC_ID_LO_R(n) HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(n))
96 #define CONTROL_MAC_ID_HI_R(n) HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(n))
97 #define CONTROL_GMII_SEL_R HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL)
98 #define CONTROL_CONF_GPMC_A_R(n) HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(n))
99 #define CONTROL_CONF_MII1_COL_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL)
100 #define CONTROL_CONF_MII1_CRS_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS)
101 #define CONTROL_CONF_MII1_RXERR_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR)
102 #define CONTROL_CONF_MII1_TXEN_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN)
103 #define CONTROL_CONF_MII1_RXDV_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV)
104 #define CONTROL_CONF_MII1_TXD3_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3)
105 #define CONTROL_CONF_MII1_TXD2_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2)
106 #define CONTROL_CONF_MII1_TXD1_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1)
107 #define CONTROL_CONF_MII1_TXD0_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0)
108 #define CONTROL_CONF_MII1_TXCLK_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK)
109 #define CONTROL_CONF_MII1_RXCLK_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK)
110 #define CONTROL_CONF_MII1_RXD3_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3)
111 #define CONTROL_CONF_MII1_RXD2_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2)
112 #define CONTROL_CONF_MII1_RXD1_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1)
113 #define CONTROL_CONF_MII1_RXD0_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0)
114 #define CONTROL_CONF_RMII1_REFCLK_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK)
115 #define CONTROL_CONF_MDIO_DATA_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA)
116 #define CONTROL_CONF_MDIO_CLK_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK)
117 
118 //CPSW_ALE registers
119 #define CPSW_ALE_IDVER_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_IDVER)
120 #define CPSW_ALE_CONTROL_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_CONTROL)
121 #define CPSW_ALE_PRESCALE_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PRESCALE)
122 #define CPSW_ALE_UNKNOWN_VLAN_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_UNKNOWN_VLAN)
123 #define CPSW_ALE_TBLCTL_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLCTL)
124 #define CPSW_ALE_TBLW_R(n) HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLW(n))
125 #define CPSW_ALE_PORTCTL_R(n) HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PORTCTL(n))
126 
127 //CPSW_CPDMA registers
128 #define CPSW_CPDMA_TX_IDVER_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_IDVER)
129 #define CPSW_CPDMA_TX_CONTROL_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_CONTROL)
130 #define CPSW_CPDMA_TX_TEARDOWN_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_TEARDOWN)
131 #define CPSW_CPDMA_RX_IDVER_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_IDVER)
132 #define CPSW_CPDMA_RX_CONTROL_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_CONTROL)
133 #define CPSW_CPDMA_RX_TEARDOWN_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_TEARDOWN)
134 #define CPSW_CPDMA_CPDMA_SOFT_RESET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_SOFT_RESET)
135 #define CPSW_CPDMA_DMACONTROL_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMACONTROL)
136 #define CPSW_CPDMA_DMASTATUS_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMASTATUS)
137 #define CPSW_CPDMA_RX_BUFFER_OFFSET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_BUFFER_OFFSET)
138 #define CPSW_CPDMA_EMCONTROL_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_EMCONTROL)
139 #define CPSW_CPDMA_TX_PRI_RATE_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_PRI_RATE(n))
140 #define CPSW_CPDMA_TX_INTSTAT_RAW_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_RAW)
141 #define CPSW_CPDMA_TX_INTSTAT_MASKED_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_MASKED)
142 #define CPSW_CPDMA_TX_INTMASK_SET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_SET)
143 #define CPSW_CPDMA_TX_INTMASK_CLEAR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_CLEAR)
144 #define CPSW_CPDMA_CPDMA_IN_VECTOR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_IN_VECTOR)
145 #define CPSW_CPDMA_CPDMA_EOI_VECTOR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_EOI_VECTOR)
146 #define CPSW_CPDMA_RX_INTSTAT_RAW_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_RAW)
147 #define CPSW_CPDMA_RX_INTSTAT_MASKED_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_MASKED)
148 #define CPSW_CPDMA_RX_INTMASK_SET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_SET)
149 #define CPSW_CPDMA_RX_INTMASK_CLEAR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_CLEAR)
150 #define CPSW_CPDMA_DMA_INTSTAT_RAW_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_RAW)
151 #define CPSW_CPDMA_DMA_INTSTAT_MASKED_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_MASKED)
152 #define CPSW_CPDMA_DMA_INTMASK_SET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_SET)
153 #define CPSW_CPDMA_DMA_INTMASK_CLEAR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_CLEAR)
154 #define CPSW_CPDMA_RX_PENDTHRESH_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_PENDTHRESH(n))
155 #define CPSW_CPDMA_RX_FREEBUFFER_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_FREEBUFFER(n))
156 #define CPSW_CPDMA_TX_HDP_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_HDP(n))
157 #define CPSW_CPDMA_RX_HDP_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_HDP(n))
158 #define CPSW_CPDMA_TX_CP_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_CP(n))
159 #define CPSW_CPDMA_RX_CP_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_CP(n))
160 
161 //CPSW_PORT registers
162 #define CPSW_PORT0_CONTROL_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CONTROL)
163 #define CPSW_PORT0_MAX_BLKS_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_MAX_BLKS)
164 #define CPSW_PORT0_BLK_CNT_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_BLK_CNT)
165 #define CPSW_PORT0_TX_IN_CTL_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TX_IN_CTL)
166 #define CPSW_PORT0_PORT_VLAN_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_PORT_VLAN)
167 #define CPSW_PORT0_TX_PRI_MAP_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TX_PRI_MAP)
168 #define CPSW_PORT0_CPDMA_TX_PRI_MAP0_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)
169 #define CPSW_PORT0_CPDMA_RX_CH_MAP0_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)
170 #define CPSW_PORT0_RX_DSCP_PRI_MAP_R(n) HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))
171 #define CPSW_PORT0_TS_SEQ_MTYPE_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TS_SEQ_MTYPE)
172 #define CPSW_PORT0_SA_LO_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SA_LO)
173 #define CPSW_PORT0_SA_HI_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SA_HI)
174 #define CPSW_PORT0_SEND_PERCENT_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SEND_PERCENT)
175 
176 #define CPSW_PORT1_CONTROL_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CONTROL)
177 #define CPSW_PORT1_MAX_BLKS_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_MAX_BLKS)
178 #define CPSW_PORT1_BLK_CNT_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_BLK_CNT)
179 #define CPSW_PORT1_TX_IN_CTL_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TX_IN_CTL)
180 #define CPSW_PORT1_PORT_VLAN_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_PORT_VLAN)
181 #define CPSW_PORT1_TX_PRI_MAP_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TX_PRI_MAP)
182 #define CPSW_PORT1_CPDMA_TX_PRI_MAP0_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)
183 #define CPSW_PORT1_CPDMA_RX_CH_MAP0_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)
184 #define CPSW_PORT1_RX_DSCP_PRI_MAP_R(n) HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))
185 #define CPSW_PORT1_TS_SEQ_MTYPE_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TS_SEQ_MTYPE)
186 #define CPSW_PORT1_SA_LO_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SA_LO)
187 #define CPSW_PORT1_SA_HI_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SA_HI)
188 #define CPSW_PORT1_SEND_PERCENT_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SEND_PERCENT)
189 
190 #define CPSW_PORT2_CONTROL_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CONTROL)
191 #define CPSW_PORT2_MAX_BLKS_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_MAX_BLKS)
192 #define CPSW_PORT2_BLK_CNT_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_BLK_CNT)
193 #define CPSW_PORT2_TX_IN_CTL_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TX_IN_CTL)
194 #define CPSW_PORT2_PORT_VLAN_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_PORT_VLAN)
195 #define CPSW_PORT2_TX_PRI_MAP_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TX_PRI_MAP)
196 #define CPSW_PORT2_CPDMA_TX_PRI_MAP0_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)
197 #define CPSW_PORT2_CPDMA_RX_CH_MAP0_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)
198 #define CPSW_PORT2_RX_DSCP_PRI_MAP_R(n) HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))
199 #define CPSW_PORT2_TS_SEQ_MTYPE_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TS_SEQ_MTYPE)
200 #define CPSW_PORT2_SA_LO_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SA_LO)
201 #define CPSW_PORT2_SA_HI_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SA_HI)
202 #define CPSW_PORT2_SEND_PERCENT_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SEND_PERCENT)
203 
204 //CPSW_SL registers
205 #define CPSW_SL1_IDVER_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_IDVER)
206 #define CPSW_SL1_MACCONTROL_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACCONTROL)
207 #define CPSW_SL1_MACSTATUS_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACSTATUS)
208 #define CPSW_SL1_SOFT_RESET_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_SOFT_RESET)
209 #define CPSW_SL1_RX_MAXLEN_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_MAXLEN)
210 #define CPSW_SL1_BOFFTEST_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_BOFFTEST)
211 #define CPSW_SL1_RX_PAUSE_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PAUSE)
212 #define CPSW_SL1_TX_PAUSE_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_PAUSE)
213 #define CPSW_SL1_EMCONTROL_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_EMCONTROL)
214 #define CPSW_SL1_RX_PRI_MAP_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PRI_MAP)
215 #define CPSW_SL1_TX_GAP_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_GAP)
216 
217 #define CPSW_SL2_IDVER_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_IDVER)
218 #define CPSW_SL2_MACCONTROL_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACCONTROL)
219 #define CPSW_SL2_MACSTATUS_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACSTATUS)
220 #define CPSW_SL2_SOFT_RESET_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_SOFT_RESET)
221 #define CPSW_SL2_RX_MAXLEN_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_MAXLEN)
222 #define CPSW_SL2_BOFFTEST_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_BOFFTEST)
223 #define CPSW_SL2_RX_PAUSE_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PAUSE)
224 #define CPSW_SL2_TX_PAUSE_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_PAUSE)
225 #define CPSW_SL2_EMCONTROL_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_EMCONTROL)
226 #define CPSW_SL2_RX_PRI_MAP_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PRI_MAP)
227 #define CPSW_SL2_TX_GAP_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_GAP)
228 
229 //CPSW_SS registers
230 #define CPSW_SS_ID_VER_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_ID_VER)
231 #define CPSW_SS_CONTROL_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_CONTROL)
232 #define CPSW_SS_SOFT_RESET_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_RESET)
233 #define CPSW_SS_STAT_PORT_EN_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_STAT_PORT_EN)
234 #define CPSW_SS_PTYPE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_PTYPE)
235 #define CPSW_SS_SOFT_IDLE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_IDLE)
236 #define CPSW_SS_THRU_RATE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_THRU_RATE)
237 #define CPSW_SS_GAP_THRESH_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_GAP_THRESH)
238 #define CPSW_SS_TX_START_WDS_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TX_START_WDS)
239 #define CPSW_SS_FLOW_CONTROL_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_FLOW_CONTROL)
240 #define CPSW_SS_VLAN_LTYPE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_VLAN_LTYPE)
241 #define CPSW_SS_TS_LTYPE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TS_LTYPE)
242 #define CPSW_SS_DLR_LTYPE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_DLR_LTYPE)
243 
244 //CPSW_WR registers
245 #define CPSW_WR_IDVER_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_IDVER)
246 #define CPSW_WR_SOFT_RESET_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_SOFT_RESET)
247 #define CPSW_WR_CONTROL_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_CONTROL)
248 #define CPSW_WR_INT_CONTROL_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_INT_CONTROL)
249 #define CPSW_WR_C_RX_THRESH_EN_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_THRESH_EN(n))
250 #define CPSW_WR_C_RX_EN_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_EN(n))
251 #define CPSW_WR_C_TX_EN_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_EN(n))
252 #define CPSW_WR_C_MISC_EN_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_EN(n))
253 #define CPSW_WR_C_RX_THRESH_STAT_R(n) HWREG(SOC_CPSW_WR_REGS +CPSW_WR_C_RX_THRESH_STAT(n))
254 #define CPSW_WR_C_RX_STAT_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_STAT(n))
255 #define CPSW_WR_C_TX_STAT_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_STAT(n))
256 #define CPSW_WR_C_MISC_STAT_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_STAT(n))
257 #define CPSW_WR_C_RX_IMAX_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_IMAX(n))
258 #define CPSW_WR_C_TX_IMAX_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_IMAX(n))
259 #define CPSW_WR_RGMII_CTL_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_RGMII_CTL)
260 
261 //MDIO registers
262 #define MDIO_REVID_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_REVID)
263 #define MDIO_CONTROL_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_CONTROL)
264 #define MDIO_ALIVE_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_ALIVE)
265 #define MDIO_LINK_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINK)
266 #define MDIO_LINKINTRAW_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTRAW)
267 #define MDIO_LINKINTMASKED_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTMASKED)
268 #define MDIO_USERINTRAW_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTRAW)
269 #define MDIO_USERINTMASKED_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKED)
270 #define MDIO_USERINTMASKSET_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKSET)
271 #define MDIO_USERINTMASKCLEAR_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKCLEAR)
272 #define MDIO_USERACCESS0_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERACCESS0)
273 #define MDIO_USERPHYSEL0_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERPHYSEL0)
274 #define MDIO_USERACCESS1_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERACCESS1)
275 #define MDIO_USERPHYSEL1_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERPHYSEL1)
276 
277 //GMII_SEL register
278 #define CONTROL_GMII_SEL_GMII2_SEL_MII 0x00000000
279 #define CONTROL_GMII_SEL_GMII2_SEL_RMII 0x00000004
280 #define CONTROL_GMII_SEL_GMII2_SEL_RGMII 0x00000008
281 #define CONTROL_GMII_SEL_GMII1_SEL_MII 0x00000000
282 #define CONTROL_GMII_SEL_GMII1_SEL_RMII 0x00000001
283 #define CONTROL_GMII_SEL_GMII1_SEL_RGMII 0x00000002
284 
285 //ALE_PORTCTL register
286 #define CPSW_ALE_PORTCTL_PORT_STATE_DISABLED 0x00000000
287 #define CPSW_ALE_PORTCTL_PORT_STATE_BLOCKED 0x00000001
288 #define CPSW_ALE_PORTCTL_PORT_STATE_LEARN 0x00000002
289 #define CPSW_ALE_PORTCTL_PORT_STATE_FORWARD 0x00000003
290 
291 //CPDMA_EOI_VECTOR register
292 #define CPSW_CPDMA_EOI_VECTOR_RX_THRESH_PULSE 0x00000000
293 #define CPSW_CPDMA_EOI_VECTOR_RX_PULSE 0x00000001
294 #define CPSW_CPDMA_EOI_VECTOR_TX_PULSE 0x00000002
295 #define CPSW_CPDMA_EOI_VECTOR_MISC_PULSE 0x00000003
296 
297 //TX buffer descriptor flags
298 #define CPSW_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
299 #define CPSW_TX_WORD1_BUFFER_POINTER 0xFFFFFFFF
300 #define CPSW_TX_WORD2_BUFFER_OFFSET 0xFFFF0000
301 #define CPSW_TX_WORD2_BUFFER_LENGTH 0x0000FFFF
302 #define CPSW_TX_WORD3_SOP 0x80000000
303 #define CPSW_TX_WORD3_EOP 0x40000000
304 #define CPSW_TX_WORD3_OWNER 0x20000000
305 #define CPSW_TX_WORD3_EOQ 0x10000000
306 #define CPSW_TX_WORD3_TDOWN_CMPLT 0x08000000
307 #define CPSW_TX_WORD3_PASS_CRC 0x04000000
308 #define CPSW_TX_WORD3_TO_PORT_EN 0x00100000
309 #define CPSW_TX_WORD3_TO_PORT 0x00030000
310 #define CPSW_TX_WORD3_TO_PORT_1 0x00010000
311 #define CPSW_TX_WORD3_TO_PORT_2 0x00020000
312 #define CPSW_TX_WORD3_PACKET_LENGTH 0x000007FF
313 
314 //RX buffer descriptor flags
315 #define CPSW_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
316 #define CPSW_RX_WORD1_BUFFER_POINTER 0xFFFFFFFF
317 #define CPSW_RX_WORD2_BUFFER_OFFSET 0x07FF0000
318 #define CPSW_RX_WORD2_BUFFER_LENGTH 0x000007FF
319 #define CPSW_RX_WORD3_SOP 0x80000000
320 #define CPSW_RX_WORD3_EOP 0x40000000
321 #define CPSW_RX_WORD3_OWNER 0x20000000
322 #define CPSW_RX_WORD3_EOQ 0x10000000
323 #define CPSW_RX_WORD3_TDOWN_CMPLT 0x08000000
324 #define CPSW_RX_WORD3_PASS_CRC 0x04000000
325 #define CPSW_RX_WORD3_LONG 0x02000000
326 #define CPSW_RX_WORD3_SHORT 0x01000000
327 #define CPSW_RX_WORD3_CONTROL 0x00800000
328 #define CPSW_RX_WORD3_OVERRUN 0x00400000
329 #define CPSW_RX_WORD3_PKT_ERROR 0x00300000
330 #define CPSW_RX_WORD3_RX_VLAN_ENCAP 0x000C0000
331 #define CPSW_RX_WORD3_FROM_PORT 0x00030000
332 #define CPSW_RX_WORD3_FROM_PORT_1 0x00010000
333 #define CPSW_RX_WORD3_FROM_PORT_2 0x00020000
334 #define CPSW_RX_WORD3_PACKET_LENGTH 0x000007FF
335 
336 //Number of entries in the ALE table
337 #define CPSW_ALE_MAX_ENTRIES 1024
338 
339 //ALE table entry
340 #define CPSW_ALE_WORD1_ENTRY_TYPE_MASK (3 << 28)
341 #define CPSW_ALE_WORD1_ENTRY_TYPE_FREE (0 << 28)
342 #define CPSW_ALE_WORD1_ENTRY_TYPE_ADDR (1 << 28)
343 #define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN (2 << 28)
344 #define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN_ADDR (3 << 28)
345 #define CPSW_ALE_WORD1_MULTICAST (1 << 8)
346 
347 //Unicast address table entry
348 #define CPSW_ALE_WORD2_DLR_UNICAST (1 << 5)
349 #define CPSW_ALE_WORD2_PORT_NUMBER_MASK (3 << 2)
350 #define CPSW_ALE_WORD2_PORT_NUMBER(n) ((n) << 2)
351 #define CPSW_ALE_WORD2_BLOCK (1 << 1)
352 #define CPSW_ALE_WORD2_SECURE (1 << 0)
353 #define CPSW_ALE_WORD1_UNICAST_TYPE_MASK (3 << 30)
354 #define CPSW_ALE_WORD1_UNICAST_TYPE(n) ((n) << 30)
355 
356 //Multicast address table entry
357 #define CPSW_ALE_WORD2_PORT_LIST_MASK (3 << 2)
358 #define CPSW_ALE_WORD2_PORT_LIST(n) ((n) << 2)
359 #define CPSW_ALE_WORD2_SUPER (1 << 1)
360 #define CPSW_ALE_WORD1_MCAST_FWD_STATE_MASK (3 << 30)
361 #define CPSW_ALE_WORD1_MCAST_FWD_STATE(n) ((n) << 30)
362 
363 //VLAN table entry
364 #define CPSW_ALE_WORD1_VLAN_ID_MASK (4095 << 16)
365 #define CPSW_ALE_WORD1_VLAN_ID(n) ((n) << 16)
366 #define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS_MASK (7 << 24)
367 #define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS(n) ((n) << 24)
368 #define CPSW_ALE_WORD0_REG_MCAST_FLOOD_MASK (7 << 16)
369 #define CPSW_ALE_WORD0_REG_MCAST_FLOOD(n) ((n) << 16)
370 #define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD_MASK (7 << 8)
371 #define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD(n) ((n) << 8)
372 #define CPSW_ALE_WORD0_VLAN_MEMBER_LIST_MASK (7 << 0)
373 #define CPSW_ALE_WORD0_VLAN_MEMBER_LIST(n) ((n) << 0)
374 
375 //C++ guard
376 #ifdef __cplusplus
377  extern "C" {
378 #endif
379 
380 
381 /**
382  * @brief ALE table entry
383  **/
384 
385 typedef struct
386 {
387  uint32_t word2;
388  uint32_t word1;
389  uint32_t word0;
391 
392 
393 /**
394  * @brief TX buffer descriptor
395  **/
396 
397 typedef struct _Am335xTxBufferDesc
398 {
399  uint32_t word0;
400  uint32_t word1;
401  uint32_t word2;
402  uint32_t word3;
406 
407 
408 /**
409  * @brief RX buffer descriptor
410  **/
411 
412 typedef struct _Am335xRxBufferDesc
413 {
414  uint32_t word0;
415  uint32_t word1;
416  uint32_t word2;
417  uint32_t word3;
421 
422 
423 //AM335x Ethernet MAC driver
424 extern const NicDriver am335xEthPort1Driver;
425 extern const NicDriver am335xEthPort2Driver;
426 
427 //AM335x Ethernet MAC related functions
430 void am335xEthInitInstance(NetInterface *interface);
431 void am335xEthInitGpio(NetInterface *interface);
432 void am335xEthInitBufferDesc(NetInterface *interface);
433 
434 void am335xEthTick(NetInterface *interface);
435 
436 void am335xEthEnableIrq(NetInterface *interface);
437 void am335xEthDisableIrq(NetInterface *interface);
438 void am335xEthTxIrqHandler(void);
439 void am335xEthRxIrqHandler(void);
440 void am335xEthEventHandler(NetInterface *interface);
441 
443  const NetBuffer *buffer, size_t offset);
444 
446  const NetBuffer *buffer, size_t offset);
447 
450 
451 void am335xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
452 uint16_t am335xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
453 
454 void am335xEthWriteEntry(uint_t index, const Am335xAleEntry *entry);
455 void am335xEthReadEntry(uint_t index, Am335xAleEntry *entry);
456 
460 
464 
465 //C++ guard
466 #ifdef __cplusplus
467  }
468 #endif
469 
470 #endif
const NicDriver am335xEthPort2Driver
AM335x Ethernet MAC driver (port2)
void am335xEthInitGpio(NetInterface *interface)
uint32_t word1
uint_t am335xEthFindVlanAddrEntry(uint_t vlanId, MacAddr *macAddr)
Search the ALE table for the specified VLAN/address entry.
error_t am335xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
struct _Am335xRxBufferDesc * prev
void am335xEthTick(NetInterface *interface)
AM335x Ethernet MAC timer handler.
struct _Am335xTxBufferDesc Am335xTxBufferDesc
TX buffer descriptor.
error_t am335xEthDeleteVlanAddrEntry(uint_t port, uint_t vlanId, MacAddr *macAddr)
Remove a VLAN/address entry from the ALE table.
void am335xEthEventHandler(NetInterface *interface)
AM335x Ethernet MAC event handler.
error_t am335xEthSendPacketPort1(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet (port 1)
const NicDriver am335xEthPort1Driver
AM335x Ethernet MAC driver (port1)
uint_t am335xEthFindFreeEntry(void)
Find a free entry in the ALE table.
TX buffer descriptor.
uint32_t word2
struct _Am335xTxBufferDesc * prev
void am335xEthReadEntry(uint_t index, Am335xAleEntry *entry)
Read an ALE table entry.
RX buffer descriptor.
error_t am335xEthAddVlanAddrEntry(uint_t port, uint_t vlanId, MacAddr *macAddr)
Add a VLAN/address entry in the ALE table.
void am335xEthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t am335xEthAddVlanEntry(uint_t port, uint_t vlanId)
Add a VLAN entry in the ALE table.
void am335xEthInitInstance(NetInterface *interface)
Initialize CPSW instance.
error_t am335xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
ALE table entry.
struct _Am335xRxBufferDesc * next
struct _Am335xTxBufferDesc * next
uint16_t am335xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
struct _Am335xRxBufferDesc Am335xRxBufferDesc
RX buffer descriptor.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void am335xEthRxIrqHandler(void)
Ethernet MAC receive interrupt.
uint16_t regAddr
error_t
Error codes.
Definition: error.h:40
error_t am335xEthSendPacketPort2(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet (port 2)
uint32_t word0
unsigned int uint_t
Definition: compiler_port.h:43
void am335xEthEnableIrq(NetInterface *interface)
Enable interrupts.
void am335xEthTxIrqHandler(void)
Ethernet MAC transmit interrupt.
__start_packed struct @112 MacAddr
MAC address.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void am335xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void am335xEthWriteEntry(uint_t index, const Am335xAleEntry *entry)
Write an ALE table entry.
uint16_t port
Definition: dns_common.h:221
error_t am335xEthInitPort2(NetInterface *interface)
AM335x Ethernet MAC initialization (port 2)
void am335xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptor lists.
error_t am335xEthInitPort1(NetInterface *interface)
AM335x Ethernet MAC initialization (port 1)
uint_t am335xEthFindVlanEntry(uint_t vlanId)
Search the ALE table for the specified VLAN entry.
Network interface controller abstraction layer.