aps3_eth_driver.c
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1 /**
2  * @file aps3_eth_driver.c
3  * @brief Cortus APS3 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.0.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <machine/sfradr.h>
36 #include <machine/sfradr_eth.h>
37 #include <machine/ethernet.h>
38 #include <machine/ic.h>
39 #undef _ETHERNET_H
40 #include "core/net.h"
42 #include "debug.h"
43 
44 //Transmit buffer
45 #define txBuffer ((uint8_t *) SFRADR_ETH_TX_MEM_BOTTOM_AD)
46 //Receive buffer
47 #define rxBuffer ((uint8_t *) SFRADR_ETH_RX_MEM_BOTTOM_AD)
48 
49 //Transmit DMA descriptors
50 #define txDmaDesc ((Aps3TxDmaDesc *) (SFRADR_ETH_TX_MEM_BOTTOM_AD + \
51  APS3_ETH_TX_BUFFER_COUNT * APS3_ETH_TX_BUFFER_SIZE))
52 
53 //Receive DMA descriptors
54 #define rxDmaDesc ((Aps3RxDmaDesc *) (SFRADR_ETH_RX_MEM_BOTTOM_AD + \
55  APS3_ETH_RX_BUFFER_COUNT * APS3_ETH_RX_BUFFER_SIZE))
56 
57 //Underlying network interface
58 static NetInterface *nicDriverInterface;
59 
60 
61 /**
62  * @brief Cortus APS3 Ethernet MAC driver
63  **/
64 
66 {
68  ETH_MTU,
79  TRUE,
80  TRUE,
81  TRUE,
82  FALSE
83 };
84 
85 
86 /**
87  * @brief Cortus APS3 Ethernet MAC initialization
88  * @param[in] interface Underlying network interface
89  * @return Error code
90  **/
91 
93 {
94  error_t error;
95 
96  //Debug message
97  TRACE_INFO("Initializing Cortus APS3 Ethernet MAC...\r\n");
98 
99  //Save underlying network interface
100  nicDriverInterface = interface;
101 
102  //Adjust MDC clock range
103  eth_miim->miim_clock_divider = 32;
104 
105  //Valid Ethernet PHY or switch driver?
106  if(interface->phyDriver != NULL)
107  {
108  //Ethernet PHY initialization
109  error = interface->phyDriver->init(interface);
110  }
111  else if(interface->switchDriver != NULL)
112  {
113  //Ethernet switch initialization
114  error = interface->switchDriver->init(interface);
115  }
116  else
117  {
118  //The interface is not properly configured
119  error = ERROR_FAILURE;
120  }
121 
122  //Any error to report?
123  if(error)
124  {
125  return error;
126  }
127 
128  //Reset Ethernet MAC peripheral
129  eth_mac->sw_reset = 1;
130 
131  //Set the MAC address of the station
132  eth_mac->addr_low = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
133  eth_mac->addr_high = interface->macAddr.w[2];
134 
135  //Initialize hash table
136  eth_mac->hash_filter_low = 0;
137  eth_mac->hash_filter_high = 0;
138 
139  //Configure the receive filter
140  eth_mac->unicast = 1;
141  eth_mac->multicast = 0;
142  eth_mac->broadcast = 1;
143  eth_mac->hash = 1;
144  eth_mac->exact_addr = 1;
145 
146  //Default duplex mode
147  eth_mac->full_duplex = 0;
148 
149  //Automatic padding and CRC generation
150  eth_mac->no_padding = 0;
151  eth_mac->crc_disable = 0;
152 
153  //Set the maximum frame length
154  eth_mac->max_frame_size = APS3_ETH_RX_BUFFER_SIZE;
155 
156  //Set transmit and receive thresholds
157  eth_tx->tx_threshold = 0;
158  eth_rx->rx_threshold = 0;
159 
160  //Disable indefinite deferral
161  eth_mac->indefinite_deferral = 0;
162  //Number of attempts to transmit a frame before aborting
163  eth_mac->max_deferral = 15;
164 
165  //Use default collision window (112 half-octets)
166  eth_mac->collision_window = 111;
167  //Maximum Number of Collisions
168  eth_mac->max_collision = 15;
169 
170  //Automatic backoff on collision
171  eth_mac->no_backoff = 0;
172 
173  //Use the default interframe gap (24 half-octets or 96 bits)
174  eth_mac->interframe_gap = 23;
175 
176  //Initialize DMA descriptor lists
177  aps3EthInitDmaDesc(interface);
178 
179  //Configure TX interrupts
180  eth_tx->tx_irq_mask = TX_IRQ_MASK_MEMORY_AVAILABLE;
181  //Configure RX interrupts
182  eth_rx->rx_irq_mask = RX_IRQ_MASK_FRAME_READY;
183 
184  //Configure TX interrupt priority
185  irq[IRQ_ETH_TX].ipl = APS3_ETH_IRQ_PRIORITY;
186  //Configure RX interrupt priority
187  irq[IRQ_ETH_RX].ipl = APS3_ETH_IRQ_PRIORITY;
188 
189  //Enable transmission and reception
190  eth_tx->tx_enable = 1;
191  eth_rx->rx_enable = 1;
192 
193  //Accept any packets from the upper layer
194  osSetEvent(&interface->nicTxEvent);
195 
196  //Successful initialization
197  return NO_ERROR;
198 }
199 
200 
201 /**
202  * @brief Initialize DMA descriptor lists
203  * @param[in] interface Underlying network interface
204  **/
205 
207 {
208  uint_t i;
209 
210  //Initialize TX DMA descriptor list
211  for(i = 0; i < APS3_ETH_TX_BUFFER_COUNT; i++)
212  {
213  //Transmit buffer address
214  txDmaDesc[i].addr = (uint32_t) txBuffer + (APS3_ETH_TX_BUFFER_SIZE * i);
215  //Transmit buffer size
216  txDmaDesc[i].size = 0;
217  //Transmit status
218  txDmaDesc[i].status = 0;
219  }
220 
221  //Initialize RX DMA descriptor list
222  for(i = 0; i < APS3_ETH_RX_BUFFER_COUNT; i++)
223  {
224  //Receive buffer address
225  rxDmaDesc[i].addr = (uint32_t) rxBuffer + (APS3_ETH_RX_BUFFER_SIZE * i);
226  //Receive buffer size
227  rxDmaDesc[i].size = 0;
228  //Receive status
229  rxDmaDesc[i].status = 0;
230  }
231 
232  //Start location of the TX descriptor list
233  eth_tx->tx_desc_base_addr = (uint32_t) txDmaDesc;
234  //Number of TX descriptors
235  eth_tx->tx_desc_number = APS3_ETH_TX_BUFFER_COUNT - 1;
236 
237  //Start location of the RX descriptor list
238  eth_rx->rx_desc_base_addr = (uint32_t) rxDmaDesc;
239  //Number of RX descriptors
240  eth_rx->rx_desc_number = APS3_ETH_RX_BUFFER_COUNT - 1;
241 }
242 
243 
244 /**
245  * @brief Cortus APS3 Ethernet MAC timer handler
246  *
247  * This routine is periodically called by the TCP/IP stack to handle periodic
248  * operations such as polling the link state
249  *
250  * @param[in] interface Underlying network interface
251  **/
252 
253 void aps3EthTick(NetInterface *interface)
254 {
255  //Valid Ethernet PHY or switch driver?
256  if(interface->phyDriver != NULL)
257  {
258  //Handle periodic operations
259  interface->phyDriver->tick(interface);
260  }
261  else if(interface->switchDriver != NULL)
262  {
263  //Handle periodic operations
264  interface->switchDriver->tick(interface);
265  }
266  else
267  {
268  //Just for sanity
269  }
270 }
271 
272 
273 /**
274  * @brief Enable interrupts
275  * @param[in] interface Underlying network interface
276  **/
277 
279 {
280  //Enable Ethernet MAC interrupts
281  irq[IRQ_ETH_TX].ien = 1;
282  irq[IRQ_ETH_RX].ien = 1;
283 
284 
285  //Valid Ethernet PHY or switch driver?
286  if(interface->phyDriver != NULL)
287  {
288  //Enable Ethernet PHY interrupts
289  interface->phyDriver->enableIrq(interface);
290  }
291  else if(interface->switchDriver != NULL)
292  {
293  //Enable Ethernet switch interrupts
294  interface->switchDriver->enableIrq(interface);
295  }
296  else
297  {
298  //Just for sanity
299  }
300 }
301 
302 
303 /**
304  * @brief Disable interrupts
305  * @param[in] interface Underlying network interface
306  **/
307 
309 {
310  //Disable Ethernet MAC interrupts
311  irq[IRQ_ETH_TX].ien = 0;
312  irq[IRQ_ETH_RX].ien = 0;
313 
314 
315  //Valid Ethernet PHY or switch driver?
316  if(interface->phyDriver != NULL)
317  {
318  //Disable Ethernet PHY interrupts
319  interface->phyDriver->disableIrq(interface);
320  }
321  else if(interface->switchDriver != NULL)
322  {
323  //Disable Ethernet switch interrupts
324  interface->switchDriver->disableIrq(interface);
325  }
326  else
327  {
328  //Just for sanity
329  }
330 }
331 
332 
333 /**
334  * @brief Ethernet MAC transmit interrupt service routine
335  **/
336 
338 {
339  bool_t flag;
340 
341  //Interrupt service routine prologue
342  osEnterIsr();
343 
344  //This flag will be set if a higher priority task must be woken
345  flag = FALSE;
346 
347  //Check interrupt flag
348  if((eth_tx->tx_status & TX_IRQ_MASK_MEMORY_AVAILABLE) != 0)
349  {
350  //Disable TX interrupts
351  eth_tx->tx_irq_mask = 0;
352 
353  //Check whether the TX buffer is available for writing
354  if(!(eth_tx->tx_desc_status))
355  {
356  //Notify the TCP/IP stack that the transmitter is ready to send
357  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
358  }
359  }
360 
361  //Interrupt service routine epilogue
362  osExitIsr(flag);
363 }
364 
365 
366 /**
367  * @brief Ethernet MAC receive interrupt service routine
368  **/
369 
371 {
372  bool_t flag;
373 
374  //Interrupt service routine prologue
375  osEnterIsr();
376 
377  //This flag will be set if a higher priority task must be woken
378  flag = FALSE;
379 
380  //Disable RX interrupts
381  eth_rx->rx_irq_mask = 0;
382 
383  //Set event flag
384  nicDriverInterface->nicEvent = TRUE;
385  //Notify the TCP/IP stack of the event
386  flag = osSetEventFromIsr(&netEvent);
387 
388  //Interrupt service routine epilogue
389  osExitIsr(flag);
390 }
391 
392 
393 /**
394  * @brief Cortus APS3 Ethernet MAC event handler
395  * @param[in] interface Underlying network interface
396  **/
397 
399 {
400  error_t error;
401 
402  //Packet received?
403  if((eth_rx->rx_status & RX_IRQ_MASK_FRAME_READY) != 0)
404  {
405  //Process all pending packets
406  do
407  {
408  //Read incoming packet
409  error = aps3EthReceivePacket(interface);
410 
411  //No more data in the receive buffer?
412  } while(error != ERROR_BUFFER_EMPTY);
413  }
414 
415  //Re-enable RX interrupts
416  eth_rx->rx_irq_mask = RX_IRQ_MASK_FRAME_READY;
417 }
418 
419 
420 /**
421  * @brief Send a packet
422  * @param[in] interface Underlying network interface
423  * @param[in] buffer Multi-part buffer containing the data to send
424  * @param[in] offset Offset to the first data byte
425  * @param[in] ancillary Additional options passed to the stack along with
426  * the packet
427  * @return Error code
428  **/
429 
431  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
432 {
433  uint_t i;
434  size_t length;
435 
436  //Retrieve the length of the packet
437  length = netBufferGetLength(buffer) - offset;
438 
439  //Check the frame length
441  {
442  //The transmitter can accept another packet
443  osSetEvent(&interface->nicTxEvent);
444  //Report an error
445  return ERROR_INVALID_LENGTH;
446  }
447 
448  //Make sure the current buffer is available for writing
449  if(eth_tx->tx_desc_status)
450  {
451  //Re-enable TX interrupts
452  eth_tx->tx_irq_mask = TX_IRQ_MASK_MEMORY_AVAILABLE;
453  //Report an error
454  return ERROR_FAILURE;
455  }
456 
457  //Get the index of the current descriptor
458  i = eth_tx->tx_desc_produce;
459 
460  //Copy user data to the transmit buffer
461  netBufferRead((uint8_t *) txDmaDesc[i].addr, buffer, offset, length);
462  //Write the number of bytes to send
463  txDmaDesc[i].size = length;
464 
465  //Start transmission
466  eth_tx->tx_sw_done = 1;
467 
468  //Check whether the next buffer is available for writing
469  if(!eth_tx->tx_desc_status)
470  {
471  //The transmitter can accept another packet
472  osSetEvent(&interface->nicTxEvent);
473  }
474  else
475  {
476  //Re-enable TX interrupts
477  eth_tx->tx_irq_mask = TX_IRQ_MASK_MEMORY_AVAILABLE;
478  }
479 
480  //Data successfully written
481  return NO_ERROR;
482 }
483 
484 
485 /**
486  * @brief Receive a packet
487  * @param[in] interface Underlying network interface
488  * @return Error code
489  **/
490 
492 {
493  error_t error;
494  uint_t i;
495  size_t n;
496  NetRxAncillary ancillary;
497 
498  //The current buffer is available for reading?
499  if(!(eth_rx->rx_desc_status))
500  {
501  //Point to the current descriptor
502  i = eth_rx->rx_desc_consume;
503 
504  //Make sure no error occurred
505  if((rxDmaDesc[i].status & RX_DESC_RECEIVE_ERROR) == 0)
506  {
507  //Retrieve the length of the frame
508  n = rxDmaDesc[i].size;
509  //Limit the number of data to read
511 
512  //Additional options can be passed to the stack along with the packet
513  ancillary = NET_DEFAULT_RX_ANCILLARY;
514 
515  //Pass the packet to the upper layer
516  nicProcessPacket(interface, (uint8_t *) rxDmaDesc[i].addr, n,
517  &ancillary);
518 
519  //Valid packet received
520  error = NO_ERROR;
521  }
522  else
523  {
524  //The received packet contains an error
525  error = ERROR_INVALID_PACKET;
526  }
527 
528  //The frame has been has been processed by the software
529  //and is no longer needed
530  eth_rx->rx_sw_done = 1;
531  }
532  else
533  {
534  //No more data in the receive buffer
535  error = ERROR_BUFFER_EMPTY;
536  }
537 
538  //Return status code
539  return error;
540 }
541 
542 
543 /**
544  * @brief Configure MAC address filtering
545  * @param[in] interface Underlying network interface
546  * @return Error code
547  **/
548 
550 {
551  uint_t i;
552  uint_t k;
553  uint32_t crc;
554  uint32_t hashTable[2];
555  MacFilterEntry *entry;
556 
557  //Debug message
558  TRACE_DEBUG("Updating MAC filter...\r\n");
559 
560  //Set the MAC address of the station
561  eth_mac->addr_low = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
562  eth_mac->addr_high = interface->macAddr.w[2];
563 
564  //Clear hash table
565  hashTable[0] = 0;
566  hashTable[1] = 0;
567 
568  //The MAC address filter contains the list of MAC addresses to accept
569  //when receiving an Ethernet frame
570  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
571  {
572  //Point to the current entry
573  entry = &interface->macAddrFilter[i];
574 
575  //Valid entry?
576  if(entry->refCount > 0)
577  {
578  //Compute CRC over the current MAC address
579  crc = aps3EthCalcCrc(&entry->addr, sizeof(MacAddr));
580  //Calculate the corresponding index in the table
581  k = (crc >> 23) & 0x3F;
582  //Update hash table contents
583  hashTable[k / 32] |= (1 << (k % 32));
584  }
585  }
586 
587  //Disable transmission and reception
588  eth_tx->tx_enable = 0;
589  eth_rx->rx_enable = 0;
590 
591  //Write the hash table
592  eth_mac->hash_filter_low = hashTable[0];
593  eth_mac->hash_filter_high = hashTable[1];
594 
595  //Debug message
596  TRACE_DEBUG(" hash_filter_low = %08" PRIX32 "\r\n", hashTable[0]);
597  TRACE_DEBUG(" hash_filter_high = %08" PRIX32 "\r\n", hashTable[1]);
598 
599  //Re-enable transmission and reception
600  eth_tx->tx_enable = 1;
601  eth_rx->rx_enable = 1;
602 
603  //Successful processing
604  return NO_ERROR;
605 }
606 
607 
608 /**
609  * @brief Adjust MAC configuration parameters for proper operation
610  * @param[in] interface Underlying network interface
611  * @return Error code
612  **/
613 
615 {
616  //Disable transmission and reception
617  eth_tx->tx_enable = 0;
618  eth_rx->rx_enable = 0;
619 
620  //Half-duplex or full-duplex mode?
621  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
622  {
623  eth_mac->full_duplex = 1;
624  }
625  else
626  {
627  eth_mac->full_duplex = 0;
628  }
629 
630  //Re-enable transmission and reception
631  eth_tx->tx_enable = 1;
632  eth_rx->rx_enable = 1;
633 
634  //Successful processing
635  return NO_ERROR;
636 }
637 
638 
639 /**
640  * @brief Write PHY register
641  * @param[in] opcode Access type (2 bits)
642  * @param[in] phyAddr PHY address (5 bits)
643  * @param[in] regAddr Register address (5 bits)
644  * @param[in] data Register value
645  **/
646 
647 void aps3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
648  uint8_t regAddr, uint16_t data)
649 {
650  //Valid opcode?
651  if(opcode == SMI_OPCODE_WRITE)
652  {
653  //Wait for the MII management module to be ready
654  while(!eth_miim->miim_status)
655  {
656  }
657 
658  //PHY address
659  eth_miim->miim_phy_addr = phyAddr;
660  //Register address
661  eth_miim->miim_phy_register_addr = regAddr;
662  //Data to be written in the PHY register
663  eth_miim->miim_data = data;
664 
665  //Start a write operation
666  eth_miim->miim_read_write = 0;
667  //Wait for the write to complete
668  while(!eth_miim->miim_status)
669  {
670  }
671  }
672  else
673  {
674  //The MAC peripheral only supports standard Clause 22 opcodes
675  }
676 }
677 
678 
679 /**
680  * @brief Read PHY register
681  * @param[in] opcode Access type (2 bits)
682  * @param[in] phyAddr PHY address (5 bits)
683  * @param[in] regAddr Register address (5 bits)
684  * @return Register value
685  **/
686 
687 uint16_t aps3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
688  uint8_t regAddr)
689 {
690  uint16_t data;
691 
692  //Valid opcode?
693  if(opcode == SMI_OPCODE_READ)
694  {
695  //Wait for the MII management module to be ready
696  while(!eth_miim->miim_status)
697  {
698  }
699 
700  //PHY address
701  eth_miim->miim_phy_addr = phyAddr;
702  //Register address
703  eth_miim->miim_phy_register_addr = regAddr;
704 
705  //Start a read operation
706  eth_miim->miim_read_write = 1;
707  //Wait for the read to complete
708  while(!eth_miim->miim_status)
709  {
710  }
711 
712  //Get register value
713  data = eth_miim->miim_data;
714  }
715  else
716  {
717  //The MAC peripheral only supports standard Clause 22 opcodes
718  data = 0;
719  }
720 
721  //Return the value of the PHY register
722  return data;
723 }
724 
725 
726 /**
727  * @brief CRC calculation
728  * @param[in] data Pointer to the data over which to calculate the CRC
729  * @param[in] length Number of bytes to process
730  * @return Resulting CRC value
731  **/
732 
733 uint32_t aps3EthCalcCrc(const void *data, size_t length)
734 {
735  uint_t i;
736  uint_t j;
737  uint32_t crc;
738  const uint8_t *p;
739 
740  //Point to the data over which to calculate the CRC
741  p = (uint8_t *) data;
742  //CRC preset value
743  crc = 0xFFFFFFFF;
744 
745  //Loop through data
746  for(i = 0; i < length; i++)
747  {
748  //Update CRC value
749  crc ^= p[i];
750 
751  //The message is processed bit by bit
752  for(j = 0; j < 8; j++)
753  {
754  //Update CRC value
755  if((crc & 0x01) != 0)
756  {
757  crc = (crc >> 1) ^ 0xEDB88320;
758  }
759  else
760  {
761  crc = crc >> 1;
762  }
763  }
764  }
765 
766  //Return CRC value
767  return ~crc;
768 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define APS3_ETH_RX_BUFFER_COUNT
uint8_t length
Definition: coap_common.h:190
#define TX_IRQ_MASK_MEMORY_AVAILABLE
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define netEvent
Definition: net_legacy.h:267
uint8_t data[]
Definition: ethernet.h:209
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:122
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
uint8_t p
Definition: ndp.h:298
#define APS3_ETH_IRQ_PRIORITY
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
#define RX_IRQ_MASK_FRAME_READY
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
void aps3EthEventHandler(NetInterface *interface)
Cortus APS3 Ethernet MAC event handler.
void aps3EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t aps3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint32_t aps3EthCalcCrc(const void *data, size_t length)
CRC calculation.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define osExitIsr(flag)
#define SMI_OPCODE_WRITE
Definition: nic.h:65
#define FALSE
Definition: os_port.h:46
__start_packed struct @0 MacAddr
MAC address.
void aps3EthTxIrqHandler(void)
Ethernet MAC transmit interrupt service routine.
error_t
Error codes.
Definition: error.h:43
error_t aps3EthReceivePacket(NetInterface *interface)
Receive a packet.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define RX_DESC_RECEIVE_ERROR
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
@ ERROR_INVALID_PACKET
Definition: error.h:139
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:248
@ ERROR_INVALID_LENGTH
Definition: error.h:110
#define APS3_ETH_TX_BUFFER_COUNT
@ ERROR_BUFFER_EMPTY
Definition: error.h:140
#define NetTxAncillary
Definition: net_misc.h:36
void aps3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define SMI_OPCODE_READ
Definition: nic.h:66
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
error_t aps3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define rxBuffer
#define TRACE_DEBUG(...)
Definition: debug.h:107
void aps3EthEnableIrq(NetInterface *interface)
Enable interrupts.
const NicDriver aps3EthDriver
Cortus APS3 Ethernet MAC driver.
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
MAC filter table entry.
Definition: ethernet.h:247
Cortus APS3 Ethernet MAC driver.
#define osEnterIsr()
void aps3EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t aps3EthInit(NetInterface *interface)
Cortus APS3 Ethernet MAC initialization.
void aps3EthTick(NetInterface *interface)
Cortus APS3 Ethernet MAC timer handler.
error_t aps3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
#define rxDmaDesc
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define txDmaDesc
Ipv4Addr addr
Definition: nbns_common.h:121
#define APS3_ETH_TX_BUFFER_SIZE
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
#define APS3_ETH_RX_BUFFER_SIZE
NIC driver.
Definition: nic.h:258
error_t aps3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
@ NO_ERROR
Success.
Definition: error.h:44
Debugging facilities.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:82
void aps3EthRxIrqHandler(void)
Ethernet MAC receive interrupt service routine.