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31 #ifndef _APS3_ETH_DRIVER_H
32 #define _APS3_ETH_DRIVER_H
38 #ifndef APS3_ETH_TX_BUFFER_COUNT
39 #define APS3_ETH_TX_BUFFER_COUNT 4
40 #elif (APS3_ETH_TX_BUFFER_COUNT < 1)
41 #error APS3_ETH_TX_BUFFER_COUNT parameter is not valid
45 #ifndef APS3_ETH_TX_BUFFER_SIZE
46 #define APS3_ETH_TX_BUFFER_SIZE 1536
47 #elif (APS3_ETH_TX_BUFFER_SIZE != 1536)
48 #error APS3_ETH_TX_BUFFER_SIZE parameter is not valid
52 #ifndef APS3_ETH_RX_BUFFER_COUNT
53 #define APS3_ETH_RX_BUFFER_COUNT 4
54 #elif (APS3_ETH_RX_BUFFER_COUNT < 1)
55 #error APS3_ETH_RX_BUFFER_COUNT parameter is not valid
59 #ifndef APS3_ETH_RX_BUFFER_SIZE
60 #define APS3_ETH_RX_BUFFER_SIZE 1536
61 #elif (APS3_ETH_RX_BUFFER_SIZE != 1536)
62 #error APS3_ETH_RX_BUFFER_SIZE parameter is not valid
66 #ifndef APS3_ETH_IRQ_PRIORITY
67 #define APS3_ETH_IRQ_PRIORITY 0
68 #elif (APS3_ETH_IRQ_PRIORITY < 0)
69 #error APS3_ETH_IRQ_PRIORITY parameter is not valid
73 #define TX_IRQ_MASK_TRANSMIT_ERROR 0x0001
74 #define TX_IRQ_MASK_EXCESSIVE_DEFERRAL 0x0002
75 #define TX_IRQ_MASK_EXCESSIVE_COLLISION 0x0004
76 #define TX_IRQ_MASK_LATE_COLLISION 0x0008
77 #define TX_IRQ_MASK_FRAME_TOO_LONG 0x0010
78 #define TX_IRQ_MASK_MEMORY_ERROR 0x0020
79 #define TX_IRQ_MASK_FRAME_SENT 0x0040
80 #define TX_IRQ_MASK_MEMORY_AVAILABLE 0x0080
81 #define TX_IRQ_MASK_THRESHOLD_REACHED 0x0100
82 #define TX_IRQ_MASK_MEMORY_EMPTY 0x0200
85 #define RX_IRQ_MASK_RECEIVE_ERROR 0x0001
86 #define RX_IRQ_MASK_LENGTH_FIELD_ERROR 0x0002
87 #define RX_IRQ_MASK_FRAME_TOO_LONG 0x0004
88 #define RX_IRQ_MASK_SHORT_FRAME 0x0008
89 #define RX_IRQ_MASK_ODD_NIBBLE_COUNT 0x0010
90 #define RX_IRQ_MASK_INVALID_ADDRESS 0x0020
91 #define RX_IRQ_MASK_PHY_ERROR 0x0040
92 #define RX_IRQ_MASK_CRC_ERROR 0x0080
93 #define RX_IRQ_MASK_MEMORY_ERROR 0x0100
94 #define RX_IRQ_MASK_WAKEUP_ON_LAN 0x0200
95 #define RX_IRQ_MASK_FRAME_READY 0x0400
96 #define RX_IRQ_MASK_THRESHOLD_REACHED 0x0800
97 #define RX_IRQ_MASK_FRAME_OVERFLOW 0x1000
100 #define TX_DESC_TRANSMIT_ERROR 0x0001
101 #define TX_DESC_EXCESSIVE_DEFERRAL 0x0002
102 #define TX_DESC_EXCESSIVE_COLLISION 0x0003
103 #define TX_DESC_LATE_COLLISION 0x0004
104 #define TX_DESC_FRAME_TOO_LONG 0x0010
105 #define TX_DESC_MEMORY_ERROR 0x0020
108 #define RX_DESC_RECEIVE_ERROR 0x0001
109 #define RX_DESC_LENGTH_FIELD_ERROR 0x0002
110 #define RX_DESC_FRAME_TOO_LONG 0x0003
111 #define RX_DESC_SHORT_FRAME 0x0004
112 #define RX_DESC_ODD_NIBBLE_COUNT 0x0010
113 #define RX_DESC_INVALID_ADDRESS 0x0020
114 #define RX_DESC_PHY_ERROR 0x0040
115 #define RX_DESC_CRC_ERROR 0x0080
116 #define RX_DESC_MEMORY_ERROR 0x0100
void aps3EthRxIrqHandler(void) __attribute__((noinline))
Ethernet MAC receive interrupt service routine.
void aps3EthTxIrqHandler(void) __attribute__((noinline))
Ethernet MAC transmit interrupt service routine.
Structure describing a buffer that spans multiple chunks.
void aps3EthEventHandler(NetInterface *interface)
Cortus APS3 Ethernet MAC event handler.
void aps3EthEnableIrq(NetInterface *interface)
Enable interrupts.
void aps3EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
const NicDriver aps3EthDriver
Cortus APS3 Ethernet MAC driver.
uint32_t aps3EthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t aps3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void aps3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t aps3EthReceivePacket(NetInterface *interface)
Receive a packet.
error_t aps3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t aps3EthInit(NetInterface *interface)
Cortus APS3 Ethernet MAC initialization.
Network interface controller abstraction layer.
void aps3EthTick(NetInterface *interface)
Cortus APS3 Ethernet MAC timer handler.
error_t aps3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void aps3EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t aps3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.