aps3_eth_driver.h
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1 /**
2  * @file aps3_eth_driver.h
3  * @brief Cortus APS3 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _APS3_ETH_DRIVER_H
32 #define _APS3_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef APS3_ETH_TX_BUFFER_COUNT
39  #define APS3_ETH_TX_BUFFER_COUNT 4
40 #elif (APS3_ETH_TX_BUFFER_COUNT < 1)
41  #error APS3_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef APS3_ETH_TX_BUFFER_SIZE
46  #define APS3_ETH_TX_BUFFER_SIZE 1536
47 #elif (APS3_ETH_TX_BUFFER_SIZE != 1536)
48  #error APS3_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef APS3_ETH_RX_BUFFER_COUNT
53  #define APS3_ETH_RX_BUFFER_COUNT 4
54 #elif (APS3_ETH_RX_BUFFER_COUNT < 1)
55  #error APS3_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef APS3_ETH_RX_BUFFER_SIZE
60  #define APS3_ETH_RX_BUFFER_SIZE 1536
61 #elif (APS3_ETH_RX_BUFFER_SIZE != 1536)
62  #error APS3_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Ethernet interrupt priority
66 #ifndef APS3_ETH_IRQ_PRIORITY
67  #define APS3_ETH_IRQ_PRIORITY 0
68 #elif (APS3_ETH_IRQ_PRIORITY < 0)
69  #error APS3_ETH_IRQ_PRIORITY parameter is not valid
70 #endif
71 
72 //tx_irq_mask register
73 #define TX_IRQ_MASK_TRANSMIT_ERROR 0x0001
74 #define TX_IRQ_MASK_EXCESSIVE_DEFERRAL 0x0002
75 #define TX_IRQ_MASK_EXCESSIVE_COLLISION 0x0004
76 #define TX_IRQ_MASK_LATE_COLLISION 0x0008
77 #define TX_IRQ_MASK_FRAME_TOO_LONG 0x0010
78 #define TX_IRQ_MASK_MEMORY_ERROR 0x0020
79 #define TX_IRQ_MASK_FRAME_SENT 0x0040
80 #define TX_IRQ_MASK_MEMORY_AVAILABLE 0x0080
81 #define TX_IRQ_MASK_THRESHOLD_REACHED 0x0100
82 #define TX_IRQ_MASK_MEMORY_EMPTY 0x0200
83 
84 //rx_irq_mask register
85 #define RX_IRQ_MASK_RECEIVE_ERROR 0x0001
86 #define RX_IRQ_MASK_LENGTH_FIELD_ERROR 0x0002
87 #define RX_IRQ_MASK_FRAME_TOO_LONG 0x0004
88 #define RX_IRQ_MASK_SHORT_FRAME 0x0008
89 #define RX_IRQ_MASK_ODD_NIBBLE_COUNT 0x0010
90 #define RX_IRQ_MASK_INVALID_ADDRESS 0x0020
91 #define RX_IRQ_MASK_PHY_ERROR 0x0040
92 #define RX_IRQ_MASK_CRC_ERROR 0x0080
93 #define RX_IRQ_MASK_MEMORY_ERROR 0x0100
94 #define RX_IRQ_MASK_WAKEUP_ON_LAN 0x0200
95 #define RX_IRQ_MASK_FRAME_READY 0x0400
96 #define RX_IRQ_MASK_THRESHOLD_REACHED 0x0800
97 #define RX_IRQ_MASK_FRAME_OVERFLOW 0x1000
98 
99 //Transmit DMA descriptor flags
100 #define TX_DESC_TRANSMIT_ERROR 0x0001
101 #define TX_DESC_EXCESSIVE_DEFERRAL 0x0002
102 #define TX_DESC_EXCESSIVE_COLLISION 0x0003
103 #define TX_DESC_LATE_COLLISION 0x0004
104 #define TX_DESC_FRAME_TOO_LONG 0x0010
105 #define TX_DESC_MEMORY_ERROR 0x0020
106 
107 //Receive DMA descriptor flags
108 #define RX_DESC_RECEIVE_ERROR 0x0001
109 #define RX_DESC_LENGTH_FIELD_ERROR 0x0002
110 #define RX_DESC_FRAME_TOO_LONG 0x0003
111 #define RX_DESC_SHORT_FRAME 0x0004
112 #define RX_DESC_ODD_NIBBLE_COUNT 0x0010
113 #define RX_DESC_INVALID_ADDRESS 0x0020
114 #define RX_DESC_PHY_ERROR 0x0040
115 #define RX_DESC_CRC_ERROR 0x0080
116 #define RX_DESC_MEMORY_ERROR 0x0100
117 
118 //C++ guard
119 #ifdef __cplusplus
120 extern "C" {
121 #endif
122 
123 
124 /**
125  * @brief TX DMA descriptor
126  **/
127 
128 typedef struct
129 {
130  uint32_t addr;
131  uint32_t size : 16;
132  uint32_t status : 16;
133 } Aps3TxDmaDesc;
134 
135 
136 /**
137  * @brief RX DMA descriptor
138  **/
139 
140 typedef struct
141 {
142  uint32_t addr;
143  uint32_t size : 16;
144  uint32_t status : 16;
145 } Aps3RxDmaDesc;
146 
147 
148 //Cortus APS3 Ethernet MAC driver
149 extern const NicDriver aps3EthDriver;
150 
151 //Cortus APS3 Ethernet MAC related functions
152 error_t aps3EthInit(NetInterface *interface);
153 void aps3EthInitDmaDesc(NetInterface *interface);
154 
155 void aps3EthTick(NetInterface *interface);
156 
157 void aps3EthEnableIrq(NetInterface *interface);
158 void aps3EthDisableIrq(NetInterface *interface);
159 
160 void aps3EthTxIrqHandler(void) __attribute__((noinline));
161 void aps3EthRxIrqHandler(void) __attribute__((noinline));
162 
163 void aps3EthEventHandler(NetInterface *interface);
164 
166  const NetBuffer *buffer, size_t offset);
167 
169 
172 
173 void aps3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
174  uint8_t regAddr, uint16_t data);
175 
176 uint16_t aps3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
177  uint8_t regAddr);
178 
179 uint32_t aps3EthCalcCrc(const void *data, size_t length);
180 
181 //C++ guard
182 #ifdef __cplusplus
183 }
184 #endif
185 
186 #endif
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
void aps3EthRxIrqHandler(void) __attribute__((noinline))
Ethernet MAC receive interrupt service routine.
void aps3EthTxIrqHandler(void) __attribute__((noinline))
Ethernet MAC transmit interrupt service routine.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void aps3EthEventHandler(NetInterface *interface)
Cortus APS3 Ethernet MAC event handler.
void aps3EthEnableIrq(NetInterface *interface)
Enable interrupts.
void aps3EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t
Error codes.
Definition: error.h:42
const NicDriver aps3EthDriver
Cortus APS3 Ethernet MAC driver.
uint32_t aps3EthCalcCrc(const void *data, size_t length)
CRC calculation.
#define NetInterface
Definition: net.h:36
error_t aps3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void aps3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t aps3EthReceivePacket(NetInterface *interface)
Receive a packet.
error_t aps3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint16_t regAddr
error_t aps3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t aps3EthInit(NetInterface *interface)
Cortus APS3 Ethernet MAC initialization.
Network interface controller abstraction layer.
TX DMA descriptor.
void aps3EthTick(NetInterface *interface)
Cortus APS3 Ethernet MAC timer handler.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
RX DMA descriptor.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void aps3EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t aps3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.