aps3_eth_driver.h
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1 /**
2  * @file aps3_eth_driver.h
3  * @brief Cortus APS3 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _APS3_ETH_DRIVER_H
30 #define _APS3_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef APS3_ETH_TX_BUFFER_COUNT
37  #define APS3_ETH_TX_BUFFER_COUNT 4
38 #elif (APS3_ETH_TX_BUFFER_COUNT < 1)
39  #error APS3_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef APS3_ETH_TX_BUFFER_SIZE
44  #define APS3_ETH_TX_BUFFER_SIZE 1536
45 #elif (APS3_ETH_TX_BUFFER_SIZE != 1536)
46  #error APS3_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef APS3_ETH_RX_BUFFER_COUNT
51  #define APS3_ETH_RX_BUFFER_COUNT 4
52 #elif (APS3_ETH_RX_BUFFER_COUNT < 1)
53  #error APS3_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef APS3_ETH_RX_BUFFER_SIZE
58  #define APS3_ETH_RX_BUFFER_SIZE 1536
59 #elif (APS3_ETH_RX_BUFFER_SIZE != 1536)
60  #error APS3_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Ethernet interrupt priority
64 #ifndef APS3_ETH_IRQ_PRIORITY
65  #define APS3_ETH_IRQ_PRIORITY 0
66 #elif (APS3_ETH_IRQ_PRIORITY < 0)
67  #error APS3_ETH_IRQ_PRIORITY parameter is not valid
68 #endif
69 
70 //tx_irq_mask register
71 #define TX_IRQ_MASK_TRANSMIT_ERROR 0x0001
72 #define TX_IRQ_MASK_EXCESSIVE_DEFERRAL 0x0002
73 #define TX_IRQ_MASK_EXCESSIVE_COLLISION 0x0004
74 #define TX_IRQ_MASK_LATE_COLLISION 0x0008
75 #define TX_IRQ_MASK_FRAME_TOO_LONG 0x0010
76 #define TX_IRQ_MASK_MEMORY_ERROR 0x0020
77 #define TX_IRQ_MASK_FRAME_SENT 0x0040
78 #define TX_IRQ_MASK_MEMORY_AVAILABLE 0x0080
79 #define TX_IRQ_MASK_THRESHOLD_REACHED 0x0100
80 #define TX_IRQ_MASK_MEMORY_EMPTY 0x0200
81 
82 //rx_irq_mask register
83 #define RX_IRQ_MASK_RECEIVE_ERROR 0x0001
84 #define RX_IRQ_MASK_LENGTH_FIELD_ERROR 0x0002
85 #define RX_IRQ_MASK_FRAME_TOO_LONG 0x0004
86 #define RX_IRQ_MASK_SHORT_FRAME 0x0008
87 #define RX_IRQ_MASK_ODD_NIBBLE_COUNT 0x0010
88 #define RX_IRQ_MASK_INVALID_ADDRESS 0x0020
89 #define RX_IRQ_MASK_PHY_ERROR 0x0040
90 #define RX_IRQ_MASK_CRC_ERROR 0x0080
91 #define RX_IRQ_MASK_MEMORY_ERROR 0x0100
92 #define RX_IRQ_MASK_WAKEUP_ON_LAN 0x0200
93 #define RX_IRQ_MASK_FRAME_READY 0x0400
94 #define RX_IRQ_MASK_THRESHOLD_REACHED 0x0800
95 #define RX_IRQ_MASK_FRAME_OVERFLOW 0x1000
96 
97 //Transmit DMA descriptor flags
98 #define TX_DESC_TRANSMIT_ERROR 0x0001
99 #define TX_DESC_EXCESSIVE_DEFERRAL 0x0002
100 #define TX_DESC_EXCESSIVE_COLLISION 0x0003
101 #define TX_DESC_LATE_COLLISION 0x0004
102 #define TX_DESC_FRAME_TOO_LONG 0x0010
103 #define TX_DESC_MEMORY_ERROR 0x0020
104 
105 //Receive DMA descriptor flags
106 #define RX_DESC_RECEIVE_ERROR 0x0001
107 #define RX_DESC_LENGTH_FIELD_ERROR 0x0002
108 #define RX_DESC_FRAME_TOO_LONG 0x0003
109 #define RX_DESC_SHORT_FRAME 0x0004
110 #define RX_DESC_ODD_NIBBLE_COUNT 0x0010
111 #define RX_DESC_INVALID_ADDRESS 0x0020
112 #define RX_DESC_PHY_ERROR 0x0040
113 #define RX_DESC_CRC_ERROR 0x0080
114 #define RX_DESC_MEMORY_ERROR 0x0100
115 
116 //C++ guard
117 #ifdef __cplusplus
118  extern "C" {
119 #endif
120 
121 
122 /**
123  * @brief TX DMA descriptor
124  **/
125 
126 typedef struct
127 {
128  uint32_t addr;
129  uint32_t size : 16;
130  uint32_t status : 16;
131 } Aps3TxDmaDesc;
132 
133 
134 /**
135  * @brief RX DMA descriptor
136  **/
137 
138 typedef struct
139 {
140  uint32_t addr;
141  uint32_t size : 16;
142  uint32_t status : 16;
143 } Aps3RxDmaDesc;
144 
145 
146 //Cortus APS3 Ethernet MAC driver
147 extern const NicDriver aps3EthDriver;
148 
149 //Cortus APS3 Ethernet MAC related functions
150 error_t aps3EthInit(NetInterface *interface);
151 void aps3EthInitDmaDesc(NetInterface *interface);
152 
153 void aps3EthTick(NetInterface *interface);
154 
155 void aps3EthEnableIrq(NetInterface *interface);
156 void aps3EthDisableIrq(NetInterface *interface);
157 
158 void aps3EthTxIrqHandler(void) __attribute__((noinline));
159 void aps3EthRxIrqHandler(void) __attribute__((noinline));
160 
161 void aps3EthEventHandler(NetInterface *interface);
162 
164  const NetBuffer *buffer, size_t offset);
165 
167 
170 
171 void aps3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
172 uint16_t aps3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
173 
174 uint32_t aps3EthCalcCrc(const void *data, size_t length);
175 
176 //C++ guard
177 #ifdef __cplusplus
178  }
179 #endif
180 
181 #endif
void aps3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t aps3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t aps3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void aps3EthTick(NetInterface *interface)
Cortus APS3 Ethernet MAC timer handler.
void aps3EthDisableIrq(NetInterface *interface)
Disable interrupts.
void aps3EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
TX DMA descriptor.
error_t aps3EthReceivePacket(NetInterface *interface)
Receive a packet.
const NicDriver aps3EthDriver
Cortus APS3 Ethernet MAC driver.
void aps3EthEnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t aps3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint32_t aps3EthCalcCrc(const void *data, size_t length)
CRC calculation.
void aps3EthEventHandler(NetInterface *interface)
Cortus APS3 Ethernet MAC event handler.
RX DMA descriptor.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
error_t aps3EthInit(NetInterface *interface)
Cortus APS3 Ethernet MAC initialization.
uint16_t regAddr
error_t
Error codes.
Definition: error.h:40
void aps3EthRxIrqHandler(void) __attribute__((noinline))
Ethernet MAC receive interrupt service routine.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
error_t aps3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint8_t length
Definition: dtls_misc.h:140
void aps3EthTxIrqHandler(void) __attribute__((noinline))
Ethernet MAC transmit interrupt service routine.
Network interface controller abstraction layer.