avr32_eth_driver.h
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1 /**
2  * @file avr32_eth_driver.h
3  * @brief AVR32 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _AVR32_ETH_DRIVER_H
30 #define _AVR32_ETH_DRIVER_H
31 
32 //Number of TX buffers
33 #ifndef AVR32_ETH_TX_BUFFER_COUNT
34  #define AVR32_ETH_TX_BUFFER_COUNT 2
35 #elif (AVR32_ETH_TX_BUFFER_COUNT < 1)
36  #error AVR32_ETH_TX_BUFFER_COUNT parameter is not valid
37 #endif
38 
39 //TX buffer size
40 #ifndef AVR32_ETH_TX_BUFFER_SIZE
41  #define AVR32_ETH_TX_BUFFER_SIZE 1536
42 #elif (AVR32_ETH_TX_BUFFER_SIZE != 1536)
43  #error AVR32_ETH_TX_BUFFER_SIZE parameter is not valid
44 #endif
45 
46 //Number of RX buffers
47 #ifndef AVR32_ETH_RX_BUFFER_COUNT
48  #define AVR32_ETH_RX_BUFFER_COUNT 48
49 #elif (AVR32_ETH_RX_BUFFER_COUNT < 12)
50  #error AVR32_ETH_RX_BUFFER_COUNT parameter is not valid
51 #endif
52 
53 //RX buffer size
54 #ifndef AVR32_ETH_RX_BUFFER_SIZE
55  #define AVR32_ETH_RX_BUFFER_SIZE 128
56 #elif (AVR32_ETH_RX_BUFFER_SIZE != 128)
57  #error AVR32_ETH_RX_BUFFER_SIZE parameter is not valid
58 #endif
59 
60 //Ethernet interrupt priority
61 #ifndef AVR32_ETH_IRQ_PRIORITY
62  #define AVR32_ETH_IRQ_PRIORITY 2
63 #elif (AVR32_ETH_IRQ_PRIORITY < 0 || AVR32_ETH_IRQ_PRIORITY > 3)
64  #error AVR32_ETH_IRQ_PRIORITY parameter is not valid
65 #endif
66 
67 //RMII pin definition
68 #define MACB_RMII_EREFCK_MASK (1 << (AVR32_MACB_TX_CLK_0_PIN - 32))
69 #define MACB_RMII_ETXEN_MASK (1 << (AVR32_MACB_TX_EN_0_PIN - 32))
70 #define MACB_RMII_ETX0_MASK (1 << (AVR32_MACB_TXD_0_PIN - 32))
71 #define MACB_RMII_ETX1_MASK (1 << (AVR32_MACB_TXD_1_PIN - 32))
72 #define MACB_RMII_ERX0_MASK (1 << (AVR32_MACB_RXD_0_PIN - 32))
73 #define MACB_RMII_ERX1_MASK (1 << (AVR32_MACB_RXD_1_PIN - 32))
74 #define MACB_RMII_ERXER_MASK (1 << (AVR32_MACB_RX_ER_0_PIN - 32))
75 #define MACB_RMII_ECRSDV_MASK (1 << (AVR32_MACB_RX_DV_0_PIN - 32))
76 #define MACB_RMII_MDC_MASK (1 << (AVR32_MACB_MDC_0_PIN - 32))
77 #define MACB_RMII_MDIO_MASK (1 << (AVR32_MACB_MDIO_0_PIN - 32))
78 
79 //RMII signals
80 #define MACB_RMII_MASK (MACB_RMII_EREFCK_MASK | MACB_RMII_ETXEN_MASK | \
81  MACB_RMII_ETX0_MASK | MACB_RMII_ETX1_MASK | MACB_RMII_ERX0_MASK | MACB_RMII_ERX1_MASK | \
82  MACB_RMII_ERXER_MASK | MACB_RMII_ECRSDV_MASK | MACB_RMII_MDC_MASK | MACB_RMII_MDIO_MASK)
83 
84 //PHY maintenance register (MAN)
85 #define MACB_MAN_SOF_01 (1 << AVR32_MACB_MAN_SOF_OFFSET)
86 #define MACB_MAN_RW_01 (1 << AVR32_MACB_MAN_RW_OFFSET)
87 #define MACB_MAN_RW_10 (2 << AVR32_MACB_MAN_RW_OFFSET)
88 #define MACB_MAN_CODE_10 (2 << AVR32_MACB_MAN_CODE_OFFSET)
89 
90 //TX buffer descriptor flags
91 #define MACB_TX_USED 0x80000000
92 #define MACB_TX_WRAP 0x40000000
93 #define MACB_TX_ERROR 0x20000000
94 #define MACB_TX_UNDERRUN 0x10000000
95 #define MACB_TX_EXHAUSTED 0x08000000
96 #define MACB_TX_NO_CRC 0x00010000
97 #define MACB_TX_LAST 0x00008000
98 #define MACB_TX_LENGTH 0x000007FF
99 
100 //RX buffer descriptor flags
101 #define MACB_RX_ADDRESS 0xFFFFFFFC
102 #define MACB_RX_WRAP 0x00000002
103 #define MACB_RX_OWNERSHIP 0x00000001
104 #define MACB_RX_BROADCAST 0x80000000
105 #define MACB_RX_MULTICAST_HASH 0x40000000
106 #define MACB_RX_UNICAST_HASH 0x20000000
107 #define MACB_RX_EXT_ADDR 0x10000000
108 #define MACB_RX_SAR1 0x04000000
109 #define MACB_RX_SAR2 0x02000000
110 #define MACB_RX_SAR3 0x01000000
111 #define MACB_RX_SAR4 0x00800000
112 #define MACB_RX_TYPE_ID 0x00400000
113 #define MACB_RX_VLAN_TAG 0x00200000
114 #define MACB_RX_PRIORITY_TAG 0x00100000
115 #define MACB_RX_VLAN_PRIORITY 0x000E0000
116 #define MACB_RX_CFI 0x00010000
117 #define MACB_RX_EOF 0x00008000
118 #define MACB_RX_SOF 0x00004000
119 #define MACB_RX_OFFSET 0x00003000
120 #define MACB_RX_LENGTH 0x00000FFF
121 
122 //C++ guard
123 #ifdef __cplusplus
124  extern "C" {
125 #endif
126 
127 
128 /**
129  * @brief Transmit buffer descriptor
130  **/
131 
132 typedef struct
133 {
134  uint32_t address;
135  uint32_t status;
137 
138 
139 /**
140  * @brief Receive buffer descriptor
141  **/
142 
143 typedef struct
144 {
145  uint32_t address;
146  uint32_t status;
148 
149 
150 //AVR32 Ethernet MAC driver
151 extern const NicDriver avr32EthDriver;
152 
153 //AVR32 Ethernet MAC related functions
154 error_t avr32EthInit(NetInterface *interface);
155 void avr32EthInitGpio(NetInterface *interface);
156 void avr32EthInitBufferDesc(NetInterface *interface);
157 
158 void avr32EthTick(NetInterface *interface);
159 
160 void avr32EthEnableIrq(NetInterface *interface);
161 void avr32EthDisableIrq(NetInterface *interface);
162 void avr32EthIrqWrapper(void);
164 void avr32EthEventHandler(NetInterface *interface);
165 
167  const NetBuffer *buffer, size_t offset);
168 
170 
173 
174 void avr32EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
175 uint16_t avr32EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
176 
177 //C++ guard
178 #ifdef __cplusplus
179  }
180 #endif
181 
182 #endif
void avr32EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
error_t avr32EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void avr32EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void avr32EthInitGpio(NetInterface *interface)
void avr32EthTick(NetInterface *interface)
AVR32 Ethernet MAC timer handler.
error_t avr32EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint16_t avr32EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void avr32EthIrqWrapper(void)
Transmit buffer descriptor.
const NicDriver avr32EthDriver
AVR32 Ethernet MAC driver.
NIC driver.
Definition: nic.h:161
error_t avr32EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
error_t avr32EthReceivePacket(NetInterface *interface)
Receive a packet.
Receive buffer descriptor.
uint16_t regAddr
void avr32EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void avr32EthDisableIrq(NetInterface *interface)
Disable interrupts.
void avr32EthEventHandler(NetInterface *interface)
AVR32 Ethernet MAC event handler.
error_t avr32EthInit(NetInterface *interface)
AVR32 Ethernet MAC initialization.
int bool_t
Definition: compiler_port.h:47
bool_t avr32EthIrqHandler(void)
AVR32 Ethernet MAC interrupt service routine.