avr32_eth_driver.h
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1 /**
2  * @file avr32_eth_driver.h
3  * @brief AVR32 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _AVR32_ETH_DRIVER_H
32 #define _AVR32_ETH_DRIVER_H
33 
34 //Number of TX buffers
35 #ifndef AVR32_ETH_TX_BUFFER_COUNT
36  #define AVR32_ETH_TX_BUFFER_COUNT 2
37 #elif (AVR32_ETH_TX_BUFFER_COUNT < 1)
38  #error AVR32_ETH_TX_BUFFER_COUNT parameter is not valid
39 #endif
40 
41 //TX buffer size
42 #ifndef AVR32_ETH_TX_BUFFER_SIZE
43  #define AVR32_ETH_TX_BUFFER_SIZE 1536
44 #elif (AVR32_ETH_TX_BUFFER_SIZE != 1536)
45  #error AVR32_ETH_TX_BUFFER_SIZE parameter is not valid
46 #endif
47 
48 //Number of RX buffers
49 #ifndef AVR32_ETH_RX_BUFFER_COUNT
50  #define AVR32_ETH_RX_BUFFER_COUNT 48
51 #elif (AVR32_ETH_RX_BUFFER_COUNT < 12)
52  #error AVR32_ETH_RX_BUFFER_COUNT parameter is not valid
53 #endif
54 
55 //RX buffer size
56 #ifndef AVR32_ETH_RX_BUFFER_SIZE
57  #define AVR32_ETH_RX_BUFFER_SIZE 128
58 #elif (AVR32_ETH_RX_BUFFER_SIZE != 128)
59  #error AVR32_ETH_RX_BUFFER_SIZE parameter is not valid
60 #endif
61 
62 //Ethernet interrupt priority
63 #ifndef AVR32_ETH_IRQ_PRIORITY
64  #define AVR32_ETH_IRQ_PRIORITY 2
65 #elif (AVR32_ETH_IRQ_PRIORITY < 0 || AVR32_ETH_IRQ_PRIORITY > 3)
66  #error AVR32_ETH_IRQ_PRIORITY parameter is not valid
67 #endif
68 
69 //RMII pin definition
70 #define MACB_RMII_EREFCK_MASK (1 << (AVR32_MACB_TX_CLK_0_PIN - 32))
71 #define MACB_RMII_ETXEN_MASK (1 << (AVR32_MACB_TX_EN_0_PIN - 32))
72 #define MACB_RMII_ETX0_MASK (1 << (AVR32_MACB_TXD_0_PIN - 32))
73 #define MACB_RMII_ETX1_MASK (1 << (AVR32_MACB_TXD_1_PIN - 32))
74 #define MACB_RMII_ERX0_MASK (1 << (AVR32_MACB_RXD_0_PIN - 32))
75 #define MACB_RMII_ERX1_MASK (1 << (AVR32_MACB_RXD_1_PIN - 32))
76 #define MACB_RMII_ERXER_MASK (1 << (AVR32_MACB_RX_ER_0_PIN - 32))
77 #define MACB_RMII_ECRSDV_MASK (1 << (AVR32_MACB_RX_DV_0_PIN - 32))
78 #define MACB_RMII_MDC_MASK (1 << (AVR32_MACB_MDC_0_PIN - 32))
79 #define MACB_RMII_MDIO_MASK (1 << (AVR32_MACB_MDIO_0_PIN - 32))
80 
81 //RMII signals
82 #define MACB_RMII_MASK (MACB_RMII_EREFCK_MASK | MACB_RMII_ETXEN_MASK | \
83  MACB_RMII_ETX0_MASK | MACB_RMII_ETX1_MASK | MACB_RMII_ERX0_MASK | MACB_RMII_ERX1_MASK | \
84  MACB_RMII_ERXER_MASK | MACB_RMII_ECRSDV_MASK | MACB_RMII_MDC_MASK | MACB_RMII_MDIO_MASK)
85 
86 //PHY maintenance register (MAN)
87 #define MACB_MAN_SOF_01 (1 << AVR32_MACB_MAN_SOF_OFFSET)
88 #define MACB_MAN_RW_01 (1 << AVR32_MACB_MAN_RW_OFFSET)
89 #define MACB_MAN_RW_10 (2 << AVR32_MACB_MAN_RW_OFFSET)
90 #define MACB_MAN_CODE_10 (2 << AVR32_MACB_MAN_CODE_OFFSET)
91 
92 //TX buffer descriptor flags
93 #define MACB_TX_USED 0x80000000
94 #define MACB_TX_WRAP 0x40000000
95 #define MACB_TX_ERROR 0x20000000
96 #define MACB_TX_UNDERRUN 0x10000000
97 #define MACB_TX_EXHAUSTED 0x08000000
98 #define MACB_TX_NO_CRC 0x00010000
99 #define MACB_TX_LAST 0x00008000
100 #define MACB_TX_LENGTH 0x000007FF
101 
102 //RX buffer descriptor flags
103 #define MACB_RX_ADDRESS 0xFFFFFFFC
104 #define MACB_RX_WRAP 0x00000002
105 #define MACB_RX_OWNERSHIP 0x00000001
106 #define MACB_RX_BROADCAST 0x80000000
107 #define MACB_RX_MULTICAST_HASH 0x40000000
108 #define MACB_RX_UNICAST_HASH 0x20000000
109 #define MACB_RX_EXT_ADDR 0x10000000
110 #define MACB_RX_SAR1 0x04000000
111 #define MACB_RX_SAR2 0x02000000
112 #define MACB_RX_SAR3 0x01000000
113 #define MACB_RX_SAR4 0x00800000
114 #define MACB_RX_TYPE_ID 0x00400000
115 #define MACB_RX_VLAN_TAG 0x00200000
116 #define MACB_RX_PRIORITY_TAG 0x00100000
117 #define MACB_RX_VLAN_PRIORITY 0x000E0000
118 #define MACB_RX_CFI 0x00010000
119 #define MACB_RX_EOF 0x00008000
120 #define MACB_RX_SOF 0x00004000
121 #define MACB_RX_OFFSET 0x00003000
122 #define MACB_RX_LENGTH 0x00000FFF
123 
124 //C++ guard
125 #ifdef __cplusplus
126 extern "C" {
127 #endif
128 
129 
130 /**
131  * @brief Transmit buffer descriptor
132  **/
133 
134 typedef struct
135 {
136  uint32_t address;
137  uint32_t status;
139 
140 
141 /**
142  * @brief Receive buffer descriptor
143  **/
144 
145 typedef struct
146 {
147  uint32_t address;
148  uint32_t status;
150 
151 
152 //AVR32 Ethernet MAC driver
153 extern const NicDriver avr32EthDriver;
154 
155 //AVR32 Ethernet MAC related functions
156 error_t avr32EthInit(NetInterface *interface);
157 void avr32EthInitGpio(NetInterface *interface);
158 void avr32EthInitBufferDesc(NetInterface *interface);
159 
160 void avr32EthTick(NetInterface *interface);
161 
162 void avr32EthEnableIrq(NetInterface *interface);
163 void avr32EthDisableIrq(NetInterface *interface);
164 void avr32EthIrqWrapper(void);
166 void avr32EthEventHandler(NetInterface *interface);
167 
169  const NetBuffer *buffer, size_t offset);
170 
172 
175 
176 void avr32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
177  uint8_t regAddr, uint16_t data);
178 
179 uint16_t avr32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
180  uint8_t regAddr);
181 
182 //C++ guard
183 #ifdef __cplusplus
184 }
185 #endif
186 
187 #endif
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
error_t avr32EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t avr32EthInit(NetInterface *interface)
AVR32 Ethernet MAC initialization.
void avr32EthDisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver avr32EthDriver
AVR32 Ethernet MAC driver.
Transmit buffer descriptor.
error_t
Error codes.
Definition: error.h:42
error_t avr32EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void avr32EthEventHandler(NetInterface *interface)
AVR32 Ethernet MAC event handler.
Receive buffer descriptor.
uint16_t avr32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define NetInterface
Definition: net.h:36
bool_t avr32EthIrqHandler(void)
AVR32 Ethernet MAC interrupt service routine.
void avr32EthInitGpio(NetInterface *interface)
void avr32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void avr32EthTick(NetInterface *interface)
AVR32 Ethernet MAC timer handler.
error_t avr32EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint16_t regAddr
void avr32EthIrqWrapper(void)
void avr32EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
error_t avr32EthReceivePacket(NetInterface *interface)
Receive a packet.
void avr32EthEnableIrq(NetInterface *interface)
Enable interrupts.