avr32_eth_driver.c
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1 /**
2  * @file avr32_eth_driver.c
3  * @brief AVR32 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <limits.h>
34 #include <avr32/io.h>
35 #include "interrupt.h"
36 #include "intc.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 4
50 //RX buffer
51 #pragma data_alignment = 4
53 //TX buffer descriptors
54 #pragma data_alignment = 8
55 static Avr32TxBufferDesc txBufferDesc[AVR32_ETH_TX_BUFFER_COUNT];
56 //RX buffer descriptors
57 #pragma data_alignment = 8
58 static Avr32RxBufferDesc rxBufferDesc[AVR32_ETH_RX_BUFFER_COUNT];
59 
60 //GCC compiler?
61 #else
62 
63 //TX buffer
65  __attribute__((aligned(4)));
66 //RX buffer
68  __attribute__((aligned(4)));
69 //TX buffer descriptors
71  __attribute__((aligned(8)));
72 //RX buffer descriptors
74  __attribute__((aligned(8)));
75 
76 #endif
77 
78 //TX buffer index
79 static uint_t txBufferIndex;
80 //RX buffer index
81 static uint_t rxBufferIndex;
82 
83 
84 /**
85  * @brief AVR32 Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  FALSE
106 };
107 
108 
109 /**
110  * @brief AVR32 Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118  volatile uint32_t status;
119 
120  //Debug message
121  TRACE_INFO("Initializing AVR32 Ethernet MAC...\r\n");
122 
123  //Save underlying network interface
124  nicDriverInterface = interface;
125 
126  //GPIO configuration
127  avr32EthInitGpio(interface);
128 
129  //Configure MDC clock speed
130  AVR32_MACB.ncfgr = AVR32_MACB_NCFGR_CLK_DIV64;
131  //Enable management port (MDC and MDIO)
132  AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;
133 
134  //PHY transceiver initialization
135  error = interface->phyDriver->init(interface);
136  //Failed to initialize PHY transceiver?
137  if(error)
138  return error;
139 
140  //Set the MAC address
141  AVR32_MACB.sa1b = interface->macAddr.b[0] |
142  (interface->macAddr.b[1] << 8) |
143  (interface->macAddr.b[2] << 16) |
144  (interface->macAddr.b[3] << 24);
145 
146  AVR32_MACB.sa1t = interface->macAddr.b[4] |
147  (interface->macAddr.b[5] << 8);
148 
149  //Configure the receive filter
150  AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_UNI_MASK | AVR32_MACB_NCFGR_MTI_MASK;
151 
152  //Initialize hash table
153  AVR32_MACB.hrb = 0;
154  AVR32_MACB.hrt = 0;
155 
156  //Initialize buffer descriptors
157  avr32EthInitBufferDesc(interface);
158 
159  //Clear transmit status register
160  AVR32_MACB.tsr = AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK | AVR32_MACB_TSR_BEX_MASK |
161  AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK | AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK;
162  //Clear receive status register
163  AVR32_MACB.rsr = AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK;
164 
165  //First disable all EMAC interrupts
166  AVR32_MACB.idr = 0xFFFFFFFF;
167  //Only the desired ones are enabled
168  AVR32_MACB.ier = AVR32_MACB_IER_ROVR_MASK | AVR32_MACB_IER_TCOMP_MASK | AVR32_MACB_IER_TXERR_MASK |
169  AVR32_MACB_IER_RLE_MASK | AVR32_MACB_IER_TUND_MASK | AVR32_MACB_IER_RXUBR_MASK | AVR32_MACB_IER_RCOMP_MASK;
170 
171  //Read EMAC ISR register to clear any pending interrupt
172  status = AVR32_MACB.isr;
173 
174  //Register interrupt handler
175  INTC_register_interrupt(avr32EthIrqWrapper, AVR32_MACB_IRQ, AVR32_ETH_IRQ_PRIORITY);
176 
177  //Enable the EMAC to transmit and receive data
178  AVR32_MACB.ncr |= AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
179 
180  //Accept any packets from the upper layer
181  osSetEvent(&interface->nicTxEvent);
182 
183  //Successful initialization
184  return NO_ERROR;
185 }
186 
187 
188 //EVK1105 evaluation board?
189 #if defined(USE_EVK1105)
190 
191 /**
192  * @brief GPIO configuration
193  * @param[in] interface Underlying network interface
194  **/
195 
196 void avr32EthInitGpio(NetInterface *interface)
197 {
198  //Assign RMII pins to peripheral A function
199  AVR32_GPIO.port[1].pmr0c = MACB_RMII_MASK;
200  AVR32_GPIO.port[1].pmr1c =MACB_RMII_MASK;
201 
202  //Disable the PIO from controlling the corresponding pins
203  AVR32_GPIO.port[1].gperc = MACB_RMII_MASK;
204 
205  //Select RMII operation mode
206  AVR32_MACB.usrio &= ~AVR32_MACB_USRIO_RMII_MASK;
207 }
208 
209 #endif
210 
211 
212 /**
213  * @brief Initialize buffer descriptors
214  * @param[in] interface Underlying network interface
215  **/
216 
218 {
219  uint_t i;
220  uint32_t address;
221 
222  //Initialize TX buffer descriptors
223  for(i = 0; i < AVR32_ETH_TX_BUFFER_COUNT; i++)
224  {
225  //Calculate the address of the current TX buffer
226  address = (uint32_t) txBuffer[i];
227  //Write the address to the descriptor entry
228  txBufferDesc[i].address = address;
229  //Initialize status field
230  txBufferDesc[i].status = MACB_TX_USED;
231  }
232 
233  //Mark the last descriptor entry with the wrap flag
234  txBufferDesc[i - 1].status |= MACB_TX_WRAP;
235  //Initialize TX buffer index
236  txBufferIndex = 0;
237 
238  //Initialize RX buffer descriptors
239  for(i = 0; i < AVR32_ETH_RX_BUFFER_COUNT; i++)
240  {
241  //Calculate the address of the current RX buffer
242  address = (uint32_t) rxBuffer[i];
243  //Write the address to the descriptor entry
244  rxBufferDesc[i].address = address & MACB_RX_ADDRESS;
245  //Clear status field
246  rxBufferDesc[i].status = 0;
247  }
248 
249  //Mark the last descriptor entry with the wrap flag
250  rxBufferDesc[i - 1].address |= MACB_RX_WRAP;
251  //Initialize RX buffer index
252  rxBufferIndex = 0;
253 
254  //Start location of the TX descriptor list
255  AVR32_MACB.tbqp = (uint32_t) txBufferDesc;
256  //Start location of the RX descriptor list
257  AVR32_MACB.rbqp = (uint32_t) rxBufferDesc;
258 }
259 
260 
261 /**
262  * @brief AVR32 Ethernet MAC timer handler
263  *
264  * This routine is periodically called by the TCP/IP stack to
265  * handle periodic operations such as polling the link state
266  *
267  * @param[in] interface Underlying network interface
268  **/
269 
270 void avr32EthTick(NetInterface *interface)
271 {
272  //Handle periodic operations
273  interface->phyDriver->tick(interface);
274 }
275 
276 
277 /**
278  * @brief Enable interrupts
279  * @param[in] interface Underlying network interface
280  **/
281 
283 {
284  //Enable Ethernet MAC interrupts
285  Enable_global_interrupt();
286  //Enable Ethernet PHY interrupts
287  interface->phyDriver->enableIrq(interface);
288 }
289 
290 
291 /**
292  * @brief Disable interrupts
293  * @param[in] interface Underlying network interface
294  **/
295 
297 {
298  //Disable Ethernet MAC interrupts
299  Disable_global_interrupt();
300  //Disable Ethernet PHY interrupts
301  interface->phyDriver->disableIrq(interface);
302 }
303 
304 
305 /**
306  * @brief AVR32 Ethernet MAC interrupt wrapper
307  **/
308 
310 {
311  //Enter interrupt service routine
312  osEnterIsr();
313 
314  //Call Ethernet MAC interrupt handler
316 
317  //Leave interrupt service routine
318  osExitIsr(flag);
319 }
320 
321 
322 /**
323  * @brief AVR32 Ethernet MAC interrupt service routine
324  * @return TRUE if a higher priority task must be woken. Else FALSE is returned
325  **/
326 
328 {
329  bool_t flag;
330  volatile uint32_t isr;
331  volatile uint32_t tsr;
332  volatile uint32_t rsr;
333 
334  //This flag will be set if a higher priority task must be woken
335  flag = FALSE;
336 
337  //Each time the software reads EMAC_ISR, it has to check the
338  //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
339  isr = AVR32_MACB.isr;
340  tsr = AVR32_MACB.tsr;
341  rsr = AVR32_MACB.rsr;
342 
343  //A packet has been transmitted?
344  if(tsr & (AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK | AVR32_MACB_TSR_BEX_MASK |
345  AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK | AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK))
346  {
347  //Only clear TSR flags that are currently set
348  AVR32_MACB.tsr = tsr;
349 
350  //Check whether the TX buffer is available for writing
351  if(txBufferDesc[txBufferIndex].status & MACB_TX_USED)
352  {
353  //Notify the TCP/IP stack that the transmitter is ready to send
354  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
355  }
356  }
357 
358  //A packet has been received?
359  if(rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK))
360  {
361  //Set event flag
362  nicDriverInterface->nicEvent = TRUE;
363  //Notify the TCP/IP stack of the event
364  flag |= osSetEventFromIsr(&netEvent);
365  }
366 
367  //A higher priority task must be woken?
368  return flag;
369 }
370 
371 
372 /**
373  * @brief AVR32 Ethernet MAC event handler
374  * @param[in] interface Underlying network interface
375  **/
376 
378 {
379  error_t error;
380  uint32_t rsr;
381 
382  //Read receive status
383  rsr = AVR32_MACB.rsr;
384 
385  //Packet received?
386  if(rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK))
387  {
388  //Only clear RSR flags that are currently set
389  AVR32_MACB.rsr = rsr;
390 
391  //Process all pending packets
392  do
393  {
394  //Read incoming packet
395  error = avr32EthReceivePacket(interface);
396 
397  //No more data in the receive buffer?
398  } while(error != ERROR_BUFFER_EMPTY);
399  }
400 }
401 
402 
403 /**
404  * @brief Send a packet
405  * @param[in] interface Underlying network interface
406  * @param[in] buffer Multi-part buffer containing the data to send
407  * @param[in] offset Offset to the first data byte
408  * @return Error code
409  **/
410 
412  const NetBuffer *buffer, size_t offset)
413 {
414  size_t length;
415 
416  //Retrieve the length of the packet
417  length = netBufferGetLength(buffer) - offset;
418 
419  //Check the frame length
421  {
422  //The transmitter can accept another packet
423  osSetEvent(&interface->nicTxEvent);
424  //Report an error
425  return ERROR_INVALID_LENGTH;
426  }
427 
428  //Make sure the current buffer is available for writing
429  if(!(txBufferDesc[txBufferIndex].status & MACB_TX_USED))
430  return ERROR_FAILURE;
431 
432  //Copy user data to the transmit buffer
433  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
434 
435  //Set the necessary flags in the descriptor entry
436  if(txBufferIndex < (AVR32_ETH_TX_BUFFER_COUNT - 1))
437  {
438  //Write the status word
439  txBufferDesc[txBufferIndex].status =
441 
442  //Point to the next buffer
443  txBufferIndex++;
444  }
445  else
446  {
447  //Write the status word
448  txBufferDesc[txBufferIndex].status = MACB_TX_WRAP |
450 
451  //Wrap around
452  txBufferIndex = 0;
453  }
454 
455  //Set the TSTART bit to initiate transmission
456  AVR32_MACB.ncr |= AVR32_MACB_NCR_TSTART_MASK;
457 
458  //Check whether the next buffer is available for writing
459  if(txBufferDesc[txBufferIndex].status & MACB_TX_USED)
460  {
461  //The transmitter can accept another packet
462  osSetEvent(&interface->nicTxEvent);
463  }
464 
465  //Successful processing
466  return NO_ERROR;
467 }
468 
469 
470 /**
471  * @brief Receive a packet
472  * @param[in] interface Underlying network interface
473  * @return Error code
474  **/
475 
477 {
478  static uint8_t temp[ETH_MAX_FRAME_SIZE];
479  error_t error;
480  uint_t i;
481  uint_t j;
482  uint_t sofIndex;
483  uint_t eofIndex;
484  size_t n;
485  size_t size;
486  size_t length;
487 
488  //Initialize SOF and EOF indices
489  sofIndex = UINT_MAX;
490  eofIndex = UINT_MAX;
491 
492  //Search for SOF and EOF flags
493  for(i = 0; i < AVR32_ETH_RX_BUFFER_COUNT; i++)
494  {
495  //Point to the current entry
496  j = rxBufferIndex + i;
497 
498  //Wrap around to the beginning of the buffer if necessary
501 
502  //No more entries to process?
503  if(!(rxBufferDesc[j].address & MACB_RX_OWNERSHIP))
504  {
505  //Stop processing
506  break;
507  }
508  //A valid SOF has been found?
509  if(rxBufferDesc[j].status & MACB_RX_SOF)
510  {
511  //Save the position of the SOF
512  sofIndex = i;
513  }
514  //A valid EOF has been found?
515  if((rxBufferDesc[j].status & MACB_RX_EOF) && sofIndex != UINT_MAX)
516  {
517  //Save the position of the EOF
518  eofIndex = i;
519  //Retrieve the length of the frame
520  size = rxBufferDesc[j].status & MACB_RX_LENGTH;
521  //Limit the number of data to read
522  size = MIN(size, ETH_MAX_FRAME_SIZE);
523  //Stop processing since we have reached the end of the frame
524  break;
525  }
526  }
527 
528  //Determine the number of entries to process
529  if(eofIndex != UINT_MAX)
530  j = eofIndex + 1;
531  else if(sofIndex != UINT_MAX)
532  j = sofIndex;
533  else
534  j = i;
535 
536  //Total number of bytes that have been copied from the receive buffer
537  length = 0;
538 
539  //Process incoming frame
540  for(i = 0; i < j; i++)
541  {
542  //Any data to copy from current buffer?
543  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
544  {
545  //Calculate the number of bytes to read at a time
546  n = MIN(size, AVR32_ETH_RX_BUFFER_SIZE);
547  //Copy data from receive buffer
548  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
549  //Update byte counters
550  length += n;
551  size -= n;
552  }
553 
554  //Mark the current buffer as free
555  rxBufferDesc[rxBufferIndex].address &= ~MACB_RX_OWNERSHIP;
556 
557  //Point to the following entry
558  rxBufferIndex++;
559 
560  //Wrap around to the beginning of the buffer if necessary
561  if(rxBufferIndex >= AVR32_ETH_RX_BUFFER_COUNT)
562  rxBufferIndex = 0;
563  }
564 
565  //Any packet to process?
566  if(length > 0)
567  {
568  //Pass the packet to the upper layer
569  nicProcessPacket(interface, temp, length);
570  //Valid packet received
571  error = NO_ERROR;
572  }
573  else
574  {
575  //No more data in the receive buffer
576  error = ERROR_BUFFER_EMPTY;
577  }
578 
579  //Return status code
580  return error;
581 }
582 
583 
584 /**
585  * @brief Configure MAC address filtering
586  * @param[in] interface Underlying network interface
587  * @return Error code
588  **/
589 
591 {
592  uint_t i;
593  uint_t k;
594  uint8_t *p;
595  uint32_t hashTable[2];
596  MacFilterEntry *entry;
597 
598  //Debug message
599  TRACE_DEBUG("Updating AVR32 hash table...\r\n");
600 
601  //Clear hash table
602  hashTable[0] = 0;
603  hashTable[1] = 0;
604 
605  //The MAC address filter contains the list of MAC addresses to accept
606  //when receiving an Ethernet frame
607  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
608  {
609  //Point to the current entry
610  entry = &interface->macAddrFilter[i];
611 
612  //Valid entry?
613  if(entry->refCount > 0)
614  {
615  //Point to the MAC address
616  p = entry->addr.b;
617 
618  //Apply the hash function
619  k = (p[0] >> 6) ^ p[0];
620  k ^= (p[1] >> 4) ^ (p[1] << 2);
621  k ^= (p[2] >> 2) ^ (p[2] << 4);
622  k ^= (p[3] >> 6) ^ p[3];
623  k ^= (p[4] >> 4) ^ (p[4] << 2);
624  k ^= (p[5] >> 2) ^ (p[5] << 4);
625 
626  //The hash value is reduced to a 6-bit index
627  k &= 0x3F;
628 
629  //Update hash table contents
630  hashTable[k / 32] |= (1 << (k % 32));
631  }
632  }
633 
634  //Write the hash table
635  AVR32_MACB.hrb = hashTable[0];
636  AVR32_MACB.hrt = hashTable[1];
637 
638  //Debug message
639  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", AVR32_MACB.hrb);
640  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", AVR32_MACB.hrt);
641 
642  //Successful processing
643  return NO_ERROR;
644 }
645 
646 
647 /**
648  * @brief Adjust MAC configuration parameters for proper operation
649  * @param[in] interface Underlying network interface
650  * @return Error code
651  **/
652 
654 {
655  uint32_t config;
656 
657  //Read network configuration register
658  config = AVR32_MACB.ncfgr;
659 
660  //10BASE-T or 100BASE-TX operation mode?
661  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
662  config |= AVR32_MACB_NCFGR_SPD_MASK;
663  else
664  config &= ~AVR32_MACB_NCFGR_SPD_MASK;
665 
666  //Half-duplex or full-duplex mode?
667  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
668  config |= AVR32_MACB_NCFGR_FD_MASK;
669  else
670  config &= ~AVR32_MACB_NCFGR_FD_MASK;
671 
672  //Write configuration value back to NCFGR register
673  AVR32_MACB.ncfgr = config;
674 
675  //Successful processing
676  return NO_ERROR;
677 }
678 
679 
680 /**
681  * @brief Write PHY register
682  * @param[in] phyAddr PHY address
683  * @param[in] regAddr Register address
684  * @param[in] data Register value
685  **/
686 
687 void avr32EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
688 {
689  uint32_t value;
690 
691  //Set up a write operation
693  //PHY address
694  value |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
695  //Register address
696  value |= (regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
697  //Register value
698  value |= data & AVR32_MACB_MAN_DATA_MASK;
699 
700  //Start a write operation
701  AVR32_MACB.man = value;
702  //Wait for the write to complete
703  while(!(AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK));
704 }
705 
706 
707 /**
708  * @brief Read PHY register
709  * @param[in] phyAddr PHY address
710  * @param[in] regAddr Register address
711  * @return Register value
712  **/
713 
714 uint16_t avr32EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
715 {
716  uint32_t value;
717 
718  //Set up a read operation
720  //PHY address
721  value |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
722  //Register address
723  value |= (regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
724 
725  //Start a read operation
726  AVR32_MACB.man = value;
727  //Wait for the read to complete
728  while(!(AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK));
729 
730  //Return PHY register contents
731  return AVR32_MACB.man & AVR32_MACB_MAN_DATA_MASK;
732 }
#define MACB_MAN_RW_10
#define MACB_RX_EOF
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
#define MACB_RX_WRAP
TCP/IP stack core.
Debugging facilities.
#define MACB_RX_LENGTH
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
void avr32EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define AVR32_ETH_IRQ_PRIORITY
#define MACB_RX_SOF
Generic error code.
Definition: error.h:43
void avr32EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void avr32EthTick(NetInterface *interface)
AVR32 Ethernet MAC timer handler.
#define MACB_MAN_CODE_10
#define txBuffer
void avr32EthInitGpio(NetInterface *interface)
const NicDriver avr32EthDriver
AVR32 Ethernet MAC driver.
#define MACB_TX_WRAP
#define MACB_RX_ADDRESS
AVR32 Ethernet MAC controller.
#define MACB_MAN_RW_01
#define AVR32_ETH_RX_BUFFER_SIZE
uint16_t avr32EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define MACB_TX_USED
#define MACB_TX_LENGTH
void avr32EthIrqWrapper(void)
void avr32EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
Transmit buffer descriptor.
#define AVR32_ETH_RX_BUFFER_COUNT
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define MACB_RMII_MASK
error_t avr32EthInit(NetInterface *interface)
AVR32 Ethernet MAC initialization.
error_t avr32EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Receive buffer descriptor.
error_t avr32EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define TRACE_INFO(...)
Definition: debug.h:86
#define MACB_RX_OWNERSHIP
uint16_t regAddr
bool_t avr32EthIrqHandler(void)
AVR32 Ethernet MAC interrupt service routine.
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define AVR32_ETH_TX_BUFFER_COUNT
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void avr32EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint8_t value[]
Definition: dtls_misc.h:141
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
error_t avr32EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint_t avr32EthReceivePacket(NetInterface *interface)
Receive a packet.
#define osExitIsr(flag)
#define MACB_MAN_SOF_01
#define osEnterIsr()
#define AVR32_ETH_TX_BUFFER_SIZE
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
MAC filter table entry.
Definition: ethernet.h:208
void avr32EthEventHandler(NetInterface *interface)
AVR32 Ethernet MAC event handler.
#define TRACE_DEBUG(...)
Definition: debug.h:98
#define MACB_TX_LAST