avr32_eth_driver.c
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1 /**
2  * @file avr32_eth_driver.c
3  * @brief AVR32 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include <avr32/io.h>
37 #include "interrupt.h"
38 #include "intc.h"
39 #include "core/net.h"
41 #include "debug.h"
42 
43 //Underlying network interface
44 static NetInterface *nicDriverInterface;
45 
46 //IAR EWARM compiler?
47 #if defined(__ICCARM__)
48 
49 //TX buffer
50 #pragma data_alignment = 4
52 //RX buffer
53 #pragma data_alignment = 4
55 //TX buffer descriptors
56 #pragma data_alignment = 8
57 static Avr32TxBufferDesc txBufferDesc[AVR32_ETH_TX_BUFFER_COUNT];
58 //RX buffer descriptors
59 #pragma data_alignment = 8
60 static Avr32RxBufferDesc rxBufferDesc[AVR32_ETH_RX_BUFFER_COUNT];
61 
62 //GCC compiler?
63 #else
64 
65 //TX buffer
67  __attribute__((aligned(4)));
68 //RX buffer
70  __attribute__((aligned(4)));
71 //TX buffer descriptors
73  __attribute__((aligned(8)));
74 //RX buffer descriptors
76  __attribute__((aligned(8)));
77 
78 #endif
79 
80 //TX buffer index
81 static uint_t txBufferIndex;
82 //RX buffer index
83 static uint_t rxBufferIndex;
84 
85 
86 /**
87  * @brief AVR32 Ethernet MAC driver
88  **/
89 
91 {
93  ETH_MTU,
104  TRUE,
105  TRUE,
106  TRUE,
107  FALSE
108 };
109 
110 
111 /**
112  * @brief AVR32 Ethernet MAC initialization
113  * @param[in] interface Underlying network interface
114  * @return Error code
115  **/
116 
118 {
119  error_t error;
120  volatile uint32_t status;
121 
122  //Debug message
123  TRACE_INFO("Initializing AVR32 Ethernet MAC...\r\n");
124 
125  //Save underlying network interface
126  nicDriverInterface = interface;
127 
128  //Disable transmit and receive circuits
129  AVR32_MACB.ncr = 0;
130 
131  //GPIO configuration
132  avr32EthInitGpio(interface);
133 
134  //Configure MDC clock speed
135  AVR32_MACB.ncfgr = AVR32_MACB_NCFGR_CLK_DIV64;
136  //Enable management port (MDC and MDIO)
137  AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;
138 
139  //Valid Ethernet PHY or switch driver?
140  if(interface->phyDriver != NULL)
141  {
142  //Ethernet PHY initialization
143  error = interface->phyDriver->init(interface);
144  }
145  else if(interface->switchDriver != NULL)
146  {
147  //Ethernet switch initialization
148  error = interface->switchDriver->init(interface);
149  }
150  else
151  {
152  //The interface is not properly configured
153  error = ERROR_FAILURE;
154  }
155 
156  //Any error to report?
157  if(error)
158  {
159  return error;
160  }
161 
162  //Set the MAC address of the station
163  AVR32_MACB.sa1b = interface->macAddr.b[0] |
164  (interface->macAddr.b[1] << 8) |
165  (interface->macAddr.b[2] << 16) |
166  (interface->macAddr.b[3] << 24);
167 
168  AVR32_MACB.sa1t = interface->macAddr.b[4] |
169  (interface->macAddr.b[5] << 8);
170 
171  //Initialize hash table
172  AVR32_MACB.hrb = 0;
173  AVR32_MACB.hrt = 0;
174 
175  //Configure the receive filter
176  AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_BIG_MASK | AVR32_MACB_NCFGR_UNI_MASK |
177  AVR32_MACB_NCFGR_MTI_MASK;
178 
179  //Initialize buffer descriptors
180  avr32EthInitBufferDesc(interface);
181 
182  //Clear transmit status register
183  AVR32_MACB.tsr = AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK | AVR32_MACB_TSR_BEX_MASK |
184  AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK | AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK;
185  //Clear receive status register
186  AVR32_MACB.rsr = AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK;
187 
188  //First disable all EMAC interrupts
189  AVR32_MACB.idr = 0xFFFFFFFF;
190  //Only the desired ones are enabled
191  AVR32_MACB.ier = AVR32_MACB_IER_ROVR_MASK | AVR32_MACB_IER_TCOMP_MASK | AVR32_MACB_IER_TXERR_MASK |
192  AVR32_MACB_IER_RLE_MASK | AVR32_MACB_IER_TUND_MASK | AVR32_MACB_IER_RXUBR_MASK | AVR32_MACB_IER_RCOMP_MASK;
193 
194  //Read EMAC ISR register to clear any pending interrupt
195  status = AVR32_MACB.isr;
196 
197  //Register interrupt handler
198  INTC_register_interrupt(avr32EthIrqWrapper, AVR32_MACB_IRQ, AVR32_ETH_IRQ_PRIORITY);
199 
200  //Enable the EMAC to transmit and receive data
201  AVR32_MACB.ncr |= AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
202 
203  //Accept any packets from the upper layer
204  osSetEvent(&interface->nicTxEvent);
205 
206  //Successful initialization
207  return NO_ERROR;
208 }
209 
210 
211 //EVK1105 evaluation board?
212 #if defined(USE_EVK1105)
213 
214 /**
215  * @brief GPIO configuration
216  * @param[in] interface Underlying network interface
217  **/
218 
219 void avr32EthInitGpio(NetInterface *interface)
220 {
221  //Assign RMII pins to peripheral A function
222  AVR32_GPIO.port[1].pmr0c = MACB_RMII_MASK;
223  AVR32_GPIO.port[1].pmr1c =MACB_RMII_MASK;
224 
225  //Disable the PIO from controlling the corresponding pins
226  AVR32_GPIO.port[1].gperc = MACB_RMII_MASK;
227 
228  //Select RMII operation mode
229  AVR32_MACB.usrio &= ~AVR32_MACB_USRIO_RMII_MASK;
230 }
231 
232 #endif
233 
234 
235 /**
236  * @brief Initialize buffer descriptors
237  * @param[in] interface Underlying network interface
238  **/
239 
241 {
242  uint_t i;
243  uint32_t address;
244 
245  //Initialize TX buffer descriptors
246  for(i = 0; i < AVR32_ETH_TX_BUFFER_COUNT; i++)
247  {
248  //Calculate the address of the current TX buffer
249  address = (uint32_t) txBuffer[i];
250  //Write the address to the descriptor entry
251  txBufferDesc[i].address = address;
252  //Initialize status field
253  txBufferDesc[i].status = MACB_TX_USED;
254  }
255 
256  //Mark the last descriptor entry with the wrap flag
257  txBufferDesc[i - 1].status |= MACB_TX_WRAP;
258  //Initialize TX buffer index
259  txBufferIndex = 0;
260 
261  //Initialize RX buffer descriptors
262  for(i = 0; i < AVR32_ETH_RX_BUFFER_COUNT; i++)
263  {
264  //Calculate the address of the current RX buffer
265  address = (uint32_t) rxBuffer[i];
266  //Write the address to the descriptor entry
267  rxBufferDesc[i].address = address & MACB_RX_ADDRESS;
268  //Clear status field
269  rxBufferDesc[i].status = 0;
270  }
271 
272  //Mark the last descriptor entry with the wrap flag
273  rxBufferDesc[i - 1].address |= MACB_RX_WRAP;
274  //Initialize RX buffer index
275  rxBufferIndex = 0;
276 
277  //Start location of the TX descriptor list
278  AVR32_MACB.tbqp = (uint32_t) txBufferDesc;
279  //Start location of the RX descriptor list
280  AVR32_MACB.rbqp = (uint32_t) rxBufferDesc;
281 }
282 
283 
284 /**
285  * @brief AVR32 Ethernet MAC timer handler
286  *
287  * This routine is periodically called by the TCP/IP stack to handle periodic
288  * operations such as polling the link state
289  *
290  * @param[in] interface Underlying network interface
291  **/
292 
293 void avr32EthTick(NetInterface *interface)
294 {
295  //Valid Ethernet PHY or switch driver?
296  if(interface->phyDriver != NULL)
297  {
298  //Handle periodic operations
299  interface->phyDriver->tick(interface);
300  }
301  else if(interface->switchDriver != NULL)
302  {
303  //Handle periodic operations
304  interface->switchDriver->tick(interface);
305  }
306  else
307  {
308  //Just for sanity
309  }
310 }
311 
312 
313 /**
314  * @brief Enable interrupts
315  * @param[in] interface Underlying network interface
316  **/
317 
319 {
320  //Enable Ethernet MAC interrupts
321  Enable_global_interrupt();
322 
323  //Valid Ethernet PHY or switch driver?
324  if(interface->phyDriver != NULL)
325  {
326  //Enable Ethernet PHY interrupts
327  interface->phyDriver->enableIrq(interface);
328  }
329  else if(interface->switchDriver != NULL)
330  {
331  //Enable Ethernet switch interrupts
332  interface->switchDriver->enableIrq(interface);
333  }
334  else
335  {
336  //Just for sanity
337  }
338 }
339 
340 
341 /**
342  * @brief Disable interrupts
343  * @param[in] interface Underlying network interface
344  **/
345 
347 {
348  //Disable Ethernet MAC interrupts
349  Disable_global_interrupt();
350 
351  //Valid Ethernet PHY or switch driver?
352  if(interface->phyDriver != NULL)
353  {
354  //Disable Ethernet PHY interrupts
355  interface->phyDriver->disableIrq(interface);
356  }
357  else if(interface->switchDriver != NULL)
358  {
359  //Disable Ethernet switch interrupts
360  interface->switchDriver->disableIrq(interface);
361  }
362  else
363  {
364  //Just for sanity
365  }
366 }
367 
368 
369 /**
370  * @brief AVR32 Ethernet MAC interrupt wrapper
371  **/
372 
373  __attribute__((naked)) void avr32EthIrqWrapper(void)
374 {
375  //Interrupt service routine prologue
376  osEnterIsr();
377 
378  //Call Ethernet MAC interrupt handler
380 
381  //Interrupt service routine epilogue
382  osExitIsr(flag);
383 }
384 
385 
386 /**
387  * @brief AVR32 Ethernet MAC interrupt service routine
388  * @return TRUE if a higher priority task must be woken. Else FALSE is returned
389  **/
390 
392 {
393  bool_t flag;
394  volatile uint32_t isr;
395  volatile uint32_t tsr;
396  volatile uint32_t rsr;
397 
398  //This flag will be set if a higher priority task must be woken
399  flag = FALSE;
400 
401  //Each time the software reads EMAC_ISR, it has to check the
402  //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
403  isr = AVR32_MACB.isr;
404  tsr = AVR32_MACB.tsr;
405  rsr = AVR32_MACB.rsr;
406 
407  //Packet transmitted?
408  if((tsr & (AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK |
409  AVR32_MACB_TSR_BEX_MASK | AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK |
410  AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK)) != 0)
411  {
412  //Only clear TSR flags that are currently set
413  AVR32_MACB.tsr = tsr;
414 
415  //Check whether the TX buffer is available for writing
416  if((txBufferDesc[txBufferIndex].status & MACB_TX_USED) != 0)
417  {
418  //Notify the TCP/IP stack that the transmitter is ready to send
419  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
420  }
421  }
422 
423  //Packet received?
424  if((rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK |
425  AVR32_MACB_RSR_BNA_MASK)) != 0)
426  {
427  //Set event flag
428  nicDriverInterface->nicEvent = TRUE;
429  //Notify the TCP/IP stack of the event
430  flag |= osSetEventFromIsr(&netEvent);
431  }
432 
433  //A higher priority task must be woken?
434  return flag;
435 }
436 
437 
438 /**
439  * @brief AVR32 Ethernet MAC event handler
440  * @param[in] interface Underlying network interface
441  **/
442 
444 {
445  error_t error;
446  uint32_t rsr;
447 
448  //Read receive status
449  rsr = AVR32_MACB.rsr;
450 
451  //Packet received?
452  if((rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK)) != 0)
453  {
454  //Only clear RSR flags that are currently set
455  AVR32_MACB.rsr = rsr;
456 
457  //Process all pending packets
458  do
459  {
460  //Read incoming packet
461  error = avr32EthReceivePacket(interface);
462 
463  //No more data in the receive buffer?
464  } while(error != ERROR_BUFFER_EMPTY);
465  }
466 }
467 
468 
469 /**
470  * @brief Send a packet
471  * @param[in] interface Underlying network interface
472  * @param[in] buffer Multi-part buffer containing the data to send
473  * @param[in] offset Offset to the first data byte
474  * @param[in] ancillary Additional options passed to the stack along with
475  * the packet
476  * @return Error code
477  **/
478 
480  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
481 {
482  size_t length;
483 
484  //Retrieve the length of the packet
485  length = netBufferGetLength(buffer) - offset;
486 
487  //Check the frame length
489  {
490  //The transmitter can accept another packet
491  osSetEvent(&interface->nicTxEvent);
492  //Report an error
493  return ERROR_INVALID_LENGTH;
494  }
495 
496  //Make sure the current buffer is available for writing
497  if((txBufferDesc[txBufferIndex].status & MACB_TX_USED) == 0)
498  {
499  return ERROR_FAILURE;
500  }
501 
502  //Copy user data to the transmit buffer
503  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
504 
505  //Set the necessary flags in the descriptor entry
506  if(txBufferIndex < (AVR32_ETH_TX_BUFFER_COUNT - 1))
507  {
508  //Write the status word
509  txBufferDesc[txBufferIndex].status = MACB_TX_LAST |
511 
512  //Point to the next buffer
513  txBufferIndex++;
514  }
515  else
516  {
517  //Write the status word
518  txBufferDesc[txBufferIndex].status = MACB_TX_WRAP | MACB_TX_LAST |
520 
521  //Wrap around
522  txBufferIndex = 0;
523  }
524 
525  //Set the TSTART bit to initiate transmission
526  AVR32_MACB.ncr |= AVR32_MACB_NCR_TSTART_MASK;
527 
528  //Check whether the next buffer is available for writing
529  if((txBufferDesc[txBufferIndex].status & MACB_TX_USED) != 0)
530  {
531  //The transmitter can accept another packet
532  osSetEvent(&interface->nicTxEvent);
533  }
534 
535  //Successful processing
536  return NO_ERROR;
537 }
538 
539 
540 /**
541  * @brief Receive a packet
542  * @param[in] interface Underlying network interface
543  * @return Error code
544  **/
545 
547 {
548  static uint8_t temp[ETH_MAX_FRAME_SIZE];
549  error_t error;
550  uint_t i;
551  uint_t j;
552  uint_t sofIndex;
553  uint_t eofIndex;
554  size_t n;
555  size_t size;
556  size_t length;
557 
558  //Initialize SOF and EOF indices
559  sofIndex = UINT_MAX;
560  eofIndex = UINT_MAX;
561 
562  //Search for SOF and EOF flags
563  for(i = 0; i < AVR32_ETH_RX_BUFFER_COUNT; i++)
564  {
565  //Point to the current entry
566  j = rxBufferIndex + i;
567 
568  //Wrap around to the beginning of the buffer if necessary
570  {
572  }
573 
574  //No more entries to process?
575  if((rxBufferDesc[j].address & MACB_RX_OWNERSHIP) == 0)
576  {
577  //Stop processing
578  break;
579  }
580 
581  //A valid SOF has been found?
582  if((rxBufferDesc[j].status & MACB_RX_SOF) != 0)
583  {
584  //Save the position of the SOF
585  sofIndex = i;
586  }
587 
588  //A valid EOF has been found?
589  if((rxBufferDesc[j].status & MACB_RX_EOF) != 0 && sofIndex != UINT_MAX)
590  {
591  //Save the position of the EOF
592  eofIndex = i;
593  //Retrieve the length of the frame
594  size = rxBufferDesc[j].status & MACB_RX_LENGTH;
595  //Limit the number of data to read
596  size = MIN(size, ETH_MAX_FRAME_SIZE);
597  //Stop processing since we have reached the end of the frame
598  break;
599  }
600  }
601 
602  //Determine the number of entries to process
603  if(eofIndex != UINT_MAX)
604  {
605  j = eofIndex + 1;
606  }
607  else if(sofIndex != UINT_MAX)
608  {
609  j = sofIndex;
610  }
611  else
612  {
613  j = i;
614  }
615 
616  //Total number of bytes that have been copied from the receive buffer
617  length = 0;
618 
619  //Process incoming frame
620  for(i = 0; i < j; i++)
621  {
622  //Any data to copy from current buffer?
623  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
624  {
625  //Calculate the number of bytes to read at a time
626  n = MIN(size, AVR32_ETH_RX_BUFFER_SIZE);
627  //Copy data from receive buffer
628  osMemcpy(temp + length, rxBuffer[rxBufferIndex], n);
629  //Update byte counters
630  length += n;
631  size -= n;
632  }
633 
634  //Mark the current buffer as free
635  rxBufferDesc[rxBufferIndex].address &= ~MACB_RX_OWNERSHIP;
636 
637  //Point to the following entry
638  rxBufferIndex++;
639 
640  //Wrap around to the beginning of the buffer if necessary
641  if(rxBufferIndex >= AVR32_ETH_RX_BUFFER_COUNT)
642  {
643  rxBufferIndex = 0;
644  }
645  }
646 
647  //Any packet to process?
648  if(length > 0)
649  {
650  NetRxAncillary ancillary;
651 
652  //Additional options can be passed to the stack along with the packet
653  ancillary = NET_DEFAULT_RX_ANCILLARY;
654 
655  //Pass the packet to the upper layer
656  nicProcessPacket(interface, temp, length, &ancillary);
657  //Valid packet received
658  error = NO_ERROR;
659  }
660  else
661  {
662  //No more data in the receive buffer
663  error = ERROR_BUFFER_EMPTY;
664  }
665 
666  //Return status code
667  return error;
668 }
669 
670 
671 /**
672  * @brief Configure MAC address filtering
673  * @param[in] interface Underlying network interface
674  * @return Error code
675  **/
676 
678 {
679  uint_t i;
680  uint_t k;
681  uint8_t *p;
682  uint32_t hashTable[2];
683  MacFilterEntry *entry;
684 
685  //Debug message
686  TRACE_DEBUG("Updating MAC filter...\r\n");
687 
688  //Set the MAC address of the station
689  AVR32_MACB.sa1b = interface->macAddr.b[0] |
690  (interface->macAddr.b[1] << 8) |
691  (interface->macAddr.b[2] << 16) |
692  (interface->macAddr.b[3] << 24);
693 
694  AVR32_MACB.sa1t = interface->macAddr.b[4] |
695  (interface->macAddr.b[5] << 8);
696 
697  //Clear hash table
698  hashTable[0] = 0;
699  hashTable[1] = 0;
700 
701  //The MAC address filter contains the list of MAC addresses to accept
702  //when receiving an Ethernet frame
703  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
704  {
705  //Point to the current entry
706  entry = &interface->macAddrFilter[i];
707 
708  //Valid entry?
709  if(entry->refCount > 0)
710  {
711  //Point to the MAC address
712  p = entry->addr.b;
713 
714  //Apply the hash function
715  k = (p[0] >> 6) ^ p[0];
716  k ^= (p[1] >> 4) ^ (p[1] << 2);
717  k ^= (p[2] >> 2) ^ (p[2] << 4);
718  k ^= (p[3] >> 6) ^ p[3];
719  k ^= (p[4] >> 4) ^ (p[4] << 2);
720  k ^= (p[5] >> 2) ^ (p[5] << 4);
721 
722  //The hash value is reduced to a 6-bit index
723  k &= 0x3F;
724 
725  //Update hash table contents
726  hashTable[k / 32] |= (1 << (k % 32));
727  }
728  }
729 
730  //Write the hash table
731  AVR32_MACB.hrb = hashTable[0];
732  AVR32_MACB.hrt = hashTable[1];
733 
734  //Debug message
735  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", AVR32_MACB.hrb);
736  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", AVR32_MACB.hrt);
737 
738  //Successful processing
739  return NO_ERROR;
740 }
741 
742 
743 /**
744  * @brief Adjust MAC configuration parameters for proper operation
745  * @param[in] interface Underlying network interface
746  * @return Error code
747  **/
748 
750 {
751  uint32_t config;
752 
753  //Read network configuration register
754  config = AVR32_MACB.ncfgr;
755 
756  //10BASE-T or 100BASE-TX operation mode?
757  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
758  {
759  config |= AVR32_MACB_NCFGR_SPD_MASK;
760  }
761  else
762  {
763  config &= ~AVR32_MACB_NCFGR_SPD_MASK;
764  }
765 
766  //Half-duplex or full-duplex mode?
767  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
768  {
769  config |= AVR32_MACB_NCFGR_FD_MASK;
770  }
771  else
772  {
773  config &= ~AVR32_MACB_NCFGR_FD_MASK;
774  }
775 
776  //Write configuration value back to NCFGR register
777  AVR32_MACB.ncfgr = config;
778 
779  //Successful processing
780  return NO_ERROR;
781 }
782 
783 
784 /**
785  * @brief Write PHY register
786  * @param[in] opcode Access type (2 bits)
787  * @param[in] phyAddr PHY address (5 bits)
788  * @param[in] regAddr Register address (5 bits)
789  * @param[in] data Register value
790  **/
791 
792 void avr32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
793  uint8_t regAddr, uint16_t data)
794 {
795  uint32_t temp;
796 
797  //Valid opcode?
798  if(opcode == SMI_OPCODE_WRITE)
799  {
800  //Set up a write operation
802  //PHY address
803  temp |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
804  //Register address
805  temp |= (regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
806  //Register value
807  temp |= data & AVR32_MACB_MAN_DATA_MASK;
808 
809  //Start a write operation
810  AVR32_MACB.man = temp;
811  //Wait for the write to complete
812  while((AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK) == 0)
813  {
814  }
815  }
816  else
817  {
818  //The MAC peripheral only supports standard Clause 22 opcodes
819  }
820 }
821 
822 
823 /**
824  * @brief Read PHY register
825  * @param[in] opcode Access type (2 bits)
826  * @param[in] phyAddr PHY address (5 bits)
827  * @param[in] regAddr Register address (5 bits)
828  * @return Register value
829  **/
830 
831 uint16_t avr32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
832  uint8_t regAddr)
833 {
834  uint16_t data;
835  uint32_t temp;
836 
837  //Valid opcode?
838  if(opcode == SMI_OPCODE_READ)
839  {
840  //Set up a read operation
842  //PHY address
843  temp |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
844  //Register address
845  temp |= (regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
846 
847  //Start a read operation
848  AVR32_MACB.man = temp;
849  //Wait for the read to complete
850  while((AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK) == 0)
851  {
852  }
853 
854  //Get register value
855  data = AVR32_MACB.man & AVR32_MACB_MAN_DATA_MASK;
856  }
857  else
858  {
859  //The MAC peripheral only supports standard Clause 22 opcodes
860  data = 0;
861  }
862 
863  //Return the value of the PHY register
864  return data;
865 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
void avr32EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define AVR32_ETH_TX_BUFFER_COUNT
#define MACB_RMII_MASK
#define netEvent
Definition: net_legacy.h:267
uint8_t data[]
Definition: ethernet.h:209
#define AVR32_ETH_RX_BUFFER_COUNT
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define MACB_TX_LENGTH
#define MACB_MAN_SOF_01
uint8_t p
Definition: ndp.h:298
void avr32EthDisableIrq(NetInterface *interface)
Disable interrupts.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:103
uint_t avr32EthReceivePacket(NetInterface *interface)
Receive a packet.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
bool_t avr32EthIrqHandler(void)
AVR32 Ethernet MAC interrupt service routine.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define osExitIsr(flag)
#define MACB_RX_LENGTH
#define SMI_OPCODE_WRITE
Definition: nic.h:65
AVR32 Ethernet MAC driver.
#define MACB_RX_WRAP
#define MACB_RX_SOF
#define AVR32_ETH_IRQ_PRIORITY
Transmit buffer descriptor.
#define FALSE
Definition: os_port.h:46
#define osMemcpy(dest, src, length)
Definition: os_port.h:134
#define MACB_RX_OWNERSHIP
error_t
Error codes.
Definition: error.h:42
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
Receive buffer descriptor.
#define txBuffer
error_t avr32EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:248
#define MACB_RX_EOF
void avr32EthEnableIrq(NetInterface *interface)
Enable interrupts.
void avr32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define NetTxAncillary
Definition: net_misc.h:36
#define SMI_OPCODE_READ
Definition: nic.h:66
#define TRACE_INFO(...)
Definition: debug.h:95
#define AVR32_ETH_TX_BUFFER_SIZE
#define MACB_MAN_CODE_10
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
void avr32EthEventHandler(NetInterface *interface)
AVR32 Ethernet MAC event handler.
void avr32EthInitGpio(NetInterface *interface)
error_t avr32EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
void avr32EthTick(NetInterface *interface)
AVR32 Ethernet MAC timer handler.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define MACB_TX_WRAP
uint16_t regAddr
#define MACB_RX_ADDRESS
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
MAC filter table entry.
Definition: ethernet.h:246
#define osEnterIsr()
uint16_t avr32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define MACB_MAN_RW_01
#define MACB_TX_LAST
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MACB_MAN_RW_10
error_t avr32EthInit(NetInterface *interface)
AVR32 Ethernet MAC initialization.
#define AVR32_ETH_RX_BUFFER_SIZE
const NicDriver avr32EthDriver
AVR32 Ethernet MAC driver.
void avr32EthIrqWrapper(void)
error_t avr32EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
NIC driver.
Definition: nic.h:257
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define MACB_TX_USED
Ethernet interface.
Definition: nic.h:82