avr32_eth_driver.c
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1 /**
2  * @file avr32_eth_driver.c
3  * @brief AVR32 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include <avr32/io.h>
37 #include "interrupt.h"
38 #include "intc.h"
39 #include "core/net.h"
41 #include "debug.h"
42 
43 //Underlying network interface
44 static NetInterface *nicDriverInterface;
45 
46 //IAR EWARM compiler?
47 #if defined(__ICCARM__)
48 
49 //TX buffer
50 #pragma data_alignment = 4
52 //RX buffer
53 #pragma data_alignment = 4
55 //TX buffer descriptors
56 #pragma data_alignment = 8
57 static Avr32TxBufferDesc txBufferDesc[AVR32_ETH_TX_BUFFER_COUNT];
58 //RX buffer descriptors
59 #pragma data_alignment = 8
60 static Avr32RxBufferDesc rxBufferDesc[AVR32_ETH_RX_BUFFER_COUNT];
61 
62 //GCC compiler?
63 #else
64 
65 //TX buffer
67  __attribute__((aligned(4)));
68 //RX buffer
70  __attribute__((aligned(4)));
71 //TX buffer descriptors
73  __attribute__((aligned(8)));
74 //RX buffer descriptors
76  __attribute__((aligned(8)));
77 
78 #endif
79 
80 //TX buffer index
81 static uint_t txBufferIndex;
82 //RX buffer index
83 static uint_t rxBufferIndex;
84 
85 
86 /**
87  * @brief AVR32 Ethernet MAC driver
88  **/
89 
91 {
93  ETH_MTU,
104  TRUE,
105  TRUE,
106  TRUE,
107  FALSE
108 };
109 
110 
111 /**
112  * @brief AVR32 Ethernet MAC initialization
113  * @param[in] interface Underlying network interface
114  * @return Error code
115  **/
116 
118 {
119  error_t error;
120  volatile uint32_t status;
121 
122  //Debug message
123  TRACE_INFO("Initializing AVR32 Ethernet MAC...\r\n");
124 
125  //Save underlying network interface
126  nicDriverInterface = interface;
127 
128  //Disable transmit and receive circuits
129  AVR32_MACB.ncr = 0;
130 
131  //GPIO configuration
132  avr32EthInitGpio(interface);
133 
134  //Configure MDC clock speed
135  AVR32_MACB.ncfgr = AVR32_MACB_NCFGR_CLK_DIV64;
136  //Enable management port (MDC and MDIO)
137  AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;
138 
139  //PHY transceiver initialization
140  error = interface->phyDriver->init(interface);
141  //Failed to initialize PHY transceiver?
142  if(error)
143  return error;
144 
145  //Set the MAC address of the station
146  AVR32_MACB.sa1b = interface->macAddr.b[0] |
147  (interface->macAddr.b[1] << 8) |
148  (interface->macAddr.b[2] << 16) |
149  (interface->macAddr.b[3] << 24);
150 
151  AVR32_MACB.sa1t = interface->macAddr.b[4] |
152  (interface->macAddr.b[5] << 8);
153 
154  //Initialize hash table
155  AVR32_MACB.hrb = 0;
156  AVR32_MACB.hrt = 0;
157 
158  //Configure the receive filter
159  AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_BIG_MASK | AVR32_MACB_NCFGR_UNI_MASK |
160  AVR32_MACB_NCFGR_MTI_MASK;
161 
162  //Initialize buffer descriptors
163  avr32EthInitBufferDesc(interface);
164 
165  //Clear transmit status register
166  AVR32_MACB.tsr = AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK | AVR32_MACB_TSR_BEX_MASK |
167  AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK | AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK;
168  //Clear receive status register
169  AVR32_MACB.rsr = AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK;
170 
171  //First disable all EMAC interrupts
172  AVR32_MACB.idr = 0xFFFFFFFF;
173  //Only the desired ones are enabled
174  AVR32_MACB.ier = AVR32_MACB_IER_ROVR_MASK | AVR32_MACB_IER_TCOMP_MASK | AVR32_MACB_IER_TXERR_MASK |
175  AVR32_MACB_IER_RLE_MASK | AVR32_MACB_IER_TUND_MASK | AVR32_MACB_IER_RXUBR_MASK | AVR32_MACB_IER_RCOMP_MASK;
176 
177  //Read EMAC ISR register to clear any pending interrupt
178  status = AVR32_MACB.isr;
179 
180  //Register interrupt handler
181  INTC_register_interrupt(avr32EthIrqWrapper, AVR32_MACB_IRQ, AVR32_ETH_IRQ_PRIORITY);
182 
183  //Enable the EMAC to transmit and receive data
184  AVR32_MACB.ncr |= AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
185 
186  //Accept any packets from the upper layer
187  osSetEvent(&interface->nicTxEvent);
188 
189  //Successful initialization
190  return NO_ERROR;
191 }
192 
193 
194 //EVK1105 evaluation board?
195 #if defined(USE_EVK1105)
196 
197 /**
198  * @brief GPIO configuration
199  * @param[in] interface Underlying network interface
200  **/
201 
202 void avr32EthInitGpio(NetInterface *interface)
203 {
204  //Assign RMII pins to peripheral A function
205  AVR32_GPIO.port[1].pmr0c = MACB_RMII_MASK;
206  AVR32_GPIO.port[1].pmr1c =MACB_RMII_MASK;
207 
208  //Disable the PIO from controlling the corresponding pins
209  AVR32_GPIO.port[1].gperc = MACB_RMII_MASK;
210 
211  //Select RMII operation mode
212  AVR32_MACB.usrio &= ~AVR32_MACB_USRIO_RMII_MASK;
213 }
214 
215 #endif
216 
217 
218 /**
219  * @brief Initialize buffer descriptors
220  * @param[in] interface Underlying network interface
221  **/
222 
224 {
225  uint_t i;
226  uint32_t address;
227 
228  //Initialize TX buffer descriptors
229  for(i = 0; i < AVR32_ETH_TX_BUFFER_COUNT; i++)
230  {
231  //Calculate the address of the current TX buffer
232  address = (uint32_t) txBuffer[i];
233  //Write the address to the descriptor entry
234  txBufferDesc[i].address = address;
235  //Initialize status field
236  txBufferDesc[i].status = MACB_TX_USED;
237  }
238 
239  //Mark the last descriptor entry with the wrap flag
240  txBufferDesc[i - 1].status |= MACB_TX_WRAP;
241  //Initialize TX buffer index
242  txBufferIndex = 0;
243 
244  //Initialize RX buffer descriptors
245  for(i = 0; i < AVR32_ETH_RX_BUFFER_COUNT; i++)
246  {
247  //Calculate the address of the current RX buffer
248  address = (uint32_t) rxBuffer[i];
249  //Write the address to the descriptor entry
250  rxBufferDesc[i].address = address & MACB_RX_ADDRESS;
251  //Clear status field
252  rxBufferDesc[i].status = 0;
253  }
254 
255  //Mark the last descriptor entry with the wrap flag
256  rxBufferDesc[i - 1].address |= MACB_RX_WRAP;
257  //Initialize RX buffer index
258  rxBufferIndex = 0;
259 
260  //Start location of the TX descriptor list
261  AVR32_MACB.tbqp = (uint32_t) txBufferDesc;
262  //Start location of the RX descriptor list
263  AVR32_MACB.rbqp = (uint32_t) rxBufferDesc;
264 }
265 
266 
267 /**
268  * @brief AVR32 Ethernet MAC timer handler
269  *
270  * This routine is periodically called by the TCP/IP stack to
271  * handle periodic operations such as polling the link state
272  *
273  * @param[in] interface Underlying network interface
274  **/
275 
276 void avr32EthTick(NetInterface *interface)
277 {
278  //Handle periodic operations
279  interface->phyDriver->tick(interface);
280 }
281 
282 
283 /**
284  * @brief Enable interrupts
285  * @param[in] interface Underlying network interface
286  **/
287 
289 {
290  //Enable Ethernet MAC interrupts
291  Enable_global_interrupt();
292  //Enable Ethernet PHY interrupts
293  interface->phyDriver->enableIrq(interface);
294 }
295 
296 
297 /**
298  * @brief Disable interrupts
299  * @param[in] interface Underlying network interface
300  **/
301 
303 {
304  //Disable Ethernet MAC interrupts
305  Disable_global_interrupt();
306  //Disable Ethernet PHY interrupts
307  interface->phyDriver->disableIrq(interface);
308 }
309 
310 
311 /**
312  * @brief AVR32 Ethernet MAC interrupt wrapper
313  **/
314 
316 {
317  //Interrupt service routine prologue
318  osEnterIsr();
319 
320  //Call Ethernet MAC interrupt handler
322 
323  //Interrupt service routine epilogue
324  osExitIsr(flag);
325 }
326 
327 
328 /**
329  * @brief AVR32 Ethernet MAC interrupt service routine
330  * @return TRUE if a higher priority task must be woken. Else FALSE is returned
331  **/
332 
334 {
335  bool_t flag;
336  volatile uint32_t isr;
337  volatile uint32_t tsr;
338  volatile uint32_t rsr;
339 
340  //This flag will be set if a higher priority task must be woken
341  flag = FALSE;
342 
343  //Each time the software reads EMAC_ISR, it has to check the
344  //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
345  isr = AVR32_MACB.isr;
346  tsr = AVR32_MACB.tsr;
347  rsr = AVR32_MACB.rsr;
348 
349  //A packet has been transmitted?
350  if(tsr & (AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK | AVR32_MACB_TSR_BEX_MASK |
351  AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK | AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK))
352  {
353  //Only clear TSR flags that are currently set
354  AVR32_MACB.tsr = tsr;
355 
356  //Check whether the TX buffer is available for writing
357  if(txBufferDesc[txBufferIndex].status & MACB_TX_USED)
358  {
359  //Notify the TCP/IP stack that the transmitter is ready to send
360  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
361  }
362  }
363 
364  //A packet has been received?
365  if(rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK))
366  {
367  //Set event flag
368  nicDriverInterface->nicEvent = TRUE;
369  //Notify the TCP/IP stack of the event
370  flag |= osSetEventFromIsr(&netEvent);
371  }
372 
373  //A higher priority task must be woken?
374  return flag;
375 }
376 
377 
378 /**
379  * @brief AVR32 Ethernet MAC event handler
380  * @param[in] interface Underlying network interface
381  **/
382 
384 {
385  error_t error;
386  uint32_t rsr;
387 
388  //Read receive status
389  rsr = AVR32_MACB.rsr;
390 
391  //Packet received?
392  if(rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK))
393  {
394  //Only clear RSR flags that are currently set
395  AVR32_MACB.rsr = rsr;
396 
397  //Process all pending packets
398  do
399  {
400  //Read incoming packet
401  error = avr32EthReceivePacket(interface);
402 
403  //No more data in the receive buffer?
404  } while(error != ERROR_BUFFER_EMPTY);
405  }
406 }
407 
408 
409 /**
410  * @brief Send a packet
411  * @param[in] interface Underlying network interface
412  * @param[in] buffer Multi-part buffer containing the data to send
413  * @param[in] offset Offset to the first data byte
414  * @return Error code
415  **/
416 
418  const NetBuffer *buffer, size_t offset)
419 {
420  size_t length;
421 
422  //Retrieve the length of the packet
423  length = netBufferGetLength(buffer) - offset;
424 
425  //Check the frame length
427  {
428  //The transmitter can accept another packet
429  osSetEvent(&interface->nicTxEvent);
430  //Report an error
431  return ERROR_INVALID_LENGTH;
432  }
433 
434  //Make sure the current buffer is available for writing
435  if(!(txBufferDesc[txBufferIndex].status & MACB_TX_USED))
436  return ERROR_FAILURE;
437 
438  //Copy user data to the transmit buffer
439  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
440 
441  //Set the necessary flags in the descriptor entry
442  if(txBufferIndex < (AVR32_ETH_TX_BUFFER_COUNT - 1))
443  {
444  //Write the status word
445  txBufferDesc[txBufferIndex].status =
447 
448  //Point to the next buffer
449  txBufferIndex++;
450  }
451  else
452  {
453  //Write the status word
454  txBufferDesc[txBufferIndex].status = MACB_TX_WRAP |
456 
457  //Wrap around
458  txBufferIndex = 0;
459  }
460 
461  //Set the TSTART bit to initiate transmission
462  AVR32_MACB.ncr |= AVR32_MACB_NCR_TSTART_MASK;
463 
464  //Check whether the next buffer is available for writing
465  if(txBufferDesc[txBufferIndex].status & MACB_TX_USED)
466  {
467  //The transmitter can accept another packet
468  osSetEvent(&interface->nicTxEvent);
469  }
470 
471  //Successful processing
472  return NO_ERROR;
473 }
474 
475 
476 /**
477  * @brief Receive a packet
478  * @param[in] interface Underlying network interface
479  * @return Error code
480  **/
481 
483 {
484  static uint8_t temp[ETH_MAX_FRAME_SIZE];
485  error_t error;
486  uint_t i;
487  uint_t j;
488  uint_t sofIndex;
489  uint_t eofIndex;
490  size_t n;
491  size_t size;
492  size_t length;
493 
494  //Initialize SOF and EOF indices
495  sofIndex = UINT_MAX;
496  eofIndex = UINT_MAX;
497 
498  //Search for SOF and EOF flags
499  for(i = 0; i < AVR32_ETH_RX_BUFFER_COUNT; i++)
500  {
501  //Point to the current entry
502  j = rxBufferIndex + i;
503 
504  //Wrap around to the beginning of the buffer if necessary
507 
508  //No more entries to process?
509  if(!(rxBufferDesc[j].address & MACB_RX_OWNERSHIP))
510  {
511  //Stop processing
512  break;
513  }
514  //A valid SOF has been found?
515  if(rxBufferDesc[j].status & MACB_RX_SOF)
516  {
517  //Save the position of the SOF
518  sofIndex = i;
519  }
520  //A valid EOF has been found?
521  if((rxBufferDesc[j].status & MACB_RX_EOF) && sofIndex != UINT_MAX)
522  {
523  //Save the position of the EOF
524  eofIndex = i;
525  //Retrieve the length of the frame
526  size = rxBufferDesc[j].status & MACB_RX_LENGTH;
527  //Limit the number of data to read
528  size = MIN(size, ETH_MAX_FRAME_SIZE);
529  //Stop processing since we have reached the end of the frame
530  break;
531  }
532  }
533 
534  //Determine the number of entries to process
535  if(eofIndex != UINT_MAX)
536  j = eofIndex + 1;
537  else if(sofIndex != UINT_MAX)
538  j = sofIndex;
539  else
540  j = i;
541 
542  //Total number of bytes that have been copied from the receive buffer
543  length = 0;
544 
545  //Process incoming frame
546  for(i = 0; i < j; i++)
547  {
548  //Any data to copy from current buffer?
549  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
550  {
551  //Calculate the number of bytes to read at a time
552  n = MIN(size, AVR32_ETH_RX_BUFFER_SIZE);
553  //Copy data from receive buffer
554  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
555  //Update byte counters
556  length += n;
557  size -= n;
558  }
559 
560  //Mark the current buffer as free
561  rxBufferDesc[rxBufferIndex].address &= ~MACB_RX_OWNERSHIP;
562 
563  //Point to the following entry
564  rxBufferIndex++;
565 
566  //Wrap around to the beginning of the buffer if necessary
567  if(rxBufferIndex >= AVR32_ETH_RX_BUFFER_COUNT)
568  rxBufferIndex = 0;
569  }
570 
571  //Any packet to process?
572  if(length > 0)
573  {
574  //Pass the packet to the upper layer
575  nicProcessPacket(interface, temp, length);
576  //Valid packet received
577  error = NO_ERROR;
578  }
579  else
580  {
581  //No more data in the receive buffer
582  error = ERROR_BUFFER_EMPTY;
583  }
584 
585  //Return status code
586  return error;
587 }
588 
589 
590 /**
591  * @brief Configure MAC address filtering
592  * @param[in] interface Underlying network interface
593  * @return Error code
594  **/
595 
597 {
598  uint_t i;
599  uint_t k;
600  uint8_t *p;
601  uint32_t hashTable[2];
602  MacFilterEntry *entry;
603 
604  //Debug message
605  TRACE_DEBUG("Updating MAC filter...\r\n");
606 
607  //Set the MAC address of the station
608  AVR32_MACB.sa1b = interface->macAddr.b[0] |
609  (interface->macAddr.b[1] << 8) |
610  (interface->macAddr.b[2] << 16) |
611  (interface->macAddr.b[3] << 24);
612 
613  AVR32_MACB.sa1t = interface->macAddr.b[4] |
614  (interface->macAddr.b[5] << 8);
615 
616  //Clear hash table
617  hashTable[0] = 0;
618  hashTable[1] = 0;
619 
620  //The MAC address filter contains the list of MAC addresses to accept
621  //when receiving an Ethernet frame
622  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
623  {
624  //Point to the current entry
625  entry = &interface->macAddrFilter[i];
626 
627  //Valid entry?
628  if(entry->refCount > 0)
629  {
630  //Point to the MAC address
631  p = entry->addr.b;
632 
633  //Apply the hash function
634  k = (p[0] >> 6) ^ p[0];
635  k ^= (p[1] >> 4) ^ (p[1] << 2);
636  k ^= (p[2] >> 2) ^ (p[2] << 4);
637  k ^= (p[3] >> 6) ^ p[3];
638  k ^= (p[4] >> 4) ^ (p[4] << 2);
639  k ^= (p[5] >> 2) ^ (p[5] << 4);
640 
641  //The hash value is reduced to a 6-bit index
642  k &= 0x3F;
643 
644  //Update hash table contents
645  hashTable[k / 32] |= (1 << (k % 32));
646  }
647  }
648 
649  //Write the hash table
650  AVR32_MACB.hrb = hashTable[0];
651  AVR32_MACB.hrt = hashTable[1];
652 
653  //Debug message
654  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", AVR32_MACB.hrb);
655  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", AVR32_MACB.hrt);
656 
657  //Successful processing
658  return NO_ERROR;
659 }
660 
661 
662 /**
663  * @brief Adjust MAC configuration parameters for proper operation
664  * @param[in] interface Underlying network interface
665  * @return Error code
666  **/
667 
669 {
670  uint32_t config;
671 
672  //Read network configuration register
673  config = AVR32_MACB.ncfgr;
674 
675  //10BASE-T or 100BASE-TX operation mode?
676  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
677  config |= AVR32_MACB_NCFGR_SPD_MASK;
678  else
679  config &= ~AVR32_MACB_NCFGR_SPD_MASK;
680 
681  //Half-duplex or full-duplex mode?
682  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
683  config |= AVR32_MACB_NCFGR_FD_MASK;
684  else
685  config &= ~AVR32_MACB_NCFGR_FD_MASK;
686 
687  //Write configuration value back to NCFGR register
688  AVR32_MACB.ncfgr = config;
689 
690  //Successful processing
691  return NO_ERROR;
692 }
693 
694 
695 /**
696  * @brief Write PHY register
697  * @param[in] opcode Access type (2 bits)
698  * @param[in] phyAddr PHY address (5 bits)
699  * @param[in] regAddr Register address (5 bits)
700  * @param[in] data Register value
701  **/
702 
703 void avr32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
704  uint8_t regAddr, uint16_t data)
705 {
706  uint32_t temp;
707 
708  //Valid opcode?
709  if(opcode == SMI_OPCODE_WRITE)
710  {
711  //Set up a write operation
713  //PHY address
714  temp |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
715  //Register address
716  temp |= (regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
717  //Register value
718  temp |= data & AVR32_MACB_MAN_DATA_MASK;
719 
720  //Start a write operation
721  AVR32_MACB.man = temp;
722  //Wait for the write to complete
723  while(!(AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK))
724  {
725  }
726  }
727  else
728  {
729  //The MAC peripheral only supports standard Clause 22 opcodes
730  }
731 }
732 
733 
734 /**
735  * @brief Read PHY register
736  * @param[in] opcode Access type (2 bits)
737  * @param[in] phyAddr PHY address (5 bits)
738  * @param[in] regAddr Register address (5 bits)
739  * @return Register value
740  **/
741 
742 uint16_t avr32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
743  uint8_t regAddr)
744 {
745  uint16_t data;
746  uint32_t temp;
747 
748  //Valid opcode?
749  if(opcode == SMI_OPCODE_READ)
750  {
751  //Set up a read operation
753  //PHY address
754  temp |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
755  //Register address
756  temp |= (regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
757 
758  //Start a read operation
759  AVR32_MACB.man = temp;
760  //Wait for the read to complete
761  while(!(AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK))
762  {
763  }
764 
765  //Get register value
766  data = AVR32_MACB.man & AVR32_MACB_MAN_DATA_MASK;
767  }
768  else
769  {
770  //The MAC peripheral only supports standard Clause 22 opcodes
771  data = 0;
772  }
773 
774  //Return the value of the PHY register
775  return data;
776 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void avr32EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define AVR32_ETH_TX_BUFFER_COUNT
#define MACB_RMII_MASK
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
#define AVR32_ETH_RX_BUFFER_COUNT
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define MACB_TX_LENGTH
#define MACB_MAN_SOF_01
uint8_t p
Definition: ndp.h:298
void avr32EthDisableIrq(NetInterface *interface)
Disable interrupts.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:89
uint_t avr32EthReceivePacket(NetInterface *interface)
Receive a packet.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
error_t avr32EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
bool_t avr32EthIrqHandler(void)
AVR32 Ethernet MAC interrupt service routine.
#define osExitIsr(flag)
#define MACB_RX_LENGTH
#define SMI_OPCODE_WRITE
Definition: nic.h:62
AVR32 Ethernet MAC controller.
#define MACB_RX_WRAP
#define MACB_RX_SOF
#define AVR32_ETH_IRQ_PRIORITY
Transmit buffer descriptor.
#define FALSE
Definition: os_port.h:46
#define MACB_RX_OWNERSHIP
error_t
Error codes.
Definition: error.h:42
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
Receive buffer descriptor.
#define txBuffer
error_t avr32EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:222
#define MACB_RX_EOF
@ ERROR_INVALID_LENGTH
Definition: error.h:109
void avr32EthEnableIrq(NetInterface *interface)
Enable interrupts.
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
void avr32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
OsEvent netEvent
Definition: net.c:77
#define SMI_OPCODE_READ
Definition: nic.h:63
#define TRACE_INFO(...)
Definition: debug.h:94
#define AVR32_ETH_TX_BUFFER_SIZE
#define MACB_MAN_CODE_10
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
void avr32EthEventHandler(NetInterface *interface)
AVR32 Ethernet MAC event handler.
void avr32EthInitGpio(NetInterface *interface)
error_t avr32EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define MIN(a, b)
Definition: os_port.h:62
#define rxBuffer
void avr32EthTick(NetInterface *interface)
AVR32 Ethernet MAC timer handler.
#define TRACE_DEBUG(...)
Definition: debug.h:106
#define MACB_TX_WRAP
uint16_t regAddr
#define MACB_RX_ADDRESS
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
MAC filter table entry.
Definition: ethernet.h:220
#define osEnterIsr()
uint16_t avr32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define MACB_MAN_RW_01
#define MACB_TX_LAST
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MACB_MAN_RW_10
error_t avr32EthInit(NetInterface *interface)
AVR32 Ethernet MAC initialization.
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
#define AVR32_ETH_RX_BUFFER_SIZE
const NicDriver avr32EthDriver
AVR32 Ethernet MAC driver.
void avr32EthIrqWrapper(void)
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define MACB_TX_USED
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79