dm9000_driver.h
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1 /**
2  * @file dm9000_driver.h
3  * @brief DM9000A/B Ethernet controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _DM9000_DRIVER_H
30 #define _DM9000_DRIVER_H
31 
32 //Dependencies
33 #include "core/ethernet.h"
34 
35 //Loopback mode
36 #ifndef DM9000_LOOPBACK_MODE
37  #define DM9000_LOOPBACK_MODE DISABLED
38 #elif (DM9000_LOOPBACK_MODE != ENABLED && DM9000_LOOPBACK_MODE != DISABLED)
39  #error DM9000_LOOPBACK_MODE parameter is not valid
40 #endif
41 
42 //DM9000 index register
43 #ifndef DM9000_INDEX_REG
44  #define DM9000_INDEX_REG *((volatile uint16_t *) 0x30000000)
45 #endif
46 
47 //DM9000 data register
48 #ifndef DM9000_DATA_REG
49  #define DM9000_DATA_REG *((volatile uint16_t *) 0x30001000)
50 #endif
51 
52 //DM9000 bus timing
53 #define AT91C_SMC2_NWS_2 (2 << 0)
54 #define AT91C_SMC2_TDF_2 (2 << 8)
55 #define AT91C_SMC2_BAT_16 (1 << 12)
56 #define AT91C_SMC2_DRP_STANDARD (0 << 15)
57 #define AT91C_SMC2_RWSETUP_1 (1 << 24)
58 #define AT91C_SMC2_RWHOLD_1 (1 << 28)
59 
60 //DM9000 identifiers
61 #define DM9000_VID 0x0A46
62 #define DM9000_PID 0x9000
63 #define DM9000A_CHIP_REV 0x19
64 #define DM9000B_CHIP_REV 0x1A
65 
66 //DM9000 registers
67 #define DM9000_REG_NCR 0x00
68 #define DM9000_REG_NSR 0x01
69 #define DM9000_REG_TCR 0x02
70 #define DM9000_REG_TSR1 0x03
71 #define DM9000_REG_TSR2 0x04
72 #define DM9000_REG_RCR 0x05
73 #define DM9000_REG_RSR 0x06
74 #define DM9000_REG_ROCR 0x07
75 #define DM9000_REG_BPTR 0x08
76 #define DM9000_REG_FCTR 0x09
77 #define DM9000_REG_FCR 0x0A
78 #define DM9000_REG_EPCR 0x0B
79 #define DM9000_REG_EPAR 0x0C
80 #define DM9000_REG_EPDRL 0x0D
81 #define DM9000_REG_EPDRH 0x0E
82 #define DM9000_REG_WCR 0x0F
83 #define DM9000_REG_PAR0 0x10
84 #define DM9000_REG_PAR1 0x11
85 #define DM9000_REG_PAR2 0x12
86 #define DM9000_REG_PAR3 0x13
87 #define DM9000_REG_PAR4 0x14
88 #define DM9000_REG_PAR5 0x15
89 #define DM9000_REG_MAR0 0x16
90 #define DM9000_REG_MAR1 0x17
91 #define DM9000_REG_MAR2 0x18
92 #define DM9000_REG_MAR3 0x19
93 #define DM9000_REG_MAR4 0x1A
94 #define DM9000_REG_MAR5 0x1B
95 #define DM9000_REG_MAR6 0x1C
96 #define DM9000_REG_MAR7 0x1D
97 #define DM9000_REG_GPCR 0x1E
98 #define DM9000_REG_GPR 0x1F
99 #define DM9000_REG_TRPAL 0x22
100 #define DM9000_REG_TRPAH 0x23
101 #define DM9000_REG_RWPAL 0x24
102 #define DM9000_REG_RWPAH 0x25
103 #define DM9000_REG_VIDL 0x28
104 #define DM9000_REG_VIDH 0x29
105 #define DM9000_REG_PIDL 0x2A
106 #define DM9000_REG_PIDH 0x2B
107 #define DM9000_REG_CHIPR 0x2C
108 #define DM9000_REG_TCR2 0x2D
109 #define DM9000_REG_OCR 0x2E
110 #define DM9000_REG_SMCR 0x2F
111 #define DM9000_REG_ETXCSR 0x30
112 #define DM9000_REG_TCSCR 0x31
113 #define DM9000_REG_RCSCSR 0x32
114 #define DM9000_REG_MPAR 0x33
115 #define DM9000_REG_LEDCR 0x34
116 #define DM9000_REG_BUSCR 0x38
117 #define DM9000_REG_INTCR 0x39
118 #define DM9000_REG_SCCR 0x50
119 #define DM9000_REG_RSCCR 0x51
120 #define DM9000_REG_MRCMDX 0xF0
121 #define DM9000_REG_MRCMDX1 0xF1
122 #define DM9000_REG_MRCMD 0xF2
123 #define DM9000_REG_MRRL 0xF4
124 #define DM9000_REG_MRRH 0xF5
125 #define DM9000_REG_MWCMDX 0xF6
126 #define DM9000_REG_MWCMD 0xF8
127 #define DM9000_REG_MWRL 0xFA
128 #define DM9000_REG_MWRH 0xFB
129 #define DM9000_REG_TXPLL 0xFC
130 #define DM9000_REG_TXPLH 0xFD
131 #define DM9000_REG_ISR 0xFE
132 #define DM9000_REG_IMR 0xFF
133 
134 //DM9000 PHY registers
135 #define DM9000_PHY_REG_BMCR 0x00
136 #define DM9000_PHY_REG_BMSR 0x01
137 #define DM9000_PHY_REG_PHYIDR1 0x02
138 #define DM9000_PHY_REG_PHYIDR2 0x03
139 #define DM9000_PHY_REG_ANAR 0x04
140 #define DM9000_PHY_REG_ANLPAR 0x05
141 #define DM9000_PHY_REG_ANER 0x06
142 #define DM9000_PHY_REG_DSCR 0x10
143 #define DM9000_PHY_REG_DSCSR 0x11
144 #define DM9000_PHY_REG_10BTCSR 0x12
145 #define DM9000_PHY_REG_PWDOR 0x13
146 #define DM9000_PHY_REG_SCR 0x14
147 #define DM9000_PHY_REG_DSP 0x1B
148 #define DM9000_PHY_REG_PSCR 0x1D
149 
150 //NCR register
151 #define NCR_WAKEEN (1 << 6)
152 #define NCR_FCOL (1 << 4)
153 #define NCR_FDX (1 << 3)
154 #define NCR_LBK (3 << 1)
155 #define NCR_RST (1 << 0)
156 
157 //NSR register
158 #define NSR_SPEED (1 << 7)
159 #define NSR_LINKST (1 << 6)
160 #define NSR_WAKEST (1 << 5)
161 #define NSR_TX2END (1 << 3)
162 #define NSR_TX1END (1 << 2)
163 #define NSR_RXOV (1 << 1)
164 
165 //TCR register
166 #define TCR_TJDIS (1 << 6)
167 #define TCR_EXCECM (1 << 5)
168 #define TCR_PAD_DIS2 (1 << 4)
169 #define TCR_CRC_DIS2 (1 << 3)
170 #define TCR_PAD_DIS1 (1 << 2)
171 #define TCR_CRC_DIS1 (1 << 1)
172 #define TCR_TXREQ (1 << 0)
173 
174 //TSR1 and TSR2 registers
175 #define TSR_TJTO (1 << 7)
176 #define TSR_LC (1 << 6)
177 #define TSR_NC (1 << 5)
178 #define TSR_LCOL (1 << 4)
179 #define TSR_COL (1 << 3)
180 #define TSR_EC (1 << 2)
181 
182 //RCR register
183 #define RCR_WTDIS (1 << 6)
184 #define RCR_DIS_LONG (1 << 5)
185 #define RCR_DIS_CRC (1 << 4)
186 #define RCR_ALL (1 << 3)
187 #define RCR_RUNT (1 << 2)
188 #define RCR_PRMSC (1 << 1)
189 #define RCR_RXEN (1 << 0)
190 
191 //RSR register
192 #define RSR_RF (1 << 7)
193 #define RSR_MF (1 << 6)
194 #define RSR_LCS (1 << 5)
195 #define RSR_RWTO (1 << 4)
196 #define RSR_PLE (1 << 3)
197 #define RSR_AE (1 << 2)
198 #define RSR_CE (1 << 1)
199 #define RSR_FOE (1 << 0)
200 
201 //ROCR register
202 #define ROCR_ROC (127 << 0)
203 #define ROCR_RXFU (1 << 7)
204 
205 //BPTR register
206 #define BPTR_BPHW (15 << 4)
207 #define BPTR_JPT (15 << 0)
208 
209 //FCTR register
210 #define FCTR_HWOT (15 << 4)
211 #define FCTR_LWOT (15 << 0)
212 
213 //FCR register
214 #define FCR_TXP0 (1 << 7)
215 #define FCR_TXPF (1 << 6)
216 #define FCR_TXPEN (1 << 5)
217 #define FCR_BKPA (1 << 4)
218 #define FCR_BKPM (1 << 3)
219 #define FCR_RXPS (1 << 2)
220 #define FCR_RXPCS (1 << 1)
221 #define FCR_FLCE (1 << 0)
222 
223 //EPCR register
224 #define EPCR_REEP (1 << 5)
225 #define EPCR_WEP (1 << 4)
226 #define EPCR_EPOS (1 << 3)
227 #define EPCR_ERPRR (1 << 2)
228 #define EPCR_ERPRW (1 << 1)
229 #define EPCR_ERRE (1 << 0)
230 
231 //EPAR register
232 #define EPAR_PHY_ADR (3 << 6)
233 #define EPAR_EROA (31 << 0)
234 
235 //WCR register
236 #define WCR_LINKEN (1 << 5)
237 #define WCR_SAMPLEEN (1 << 4)
238 #define WCR_MAGICEN (1 << 3)
239 #define WCR_LINKST (1 << 2)
240 #define WCR_SAMPLEST (1 << 1)
241 #define WCR_MAGICST (1 << 0)
242 
243 //GPCR register
244 #define GPCR_GPC6 (1 << 6)
245 #define GPCR_GPC5 (1 << 5)
246 #define GPCR_GPC4 (1 << 4)
247 #define GPCR_GPC3 (1 << 3)
248 #define GPCR_GPC2 (1 << 2)
249 #define GPCR_GPC1 (1 << 1)
250 
251 //GPR register
252 #define GPR_GPO6 (1 << 6)
253 #define GPR_GPO5 (1 << 5)
254 #define GPR_GPO4 (1 << 4)
255 #define GPR_GPIO3 (1 << 3)
256 #define GPR_GPIO2 (1 << 2)
257 #define GPR_GPIO1 (1 << 1)
258 #define GPR_PHYPD (1 << 0)
259 
260 //TCR2 register
261 #define TCR2_LED (1 << 7)
262 #define TCR2_RLCP (1 << 6)
263 #define TCR2_DTU (1 << 5)
264 #define TCR2_ONEPM (1 << 4)
265 #define TCR2_IFGS (15 << 0)
266 
267 //OCR register
268 #define OCR_SCC (3 << 6)
269 #define OCR_SOE (1 << 4)
270 #define OCR_SCS (1 << 3)
271 #define OCR_PHYOP (7 << 0)
272 
273 //SMCR register
274 #define SMCR_SM_EN (1 << 7)
275 #define SMCR_FLC (1 << 2)
276 #define SMCR_FB1 (1 << 1)
277 #define SMCR_FB0 (1 << 0)
278 
279 //ETXCSR register
280 #define ETXCSR_ETE (1 << 7)
281 #define ETXCSR_ETS2 (1 << 6)
282 #define ETXCSR_ETS1 (1 << 5)
283 #define ETXCSR_ETT (3 << 0)
284 
285 //TCSCR register
286 #define TCSCR_UDPCSE (1 << 2)
287 #define TCSCR_TCPCSE (1 << 1)
288 #define TCSCR_IPCSE (1 << 0)
289 
290 //RCSCSR register
291 #define RCSCSR_UDPS (1 << 7)
292 #define RCSCSR_TCPS (1 << 6)
293 #define RCSCSR_IPS (1 << 5)
294 #define RCSCSR_UDPP (1 << 4)
295 #define RCSCSR_TCPP (1 << 3)
296 #define RCSCSR_IPP (1 << 2)
297 #define RCSCSR_RCSEN (1 << 1)
298 #define RCSCSR_DCSE (1 << 0)
299 
300 //MPAR register
301 #define MPAR_ADR_EN (1 << 7)
302 #define MPAR_EPHYADR (31 << 0)
303 
304 //LEDC register
305 #define LEDCR_GPIO (1 << 1)
306 #define LEDCR_MII (1 << 0)
307 
308 //BUSCR register
309 #define BUSCR_CURR (3 << 5)
310 #define BUSCR_EST (1 << 3)
311 #define BUSCR_IOW_SPIKE (1 << 1)
312 #define BUSCR_IOR_SPIKE (1 << 0)
313 
314 //INTCR register
315 #define INTCR_INT_TYPE (1 << 1)
316 #define INTCR_INT_POL (1 << 0)
317 
318 //SCCR register
319 #define SCCR_DIS_CLK (1 << 0)
320 
321 //ISR register
322 #define ISR_IOMODE (1 << 7)
323 #define ISR_LNKCHG (1 << 5)
324 #define ISR_UDRUN (1 << 4)
325 #define ISR_ROO (1 << 3)
326 #define ISR_ROS (1 << 2)
327 #define ISR_PT (1 << 1)
328 #define ISR_PR (1 << 0)
329 
330 //IMR register
331 #define IMR_PAR (1 << 7)
332 #define IMR_LNKCHGI (1 << 5)
333 #define IMR_UDRUNI (1 << 4)
334 #define IMR_ROOI (1 << 3)
335 #define IMR_ROI (1 << 2)
336 #define IMR_PTI (1 << 1)
337 #define IMR_PRI (1 << 0)
338 
339 //PHY BMCR register
340 #define BMCR_RST (1 << 15)
341 #define BMCR_LOOPBACK (1 << 14)
342 #define BMCR_SPEED_SEL (1 << 13)
343 #define BMCR_AN_EN (1 << 12)
344 #define BMCR_PD (1 << 11)
345 #define BMCR_ISOLATE (1 << 10)
346 #define BMCR_RESTART_AN (1 << 9)
347 #define BMCR_DUPLEX_MODE (1 << 8)
348 #define BMCR_COL_TEST (1 << 7)
349 
350 //Loopback mode
351 #define DM9000_LBK_NORMAL (0 << 1)
352 #define DM9000_LBK_MAC (1 << 1)
353 #define DM9000_LBK_PHY (2 << 1)
354 
355 //C++ guard
356 #ifdef __cplusplus
357  extern "C" {
358 #endif
359 
360 
361 /**
362  * @brief DM9000 driver context
363  **/
364 
365 typedef struct
366 {
367  uint_t queuedPackets; ///<Number of packets in transmission buffer
368  uint8_t *txBuffer; ///<Transmit buffer
369  uint8_t *rxBuffer; ///<Receive buffer
370 } Dm9000Context;
371 
372 
373 //DM9000 driver
374 extern const NicDriver dm9000Driver;
375 
376 //DM9000 related functions
377 error_t dm9000Init(NetInterface *interface);
378 
379 void dm9000Tick(NetInterface *interface);
380 
381 void dm9000EnableIrq(NetInterface *interface);
382 void dm9000DisableIrq(NetInterface *interface);
384 void dm9000EventHandler(NetInterface *interface);
385 
387  const NetBuffer *buffer, size_t offset);
388 
390 
392 
393 void dm9000WriteReg(uint8_t address, uint8_t data);
394 uint8_t dm9000ReadReg(uint8_t address);
395 
396 void dm9000WritePhyReg(uint8_t address, uint16_t data);
397 uint16_t dm9000ReadPhyReg(uint8_t address);
398 
399 uint32_t dm9000CalcCrc(const void *data, size_t length);
400 
401 //C++ guard
402 #ifdef __cplusplus
403  }
404 #endif
405 
406 #endif
uint8_t dm9000ReadReg(uint8_t address)
Read DM9000 register.
error_t dm9000SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet to DM9000.
bool_t dm9000IrqHandler(NetInterface *interface)
DM9000 interrupt service routine.
void dm9000EventHandler(NetInterface *interface)
DM9000 event handler.
uint_t queuedPackets
Number of packets in transmission buffer.
DM9000 driver context.
const NicDriver dm9000Driver
DM9000 driver.
Definition: dm9000_driver.c:43
void dm9000EnableIrq(NetInterface *interface)
Enable interrupts.
void dm9000DisableIrq(NetInterface *interface)
Disable interrupts.
Ethernet.
void dm9000WritePhyReg(uint8_t address, uint16_t data)
Write DM9000 PHY register.
error_t dm9000UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void dm9000Tick(NetInterface *interface)
DM9000 timer handler.
void dm9000WriteReg(uint8_t address, uint8_t data)
Write DM9000 register.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
error_t dm9000Init(NetInterface *interface)
DM9000 controller initialization.
Definition: dm9000_driver.c:70
#define NetInterface
Definition: net.h:34
uint8_t * txBuffer
Transmit buffer.
uint16_t dm9000ReadPhyReg(uint8_t address)
Read DM9000 PHY register.
uint8_t length
Definition: dtls_misc.h:140
uint32_t dm9000CalcCrc(const void *data, size_t length)
CRC calculation.
int bool_t
Definition: compiler_port.h:47
uint8_t * rxBuffer
Receive buffer.
error_t dm9000ReceivePacket(NetInterface *interface)
Receive a packet.