dm9000_driver.h
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1 /**
2  * @file dm9000_driver.h
3  * @brief DM9000A/B Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 #ifndef _DM9000_DRIVER_H
32 #define _DM9000_DRIVER_H
33 
34 //Dependencies
35 #include "core/ethernet.h"
36 
37 //Loopback mode
38 #ifndef DM9000_LOOPBACK_MODE
39  #define DM9000_LOOPBACK_MODE DISABLED
40 #elif (DM9000_LOOPBACK_MODE != ENABLED && DM9000_LOOPBACK_MODE != DISABLED)
41  #error DM9000_LOOPBACK_MODE parameter is not valid
42 #endif
43 
44 //DM9000 index register
45 #ifndef DM9000_INDEX_REG
46  #define DM9000_INDEX_REG *((volatile uint16_t *) 0x30000000)
47 #endif
48 
49 //DM9000 data register
50 #ifndef DM9000_DATA_REG
51  #define DM9000_DATA_REG *((volatile uint16_t *) 0x30001000)
52 #endif
53 
54 //DM9000 bus timing
55 #define AT91C_SMC2_NWS_2 (2 << 0)
56 #define AT91C_SMC2_TDF_2 (2 << 8)
57 #define AT91C_SMC2_BAT_16 (1 << 12)
58 #define AT91C_SMC2_DRP_STANDARD (0 << 15)
59 #define AT91C_SMC2_RWSETUP_1 (1 << 24)
60 #define AT91C_SMC2_RWHOLD_1 (1 << 28)
61 
62 //DM9000 identifiers
63 #define DM9000_VID 0x0A46
64 #define DM9000_PID 0x9000
65 #define DM9000A_CHIP_REV 0x19
66 #define DM9000B_CHIP_REV 0x1A
67 
68 //DM9000 registers
69 #define DM9000_REG_NCR 0x00
70 #define DM9000_REG_NSR 0x01
71 #define DM9000_REG_TCR 0x02
72 #define DM9000_REG_TSR1 0x03
73 #define DM9000_REG_TSR2 0x04
74 #define DM9000_REG_RCR 0x05
75 #define DM9000_REG_RSR 0x06
76 #define DM9000_REG_ROCR 0x07
77 #define DM9000_REG_BPTR 0x08
78 #define DM9000_REG_FCTR 0x09
79 #define DM9000_REG_FCR 0x0A
80 #define DM9000_REG_EPCR 0x0B
81 #define DM9000_REG_EPAR 0x0C
82 #define DM9000_REG_EPDRL 0x0D
83 #define DM9000_REG_EPDRH 0x0E
84 #define DM9000_REG_WCR 0x0F
85 #define DM9000_REG_PAR0 0x10
86 #define DM9000_REG_PAR1 0x11
87 #define DM9000_REG_PAR2 0x12
88 #define DM9000_REG_PAR3 0x13
89 #define DM9000_REG_PAR4 0x14
90 #define DM9000_REG_PAR5 0x15
91 #define DM9000_REG_MAR0 0x16
92 #define DM9000_REG_MAR1 0x17
93 #define DM9000_REG_MAR2 0x18
94 #define DM9000_REG_MAR3 0x19
95 #define DM9000_REG_MAR4 0x1A
96 #define DM9000_REG_MAR5 0x1B
97 #define DM9000_REG_MAR6 0x1C
98 #define DM9000_REG_MAR7 0x1D
99 #define DM9000_REG_GPCR 0x1E
100 #define DM9000_REG_GPR 0x1F
101 #define DM9000_REG_TRPAL 0x22
102 #define DM9000_REG_TRPAH 0x23
103 #define DM9000_REG_RWPAL 0x24
104 #define DM9000_REG_RWPAH 0x25
105 #define DM9000_REG_VIDL 0x28
106 #define DM9000_REG_VIDH 0x29
107 #define DM9000_REG_PIDL 0x2A
108 #define DM9000_REG_PIDH 0x2B
109 #define DM9000_REG_CHIPR 0x2C
110 #define DM9000_REG_TCR2 0x2D
111 #define DM9000_REG_OCR 0x2E
112 #define DM9000_REG_SMCR 0x2F
113 #define DM9000_REG_ETXCSR 0x30
114 #define DM9000_REG_TCSCR 0x31
115 #define DM9000_REG_RCSCSR 0x32
116 #define DM9000_REG_MPAR 0x33
117 #define DM9000_REG_LEDCR 0x34
118 #define DM9000_REG_BUSCR 0x38
119 #define DM9000_REG_INTCR 0x39
120 #define DM9000_REG_SCCR 0x50
121 #define DM9000_REG_RSCCR 0x51
122 #define DM9000_REG_MRCMDX 0xF0
123 #define DM9000_REG_MRCMDX1 0xF1
124 #define DM9000_REG_MRCMD 0xF2
125 #define DM9000_REG_MRRL 0xF4
126 #define DM9000_REG_MRRH 0xF5
127 #define DM9000_REG_MWCMDX 0xF6
128 #define DM9000_REG_MWCMD 0xF8
129 #define DM9000_REG_MWRL 0xFA
130 #define DM9000_REG_MWRH 0xFB
131 #define DM9000_REG_TXPLL 0xFC
132 #define DM9000_REG_TXPLH 0xFD
133 #define DM9000_REG_ISR 0xFE
134 #define DM9000_REG_IMR 0xFF
135 
136 //DM9000 PHY registers
137 #define DM9000_PHY_REG_BMCR 0x00
138 #define DM9000_PHY_REG_BMSR 0x01
139 #define DM9000_PHY_REG_PHYIDR1 0x02
140 #define DM9000_PHY_REG_PHYIDR2 0x03
141 #define DM9000_PHY_REG_ANAR 0x04
142 #define DM9000_PHY_REG_ANLPAR 0x05
143 #define DM9000_PHY_REG_ANER 0x06
144 #define DM9000_PHY_REG_DSCR 0x10
145 #define DM9000_PHY_REG_DSCSR 0x11
146 #define DM9000_PHY_REG_10BTCSR 0x12
147 #define DM9000_PHY_REG_PWDOR 0x13
148 #define DM9000_PHY_REG_SCR 0x14
149 #define DM9000_PHY_REG_DSP 0x1B
150 #define DM9000_PHY_REG_PSCR 0x1D
151 
152 //NCR register
153 #define NCR_WAKEEN (1 << 6)
154 #define NCR_FCOL (1 << 4)
155 #define NCR_FDX (1 << 3)
156 #define NCR_LBK (3 << 1)
157 #define NCR_RST (1 << 0)
158 
159 //NSR register
160 #define NSR_SPEED (1 << 7)
161 #define NSR_LINKST (1 << 6)
162 #define NSR_WAKEST (1 << 5)
163 #define NSR_TX2END (1 << 3)
164 #define NSR_TX1END (1 << 2)
165 #define NSR_RXOV (1 << 1)
166 
167 //TCR register
168 #define TCR_TJDIS (1 << 6)
169 #define TCR_EXCECM (1 << 5)
170 #define TCR_PAD_DIS2 (1 << 4)
171 #define TCR_CRC_DIS2 (1 << 3)
172 #define TCR_PAD_DIS1 (1 << 2)
173 #define TCR_CRC_DIS1 (1 << 1)
174 #define TCR_TXREQ (1 << 0)
175 
176 //TSR1 and TSR2 registers
177 #define TSR_TJTO (1 << 7)
178 #define TSR_LC (1 << 6)
179 #define TSR_NC (1 << 5)
180 #define TSR_LCOL (1 << 4)
181 #define TSR_COL (1 << 3)
182 #define TSR_EC (1 << 2)
183 
184 //RCR register
185 #define RCR_WTDIS (1 << 6)
186 #define RCR_DIS_LONG (1 << 5)
187 #define RCR_DIS_CRC (1 << 4)
188 #define RCR_ALL (1 << 3)
189 #define RCR_RUNT (1 << 2)
190 #define RCR_PRMSC (1 << 1)
191 #define RCR_RXEN (1 << 0)
192 
193 //RSR register
194 #define RSR_RF (1 << 7)
195 #define RSR_MF (1 << 6)
196 #define RSR_LCS (1 << 5)
197 #define RSR_RWTO (1 << 4)
198 #define RSR_PLE (1 << 3)
199 #define RSR_AE (1 << 2)
200 #define RSR_CE (1 << 1)
201 #define RSR_FOE (1 << 0)
202 
203 //ROCR register
204 #define ROCR_ROC (127 << 0)
205 #define ROCR_RXFU (1 << 7)
206 
207 //BPTR register
208 #define BPTR_BPHW (15 << 4)
209 #define BPTR_JPT (15 << 0)
210 
211 //FCTR register
212 #define FCTR_HWOT (15 << 4)
213 #define FCTR_LWOT (15 << 0)
214 
215 //FCR register
216 #define FCR_TXP0 (1 << 7)
217 #define FCR_TXPF (1 << 6)
218 #define FCR_TXPEN (1 << 5)
219 #define FCR_BKPA (1 << 4)
220 #define FCR_BKPM (1 << 3)
221 #define FCR_RXPS (1 << 2)
222 #define FCR_RXPCS (1 << 1)
223 #define FCR_FLCE (1 << 0)
224 
225 //EPCR register
226 #define EPCR_REEP (1 << 5)
227 #define EPCR_WEP (1 << 4)
228 #define EPCR_EPOS (1 << 3)
229 #define EPCR_ERPRR (1 << 2)
230 #define EPCR_ERPRW (1 << 1)
231 #define EPCR_ERRE (1 << 0)
232 
233 //EPAR register
234 #define EPAR_PHY_ADR (3 << 6)
235 #define EPAR_EROA (31 << 0)
236 
237 //WCR register
238 #define WCR_LINKEN (1 << 5)
239 #define WCR_SAMPLEEN (1 << 4)
240 #define WCR_MAGICEN (1 << 3)
241 #define WCR_LINKST (1 << 2)
242 #define WCR_SAMPLEST (1 << 1)
243 #define WCR_MAGICST (1 << 0)
244 
245 //GPCR register
246 #define GPCR_GPC6 (1 << 6)
247 #define GPCR_GPC5 (1 << 5)
248 #define GPCR_GPC4 (1 << 4)
249 #define GPCR_GPC3 (1 << 3)
250 #define GPCR_GPC2 (1 << 2)
251 #define GPCR_GPC1 (1 << 1)
252 
253 //GPR register
254 #define GPR_GPO6 (1 << 6)
255 #define GPR_GPO5 (1 << 5)
256 #define GPR_GPO4 (1 << 4)
257 #define GPR_GPIO3 (1 << 3)
258 #define GPR_GPIO2 (1 << 2)
259 #define GPR_GPIO1 (1 << 1)
260 #define GPR_PHYPD (1 << 0)
261 
262 //TCR2 register
263 #define TCR2_LED (1 << 7)
264 #define TCR2_RLCP (1 << 6)
265 #define TCR2_DTU (1 << 5)
266 #define TCR2_ONEPM (1 << 4)
267 #define TCR2_IFGS (15 << 0)
268 
269 //OCR register
270 #define OCR_SCC (3 << 6)
271 #define OCR_SOE (1 << 4)
272 #define OCR_SCS (1 << 3)
273 #define OCR_PHYOP (7 << 0)
274 
275 //SMCR register
276 #define SMCR_SM_EN (1 << 7)
277 #define SMCR_FLC (1 << 2)
278 #define SMCR_FB1 (1 << 1)
279 #define SMCR_FB0 (1 << 0)
280 
281 //ETXCSR register
282 #define ETXCSR_ETE (1 << 7)
283 #define ETXCSR_ETS2 (1 << 6)
284 #define ETXCSR_ETS1 (1 << 5)
285 #define ETXCSR_ETT (3 << 0)
286 
287 //TCSCR register
288 #define TCSCR_UDPCSE (1 << 2)
289 #define TCSCR_TCPCSE (1 << 1)
290 #define TCSCR_IPCSE (1 << 0)
291 
292 //RCSCSR register
293 #define RCSCSR_UDPS (1 << 7)
294 #define RCSCSR_TCPS (1 << 6)
295 #define RCSCSR_IPS (1 << 5)
296 #define RCSCSR_UDPP (1 << 4)
297 #define RCSCSR_TCPP (1 << 3)
298 #define RCSCSR_IPP (1 << 2)
299 #define RCSCSR_RCSEN (1 << 1)
300 #define RCSCSR_DCSE (1 << 0)
301 
302 //MPAR register
303 #define MPAR_ADR_EN (1 << 7)
304 #define MPAR_EPHYADR (31 << 0)
305 
306 //LEDC register
307 #define LEDCR_GPIO (1 << 1)
308 #define LEDCR_MII (1 << 0)
309 
310 //BUSCR register
311 #define BUSCR_CURR (3 << 5)
312 #define BUSCR_EST (1 << 3)
313 #define BUSCR_IOW_SPIKE (1 << 1)
314 #define BUSCR_IOR_SPIKE (1 << 0)
315 
316 //INTCR register
317 #define INTCR_INT_TYPE (1 << 1)
318 #define INTCR_INT_POL (1 << 0)
319 
320 //SCCR register
321 #define SCCR_DIS_CLK (1 << 0)
322 
323 //ISR register
324 #define ISR_IOMODE (1 << 7)
325 #define ISR_LNKCHG (1 << 5)
326 #define ISR_UDRUN (1 << 4)
327 #define ISR_ROO (1 << 3)
328 #define ISR_ROS (1 << 2)
329 #define ISR_PT (1 << 1)
330 #define ISR_PR (1 << 0)
331 
332 //IMR register
333 #define IMR_PAR (1 << 7)
334 #define IMR_LNKCHGI (1 << 5)
335 #define IMR_UDRUNI (1 << 4)
336 #define IMR_ROOI (1 << 3)
337 #define IMR_ROI (1 << 2)
338 #define IMR_PTI (1 << 1)
339 #define IMR_PRI (1 << 0)
340 
341 //PHY BMCR register
342 #define BMCR_RST (1 << 15)
343 #define BMCR_LOOPBACK (1 << 14)
344 #define BMCR_SPEED_SEL (1 << 13)
345 #define BMCR_AN_EN (1 << 12)
346 #define BMCR_PD (1 << 11)
347 #define BMCR_ISOLATE (1 << 10)
348 #define BMCR_RESTART_AN (1 << 9)
349 #define BMCR_DUPLEX_MODE (1 << 8)
350 #define BMCR_COL_TEST (1 << 7)
351 
352 //Loopback mode
353 #define DM9000_LBK_NORMAL (0 << 1)
354 #define DM9000_LBK_MAC (1 << 1)
355 #define DM9000_LBK_PHY (2 << 1)
356 
357 //C++ guard
358 #ifdef __cplusplus
359 extern "C" {
360 #endif
361 
362 
363 /**
364  * @brief DM9000 driver context
365  **/
366 
367 typedef struct
368 {
369  uint_t queuedPackets; ///<Number of packets in transmission buffer
370  uint8_t *txBuffer; ///<Transmit buffer
371  uint8_t *rxBuffer; ///<Receive buffer
372 } Dm9000Context;
373 
374 
375 //DM9000 driver
376 extern const NicDriver dm9000Driver;
377 
378 //DM9000 related functions
379 error_t dm9000Init(NetInterface *interface);
380 
381 void dm9000Tick(NetInterface *interface);
382 
383 void dm9000EnableIrq(NetInterface *interface);
384 void dm9000DisableIrq(NetInterface *interface);
386 void dm9000EventHandler(NetInterface *interface);
387 
389  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
390 
392 
394 
395 void dm9000WriteReg(uint8_t address, uint8_t data);
396 uint8_t dm9000ReadReg(uint8_t address);
397 
398 void dm9000WritePhyReg(uint8_t address, uint16_t data);
399 uint16_t dm9000ReadPhyReg(uint8_t address);
400 
401 uint32_t dm9000CalcCrc(const void *data, size_t length);
402 
403 //C++ guard
404 #ifdef __cplusplus
405 }
406 #endif
407 
408 #endif
uint8_t length
Definition: coap_common.h:190
uint16_t dm9000ReadPhyReg(uint8_t address)
Read DM9000 PHY register.
int bool_t
Definition: compiler_port.h:49
uint8_t data[]
Definition: ethernet.h:209
uint8_t * rxBuffer
Receive buffer.
void dm9000Tick(NetInterface *interface)
DM9000 timer handler.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t dm9000Init(NetInterface *interface)
DM9000 controller initialization.
Definition: dm9000_driver.c:72
uint8_t dm9000ReadReg(uint8_t address)
Read DM9000 register.
Ethernet.
error_t
Error codes.
Definition: error.h:42
bool_t dm9000IrqHandler(NetInterface *interface)
DM9000 interrupt service routine.
uint32_t dm9000CalcCrc(const void *data, size_t length)
CRC calculation.
#define NetInterface
Definition: net.h:36
void dm9000WriteReg(uint8_t address, uint8_t data)
Write DM9000 register.
void dm9000DisableIrq(NetInterface *interface)
Disable interrupts.
#define NetTxAncillary
Definition: net_misc.h:36
error_t dm9000ReceivePacket(NetInterface *interface)
Receive a packet.
error_t dm9000SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint8_t * txBuffer
Transmit buffer.
void dm9000EventHandler(NetInterface *interface)
DM9000 event handler.
Ipv6Addr address
void dm9000EnableIrq(NetInterface *interface)
Enable interrupts.
DM9000 driver context.
error_t dm9000UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
const NicDriver dm9000Driver
DM9000 driver.
Definition: dm9000_driver.c:45
unsigned int uint_t
Definition: compiler_port.h:45
NIC driver.
Definition: nic.h:257
uint_t queuedPackets
Number of packets in transmission buffer.
void dm9000WritePhyReg(uint8_t address, uint16_t data)
Write DM9000 PHY register.