dm9000_driver.c
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1 /**
2  * @file dm9000_driver.c
3  * @brief DM9000A/B Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "core/net.h"
36 #include "core/ethernet.h"
38 #include "debug.h"
39 
40 
41 /**
42  * @brief DM9000 driver
43  **/
44 
46 {
48  ETH_MTU,
49  dm9000Init,
50  dm9000Tick,
56  NULL,
57  NULL,
58  NULL,
59  TRUE,
60  TRUE,
61  TRUE,
62  FALSE
63 };
64 
65 
66 /**
67  * @brief DM9000 controller initialization
68  * @param[in] interface Underlying network interface
69  * @return Error code
70  **/
71 
73 {
74  uint_t i;
75  uint16_t vendorId;
76  uint16_t productId;
77  uint8_t chipRevision;
78  Dm9000Context *context;
79 
80  //Debug message
81  TRACE_INFO("Initializing DM9000 Ethernet controller...\r\n");
82 
83  //Initialize external interrupt line
84  interface->extIntDriver->init();
85 
86  //Point to the driver context
87  context = (Dm9000Context *) interface->nicContext;
88 
89  //Initialize driver specific variables
90  context->queuedPackets = 0;
91 
92  //Allocate TX and RX buffers
95 
96  //Failed to allocate memory?
97  if(context->txBuffer == NULL || context->rxBuffer == NULL)
98  {
99  //Clean up side effects
100  memPoolFree(context->txBuffer);
101  memPoolFree(context->rxBuffer);
102 
103  //Report an error
104  return ERROR_OUT_OF_MEMORY;
105  }
106 
107  //Retrieve vendorID, product ID and chip revision
110  chipRevision = dm9000ReadReg(DM9000_REG_CHIPR);
111 
112  //Check vendor ID and product ID
113  if(vendorId != DM9000_VID || productId != DM9000_PID)
114  {
115  return ERROR_WRONG_IDENTIFIER;
116  }
117 
118  //Check chip revision
119  if(chipRevision != DM9000A_CHIP_REV && chipRevision != DM9000B_CHIP_REV)
120  {
121  return ERROR_WRONG_IDENTIFIER;
122  }
123 
124  //Power up the internal PHY by clearing PHYPD
126  //Wait for the PHY to be ready
127  sleep(10);
128 
129  //Software reset
131  //Wait for the reset to complete
132  while((dm9000ReadReg(DM9000_REG_NCR) & NCR_RST) != 0)
133  {
134  }
135 
136  //PHY software reset
138  //Wait for the PHY reset to complete
140  {
141  }
142 
143  //Debug message
144  TRACE_INFO(" VID = 0x%04" PRIX16 "\r\n", vendorId);
145  TRACE_INFO(" PID = 0x%04" PRIX16 "\r\n", productId);
146  TRACE_INFO(" CHIPR = 0x%02" PRIX8 "\r\n", chipRevision);
147  TRACE_INFO(" PHYIDR1 = 0x%04" PRIX16 "\r\n", dm9000ReadPhyReg(DM9000_PHY_REG_PHYIDR1));
148  TRACE_INFO(" PHYIDR2 = 0x%04" PRIX16 "\r\n", dm9000ReadPhyReg(DM9000_PHY_REG_PHYIDR2));
149 
150  //Enable loopback mode?
151 #if (DM9000_LOOPBACK_MODE == ENABLED)
154 #endif
155 
156  //Set host MAC address
157  for(i = 0; i < 6; i++)
158  {
159  dm9000WriteReg(DM9000_REG_PAR0 + i, interface->macAddr.b[i]);
160  }
161 
162  //Initialize hash table
163  for(i = 0; i < 8; i++)
164  {
165  dm9000WriteReg(DM9000_REG_MAR0 + i, 0x00);
166  }
167 
168  //Always accept broadcast packets
170 
171  //Enable the Pointer Auto Return function
173  //Clear NSR status bits
175  //Clear interrupt flags
177  //Enable interrupts
179  //Enable the receiver by setting RXEN
181 
182  //Accept any packets from the upper layer
183  osSetEvent(&interface->nicTxEvent);
184 
185  //Force the TCP/IP stack to poll the link state at startup
186  interface->nicEvent = TRUE;
187  //Notify the TCP/IP stack of the event
189 
190  //Successful initialization
191  return NO_ERROR;
192 }
193 
194 
195 /**
196  * @brief DM9000 timer handler
197  * @param[in] interface Underlying network interface
198  **/
199 
200 void dm9000Tick(NetInterface *interface)
201 {
202 }
203 
204 
205 /**
206  * @brief Enable interrupts
207  * @param[in] interface Underlying network interface
208  **/
209 
211 {
212  //Enable interrupts
213  interface->extIntDriver->enableIrq();
214 }
215 
216 
217 /**
218  * @brief Disable interrupts
219  * @param[in] interface Underlying network interface
220  **/
221 
223 {
224  //Disable interrupts
225  interface->extIntDriver->disableIrq();
226 }
227 
228 
229 /**
230  * @brief DM9000 interrupt service routine
231  * @param[in] interface Underlying network interface
232  * @return TRUE if a higher priority task must be woken. Else FALSE is returned
233  **/
234 
236 {
237  bool_t flag;
238  uint8_t status;
239  uint8_t mask;
240  Dm9000Context *context;
241 
242  //This flag will be set if a higher priority task must be woken
243  flag = FALSE;
244 
245  //Point to the driver context
246  context = (Dm9000Context *) interface->nicContext;
247 
248  //Read interrupt status register
249  status = dm9000ReadReg(DM9000_REG_ISR);
250 
251  //Link status change?
252  if((status & ISR_LNKCHG) != 0)
253  {
254  //Read interrupt mask register
256  //Disable LNKCHGI interrupt
258 
259  //Set event flag
260  interface->nicEvent = TRUE;
261  //Notify the TCP/IP stack of the event
262  flag |= osSetEventFromIsr(&netEvent);
263  }
264 
265  //Packet transmission complete?
266  if((status & ISR_PT) != 0)
267  {
268  //Check TX complete status bits
270  {
271  //The transmission of the current packet is complete
272  if(context->queuedPackets > 0)
273  {
274  context->queuedPackets--;
275  }
276 
277  //Notify the TCP/IP stack that the transmitter is ready to send
278  flag |= osSetEventFromIsr(&interface->nicTxEvent);
279  }
280 
281  //Clear interrupt flag
283  }
284 
285  //Packet received?
286  if((status & ISR_PR) != 0)
287  {
288  //Read interrupt mask register
290  //Disable PRI interrupt
292 
293  //Set event flag
294  interface->nicEvent = TRUE;
295  //Notify the TCP/IP stack of the event
296  flag |= osSetEventFromIsr(&netEvent);
297  }
298 
299  //A higher priority task must be woken?
300  return flag;
301 }
302 
303 
304 /**
305  * @brief DM9000 event handler
306  * @param[in] interface Underlying network interface
307  **/
308 
310 {
311  error_t error;
312  uint8_t status;
313 
314  //Read interrupt status register
315  status = dm9000ReadReg(DM9000_REG_ISR);
316 
317  //Check whether the link status has changed?
318  if((status & ISR_LNKCHG) != 0)
319  {
320  //Clear interrupt flag
322  //Read network status register
323  status = dm9000ReadReg(DM9000_REG_NSR);
324 
325  //Check link state
326  if((status & NSR_LINKST) != 0)
327  {
328  //Get current speed
329  if((status & NSR_SPEED) != 0)
330  {
331  interface->linkSpeed = NIC_LINK_SPEED_10MBPS;
332  }
333  else
334  {
335  interface->linkSpeed = NIC_LINK_SPEED_100MBPS;
336  }
337 
338  //Read network control register
339  status = dm9000ReadReg(DM9000_REG_NCR);
340 
341  //Determine the new duplex mode
342  if((status & NCR_FDX) != 0)
343  {
344  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
345  }
346  else
347  {
348  interface->duplexMode = NIC_HALF_DUPLEX_MODE;
349  }
350 
351  //Link is up
352  interface->linkState = TRUE;
353  }
354  else
355  {
356  //Link is down
357  interface->linkState = FALSE;
358  }
359 
360  //Process link state change event
361  nicNotifyLinkChange(interface);
362  }
363 
364  //Check whether a packet has been received?
365  if((status & ISR_PR) != 0)
366  {
367  //Clear interrupt flag
369 
370  //Process all pending packets
371  do
372  {
373  //Read incoming packet
374  error = dm9000ReceivePacket(interface);
375 
376  //No more data in the receive buffer?
377  } while(error != ERROR_BUFFER_EMPTY);
378  }
379 
380  //Re-enable LNKCHGI and PRI interrupts
382 }
383 
384 
385 /**
386  * @brief Send a packet
387  * @param[in] interface Underlying network interface
388  * @param[in] buffer Multi-part buffer containing the data to send
389  * @param[in] offset Offset to the first data byte
390  * @param[in] ancillary Additional options passed to the stack along with
391  * the packet
392  * @return Error code
393  **/
394 
396  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
397 {
398  size_t i;
399  size_t length;
400  uint16_t *p;
401  Dm9000Context *context;
402 
403  //Point to the driver context
404  context = (Dm9000Context *) interface->nicContext;
405 
406  //Retrieve the length of the packet
407  length = netBufferGetLength(buffer) - offset;
408 
409  //Check the frame length
411  {
412  //The transmitter can accept another packet
413  osSetEvent(&interface->nicTxEvent);
414  //Report an error
415  return ERROR_INVALID_LENGTH;
416  }
417 
418  //Copy user data
419  netBufferRead(context->txBuffer, buffer, offset, length);
420 
421  //A dummy write is required before accessing FIFO
423  //Select MWCMD register
425 
426  //Point to the beginning of the buffer
427  p = (uint16_t *) context->txBuffer;
428 
429  //Write data to the FIFO using 16-bit mode
430  for(i = length; i > 1; i -= 2)
431  {
432  DM9000_DATA_REG = *(p++);
433  }
434 
435  //Odd number of bytes?
436  if(i > 0)
437  {
438  DM9000_DATA_REG = *((uint8_t *) p);
439  }
440 
441  //Write the number of bytes to send
444 
445  //Clear interrupt flag
447  //Start data transfer
449 
450  //The packet was successfully written to FIFO
451  context->queuedPackets++;
452 
453  //Successful processing
454  return NO_ERROR;
455 }
456 
457 
458 /**
459  * @brief Receive a packet
460  * @param[in] interface Underlying network interface
461  * @return Error code
462  **/
463 
465 {
466  error_t error;
467  size_t i;
468  size_t n;
469  size_t length;
470  volatile uint8_t status;
471  volatile uint16_t data;
472  Dm9000Context *context;
473 
474  //Point to the driver context
475  context = (Dm9000Context *) interface->nicContext;
476 
477  //A dummy read is required before accessing the 4-byte header
479 
480  //Select MRCMDX1 register
482  //Read the first byte of the header
483  status = LSB(DM9000_DATA_REG);
484 
485  //The first byte indicates if a packet has been received
486  if(status == 0x01)
487  {
488  //Select MRCMD register
490  //The second byte is the RX status byte
491  status = MSB(DM9000_DATA_REG);
492 
493  //Retrieve packet length
495  //Limit the number of data to read
497 
498  //Point to the beginning of the buffer
499  i = 0;
500 
501  //Make sure no error occurred
502  if(!(status & (RSR_LCS | RSR_RWTO | RSR_PLE | RSR_AE | RSR_CE | RSR_FOE)))
503  {
504  //Read data from FIFO using 16-bit mode
505  while((i + 1) < n)
506  {
508  context->rxBuffer[i++] = LSB(data);
509  context->rxBuffer[i++] = MSB(data);
510  }
511 
512  //Odd number of bytes to read?
513  if((i + 1) == n)
514  {
516  context->rxBuffer[i] = LSB(data);
517  i += 2;
518  }
519 
520  //Valid packet received
521  error = NO_ERROR;
522  }
523  else
524  {
525  //The received packet contains an error
526  error = ERROR_INVALID_PACKET;
527  }
528 
529  //Flush remaining bytes
530  while(i < length)
531  {
533  i += 2;
534  }
535  }
536  else
537  {
538  //No more data in the receive buffer
539  error = ERROR_BUFFER_EMPTY;
540  }
541 
542  //Check whether a valid packet has been received
543  if(!error)
544  {
545  NetRxAncillary ancillary;
546 
547  //Additional options can be passed to the stack along with the packet
548  ancillary = NET_DEFAULT_RX_ANCILLARY;
549 
550  //Pass the packet to the upper layer
551  nicProcessPacket(interface, context->rxBuffer, n, &ancillary);
552  }
553 
554  //Return status code
555  return error;
556 }
557 
558 
559 /**
560  * @brief Configure MAC address filtering
561  * @param[in] interface Underlying network interface
562  * @return Error code
563  **/
564 
566 {
567  uint_t i;
568  uint_t k;
569  uint32_t crc;
570  uint8_t hashTable[8];
571  MacFilterEntry *entry;
572 
573  //Debug message
574  TRACE_DEBUG("Updating MAC filter...\r\n");
575 
576  //Clear hash table
577  osMemset(hashTable, 0, sizeof(hashTable));
578  //Always accept broadcast packets regardless of the MAC filter table
579  hashTable[7] = 0x80;
580 
581  //The MAC address filter contains the list of MAC addresses to accept
582  //when receiving an Ethernet frame
583  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
584  {
585  //Point to the current entry
586  entry = &interface->macAddrFilter[i];
587 
588  //Valid entry?
589  if(entry->refCount > 0)
590  {
591  //Compute CRC over the current MAC address
592  crc = dm9000CalcCrc(&entry->addr, sizeof(MacAddr));
593  //Calculate the corresponding index in the table
594  k = crc & 0x3F;
595  //Update hash table contents
596  hashTable[k / 8] |= (1 << (k % 8));
597  }
598  }
599 
600  //Write the hash table to the DM9000 controller
601  for(i = 0; i < 8; i++)
602  {
603  dm9000WriteReg(DM9000_REG_MAR0 + i, hashTable[i]);
604  }
605 
606  //Debug message
607  TRACE_DEBUG(" MAR = %02" PRIX8 " %02" PRIX8 " %02" PRIX8 " %02" PRIX8 " "
608  "%02" PRIX8 " %02" PRIX8 " %02" PRIX8 " %02" PRIX8 "\r\n",
613 
614  //Successful processing
615  return NO_ERROR;
616 }
617 
618 
619 /**
620  * @brief Write DM9000 register
621  * @param[in] address Register address
622  * @param[in] data Register value
623  **/
624 
625 void dm9000WriteReg(uint8_t address, uint8_t data)
626 {
627  //Write register address to INDEX register
629  //Write register value to DATA register
631 }
632 
633 
634 /**
635  * @brief Read DM9000 register
636  * @param[in] address Register address
637  * @return Register value
638  **/
639 
640 uint8_t dm9000ReadReg(uint8_t address)
641 {
642  //Write register address to INDEX register
644  //Read register value from DATA register
645  return DM9000_DATA_REG;
646 }
647 
648 
649 /**
650  * @brief Write DM9000 PHY register
651  * @param[in] address PHY register address
652  * @param[in] data Register value
653  **/
654 
655 void dm9000WritePhyReg(uint8_t address, uint16_t data)
656 {
657  //Write PHY register address
659  //Write register value
662 
663  //Start the write operation
665  //PHY access is still in progress?
666  while((dm9000ReadReg(DM9000_REG_EPCR) & EPCR_ERRE) != 0)
667  {
668  }
669 
670  //Wait 5us minimum
671  usleep(5);
672  //Clear command register
674 }
675 
676 
677 /**
678  * @brief Read DM9000 PHY register
679  * @param[in] address PHY register address
680  * @return Register value
681  **/
682 
683 uint16_t dm9000ReadPhyReg(uint8_t address)
684 {
685  //Write PHY register address
687 
688  //Start the read operation
690  //PHY access is still in progress?
691  while((dm9000ReadReg(DM9000_REG_EPCR) & EPCR_ERRE) != 0)
692  {
693  }
694 
695  //Clear command register
697  //Wait 5us minimum
698  usleep(5);
699 
700  //Return register value
702 }
703 
704 
705 /**
706  * @brief CRC calculation
707  * @param[in] data Pointer to the data over which to calculate the CRC
708  * @param[in] length Number of bytes to process
709  * @return Resulting CRC value
710  **/
711 
712 uint32_t dm9000CalcCrc(const void *data, size_t length)
713 {
714  uint_t i;
715  uint_t j;
716  uint32_t crc;
717  const uint8_t *p;
718 
719  //Point to the data over which to calculate the CRC
720  p = (uint8_t *) data;
721  //CRC preset value
722  crc = 0xFFFFFFFF;
723 
724  //Loop through data
725  for(i = 0; i < length; i++)
726  {
727  //Update CRC value
728  crc ^= p[i];
729  //The message is processed bit by bit
730  for(j = 0; j < 8; j++)
731  {
732  if((crc & 0x01) != 0)
733  {
734  crc = (crc >> 1) ^ 0xEDB88320;
735  }
736  else
737  {
738  crc = crc >> 1;
739  }
740  }
741  }
742 
743  //Return CRC value
744  return crc;
745 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void nicNotifyLinkChange(NetInterface *interface)
Process link state change notification.
Definition: nic.c:532
void dm9000WritePhyReg(uint8_t address, uint16_t data)
Write DM9000 PHY register.
error_t dm9000UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint8_t length
Definition: coap_common.h:190
#define usleep(delay)
Definition: os_port.h:247
#define DM9000_REG_IMR
int bool_t
Definition: compiler_port.h:49
#define DM9000B_CHIP_REV
Definition: dm9000_driver.h:66
#define RSR_AE
#define netEvent
Definition: net_legacy.h:267
#define NSR_LINKST
#define DM9000_INDEX_REG
Definition: dm9000_driver.h:46
void dm9000WriteReg(uint8_t address, uint8_t data)
Write DM9000 register.
void memPoolFree(void *p)
Release a memory block.
Definition: net_mem.c:166
uint8_t data[]
Definition: ethernet.h:209
uint8_t * rxBuffer
Receive buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define DM9000_REG_MAR0
Definition: dm9000_driver.h:91
#define DM9000_REG_MAR4
Definition: dm9000_driver.h:95
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define RSR_RWTO
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
#define sleep(delay)
Definition: os_port.h:251
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:103
__start_packed struct @5 MacAddr
MAC address.
#define DM9000_VID
Definition: dm9000_driver.h:63
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
#define BMCR_SPEED_SEL
#define DM9000_REG_PAR0
Definition: dm9000_driver.h:85
#define RCR_RXEN
#define RCR_DIS_CRC
#define DM9000_REG_MAR2
Definition: dm9000_driver.h:93
void * memPoolAlloc(size_t size)
Allocate a memory block.
Definition: net_mem.c:100
void dm9000Tick(NetInterface *interface)
DM9000 timer handler.
#define DM9000_LBK_PHY
#define RSR_LCS
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define RSR_CE
#define DM9000_REG_VIDL
#define NSR_TX2END
#define DM9000_REG_NSR
Definition: dm9000_driver.h:70
#define ISR_LNKCHG
#define NSR_WAKEST
#define RCR_DIS_LONG
Ethernet.
uint32_t dm9000CalcCrc(const void *data, size_t length)
CRC calculation.
error_t dm9000Init(NetInterface *interface)
DM9000 controller initialization.
Definition: dm9000_driver.c:72
#define EPCR_ERPRW
#define ISR_ROO
#define DM9000_REG_RCR
Definition: dm9000_driver.h:74
#define DM9000_REG_MAR6
Definition: dm9000_driver.h:97
#define RSR_FOE
#define FALSE
Definition: os_port.h:46
#define DM9000_REG_PIDH
#define BMCR_DUPLEX_MODE
#define DM9000_REG_MRCMDX1
#define ISR_UDRUN
error_t
Error codes.
Definition: error.h:42
error_t dm9000ReceivePacket(NetInterface *interface)
Receive a packet.
error_t dm9000SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
#define DM9000_DATA_REG
Definition: dm9000_driver.h:51
#define NSR_TX1END
#define EPCR_EPOS
uint16_t dm9000ReadPhyReg(uint8_t address)
Read DM9000 PHY register.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
#define IMR_PAR
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:248
#define DM9000_REG_TXPLH
#define NCR_RST
#define NetTxAncillary
Definition: net_misc.h:36
uint8_t mask
Definition: web_socket.h:317
#define MSB(x)
Definition: os_port.h:58
#define DM9000_REG_GPR
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define LSB(x)
Definition: os_port.h:54
#define DM9000_REG_TXPLL
#define DM9000_REG_EPCR
Definition: dm9000_driver.h:80
#define DM9000_REG_ISR
#define NSR_SPEED
#define MIN(a, b)
Definition: os_port.h:62
#define IMR_PRI
#define DM9000_REG_EPAR
Definition: dm9000_driver.h:81
#define EPCR_ERPRR
#define DM9000_REG_MWCMD
#define DM9000_REG_MRCMDX
#define DM9000_REG_EPDRH
Definition: dm9000_driver.h:83
uint8_t dm9000ReadReg(uint8_t address)
Read DM9000 register.
#define NCR_FDX
#define DM9000A_CHIP_REV
Definition: dm9000_driver.h:65
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define DM9000_REG_CHIPR
#define DM9000_REG_MAR1
Definition: dm9000_driver.h:92
#define DM9000_REG_MWCMDX
#define IMR_LNKCHGI
#define ETH_MTU
Definition: ethernet.h:105
#define DM9000_REG_MAR3
Definition: dm9000_driver.h:94
uint8_t n
MAC filter table entry.
Definition: ethernet.h:246
#define DM9000_PHY_REG_PHYIDR1
void dm9000DisableIrq(NetInterface *interface)
Disable interrupts.
#define BMCR_LOOPBACK
uint8_t * txBuffer
Transmit buffer.
#define DM9000_REG_TCR
Definition: dm9000_driver.h:71
DM9000A/B Ethernet controller.
#define BMCR_RST
void dm9000EventHandler(NetInterface *interface)
DM9000 event handler.
#define DM9000_REG_EPDRL
Definition: dm9000_driver.h:82
#define DM9000_REG_MAR5
Definition: dm9000_driver.h:96
Ipv6Addr address
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
bool_t dm9000IrqHandler(NetInterface *interface)
DM9000 interrupt service routine.
#define IMR_PTI
#define DM9000_REG_VIDH
#define ISR_PR
DM9000 driver context.
#define DM9000_PHY_REG_PHYIDR2
#define TCR_TXREQ
#define DM9000_PID
Definition: dm9000_driver.h:64
#define DM9000_REG_PIDL
#define ISR_ROS
unsigned int uint_t
Definition: compiler_port.h:45
#define osMemset(p, value, length)
Definition: os_port.h:128
TCP/IP stack core.
#define DM9000_PHY_REG_BMCR
NIC driver.
Definition: nic.h:257
#define DM9000_REG_MAR7
Definition: dm9000_driver.h:98
#define BMCR_AN_EN
#define EPCR_ERRE
#define RSR_PLE
#define DM9000_REG_NCR
Definition: dm9000_driver.h:69
const NicDriver dm9000Driver
DM9000 driver.
Definition: dm9000_driver.c:45
uint_t queuedPackets
Number of packets in transmission buffer.
void dm9000EnableIrq(NetInterface *interface)
Enable interrupts.
#define ISR_PT
Success.
Definition: error.h:44
Debugging facilities.
#define DM9000_REG_MRCMD
Ethernet interface.
Definition: nic.h:82