dm9161_driver.h
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1 /**
2  * @file dm9161_driver.h
3  * @brief DM9161 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _DM9161_DRIVER_H
32 #define _DM9161_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //PHY address
38 #ifndef DM9161_PHY_ADDR
39  #define DM9161_PHY_ADDR 0
40 #elif (DM9161_PHY_ADDR < 0 || DM9161_PHY_ADDR > 31)
41  #error DM9161_PHY_ADDR parameter is not valid
42 #endif
43 
44 //DM9161 PHY registers
45 #define DM9161_BMCR 0x00
46 #define DM9161_BMSR 0x01
47 #define DM9161_PHYID1 0x02
48 #define DM9161_PHYID2 0x03
49 #define DM9161_ANAR 0x04
50 #define DM9161_ANLPAR 0x05
51 #define DM9161_ANER 0x06
52 #define DM9161_DSCR 0x10
53 #define DM9161_DSCSR 0x11
54 #define DM9161_10BTCSR 0x12
55 #define DM9161_MDINTR 0x15
56 #define DM9161_RECR 0x16
57 #define DM9161_DISCR 0x17
58 #define DM9161_RLSR 0x18
59 
60 //Basic Mode Control register
61 #define DM9161_BMCR_RESET 0x8000
62 #define DM9161_BMCR_LOOPBACK 0x4000
63 #define DM9161_BMCR_SPEED_SEL 0x2000
64 #define DM9161_BMCR_AN_EN 0x1000
65 #define DM9161_BMCR_POWER_DOWN 0x0800
66 #define DM9161_BMCR_ISOLATE 0x0400
67 #define DM9161_BMCR_RESTART_AN 0x0200
68 #define DM9161_BMCR_DUPLEX_MODE 0x0100
69 #define DM9161_BMCR_COL_TEST 0x0080
70 
71 //Basic Mode Status register
72 #define DM9161_BMSR_100BT4 0x8000
73 #define DM9161_BMSR_100BTX_FD 0x4000
74 #define DM9161_BMSR_100BTX_HD 0x2000
75 #define DM9161_BMSR_10BT_FD 0x1000
76 #define DM9161_BMSR_10BT_HD 0x0800
77 #define DM9161_BMSR_MF_PREAMBLE_SUPPR 0x0040
78 #define DM9161_BMSR_AN_COMPLETE 0x0020
79 #define DM9161_BMSR_REMOTE_FAULT 0x0010
80 #define DM9161_BMSR_AN_CAPABLE 0x0008
81 #define DM9161_BMSR_LINK_STATUS 0x0004
82 #define DM9161_BMSR_JABBER_DETECT 0x0002
83 #define DM9161_BMSR_EXTENDED_CAPABLE 0x0001
84 
85 //PHY Identifier 1 register
86 #define DM9161_PHYID1_OUI_MSB 0xFFFF
87 #define DM9161_PHYID1_OUI_MSB_DEFAULT 0x0181
88 
89 //PHY Identifier 2 register
90 #define DM9161_PHYID2_OUI_LSB 0xFC00
91 #define DM9161_PHYID2_OUI_LSB_DEFAULT 0xB800
92 #define DM9161_PHYID2_VNDR_MDL 0x03F0
93 #define DM9161_PHYID2_VNDR_MDL_DEFAULT 0x0080
94 #define DM9161_PHYID2_MDL_REV 0x000F
95 
96 //Auto-Negotiation Advertisement register
97 #define DM9161_ANAR_NEXT_PAGE 0x8000
98 #define DM9161_ANAR_ACK 0x4000
99 #define DM9161_ANAR_REMOTE_FAULT 0x2000
100 #define DM9161_ANAR_FCS 0x0400
101 #define DM9161_ANAR_100BT4 0x0200
102 #define DM9161_ANAR_100BTX_FD 0x0100
103 #define DM9161_ANAR_100BTX_HD 0x0080
104 #define DM9161_ANAR_10BT_FD 0x0040
105 #define DM9161_ANAR_10BT_HD 0x0020
106 #define DM9161_ANAR_SELECTOR 0x001F
107 #define DM9161_ANAR_SELECTOR_DEFAULT 0x0001
108 
109 //Auto-Negotiation Link Partner Ability register
110 #define DM9161_ANLPAR_NEXT_PAGE 0x8000
111 #define DM9161_ANLPAR_ACK 0x4000
112 #define DM9161_ANLPAR_REMOTE_FAULT 0x2000
113 #define DM9161_ANLPAR_FCS 0x0400
114 #define DM9161_ANLPAR_100BT4 0x0200
115 #define DM9161_ANLPAR_100BTX_FD 0x0100
116 #define DM9161_ANLPAR_100BTX_HD 0x0080
117 #define DM9161_ANLPAR_10BT_FD 0x0040
118 #define DM9161_ANLPAR_10BT_HD 0x0020
119 #define DM9161_ANLPAR_SELECTOR 0x001F
120 #define DM9161_ANLPAR_SELECTOR_DEFAULT 0x0001
121 
122 //Auto-Negotiation Expansion register
123 #define DM9161_ANER_PAR_DETECT_FAULT 0x0010
124 #define DM9161_ANER_LP_NP_ABLE 0x0008
125 #define DM9161_ANER_NP_ABLE 0x0004
126 #define DM9161_ANER_PAGE_RX 0x0002
127 #define DM9161_ANER_LP_AN_ABLE 0x0001
128 
129 //DAVICOM Specified Configuration register
130 #define DM9161_DSCR_BP_4B5B 0x8000
131 #define DM9161_DSCR_BP_SCR 0x4000
132 #define DM9161_DSCR_BP_ALIGN 0x2000
133 #define DM9161_DSCR_BP_ADPOK 0x1000
134 #define DM9161_DSCR_REPEATER 0x0800
135 #define DM9161_DSCR_TX 0x0400
136 #define DM9161_DSCR_FEF 0x0200
137 #define DM9161_DSCR_RMII_EN 0x0100
138 #define DM9161_DSCR_F_LINK_100 0x0080
139 #define DM9161_DSCR_SPLED_CTL 0x0040
140 #define DM9161_DSCR_COLLED_CTL 0x0020
141 #define DM9161_DSCR_RPDCTR_EN 0x0010
142 #define DM9161_DSCR_SMRST 0x0008
143 #define DM9161_DSCR_MFPSC 0x0004
144 #define DM9161_DSCR_SLEEP 0x0002
145 #define DM9161_DSCR_RLOUT 0x0001
146 
147 //DAVICOM Specified Configuration and Status register
148 #define DM9161_DSCSR_100FDX 0x8000
149 #define DM9161_DSCSR_100HDX 0x4000
150 #define DM9161_DSCSR_10FDX 0x2000
151 #define DM9161_DSCSR_10HDX 0x1000
152 #define DM9161_DSCSR_PHYADR 0x01F0
153 #define DM9161_DSCSR_ANMB 0x000F
154 #define DM9161_DSCSR_ANMB_IDLE 0x0000
155 #define DM9161_DSCSR_ANMB_ABILITY_MATCH 0x0001
156 #define DM9161_DSCSR_ANMB_ACK_MATCH 0x0002
157 #define DM9161_DSCSR_ANMB_ACK_MATCH_FAIL 0x0003
158 #define DM9161_DSCSR_ANMB_CONSIST_MATCH 0x0004
159 #define DM9161_DSCSR_ANMB_CONSIST_MATCH_FAIL 0x0005
160 #define DM9161_DSCSR_ANMB_LINK_READY 0x0006
161 #define DM9161_DSCSR_ANMB_LINK_READY_FAIL 0x0007
162 #define DM9161_DSCSR_ANMB_AN_COMPLETE 0x0008
163 
164 //10BASE-T Configuration/Status register
165 #define DM9161_10BTCSR_LP_EN 0x4000
166 #define DM9161_10BTCSR_HBE 0x2000
167 #define DM9161_10BTCSR_SQUELCH 0x1000
168 #define DM9161_10BTCSR_JABEN 0x0800
169 #define DM9161_10BTCSR_10BT_SER 0x0400
170 #define DM9161_10BTCSR_POLR 0x0001
171 
172 //DAVICOM Specified Interrupt register
173 #define DM9161_MDINTR_INTR_PEND 0x8000
174 #define DM9161_MDINTR_FDX_MASK 0x0800
175 #define DM9161_MDINTR_SPD_MASK 0x0400
176 #define DM9161_MDINTR_LINK_MASK 0x0200
177 #define DM9161_MDINTR_INTR_MASK 0x0100
178 #define DM9161_MDINTR_FDX_CHANGE 0x0010
179 #define DM9161_MDINTR_SPD_CHANGE 0x0008
180 #define DM9161_MDINTR_LINK_CHANGE 0x0004
181 #define DM9161_MDINTR_INTR_STATUS 0x0001
182 
183 //DAVICOM Specified Disconnect Counter register
184 #define DM9161_DISCR_DISCONNECT_COUNT 0x00FF
185 
186 //DAVICOM Hardware Reset Latch State register
187 #define DM9161_RLSR_LH_LEDST 0x2000
188 #define DM9161_RLSR_LH_CSTS 0x1000
189 #define DM9161_RLSR_LH_RMII 0x0800
190 #define DM9161_RLSR_LH_SCRAM 0x0400
191 #define DM9161_RLSR_LH_REPTR 0x0200
192 #define DM9161_RLSR_LH_TSTMOD 0x0100
193 #define DM9161_RLSR_LH_OP 0x00E0
194 #define DM9161_RLSR_LH_PH 0x001F
195 
196 //C++ guard
197 #ifdef __cplusplus
198 extern "C" {
199 #endif
200 
201 //DM9161 Ethernet PHY driver
202 extern const PhyDriver dm9161PhyDriver;
203 
204 //DM9161 related functions
205 error_t dm9161Init(NetInterface *interface);
206 
207 void dm9161Tick(NetInterface *interface);
208 
209 void dm9161EnableIrq(NetInterface *interface);
210 void dm9161DisableIrq(NetInterface *interface);
211 
212 void dm9161EventHandler(NetInterface *interface);
213 
214 void dm9161WritePhyReg(NetInterface *interface, uint8_t address,
215  uint16_t data);
216 
217 uint16_t dm9161ReadPhyReg(NetInterface *interface, uint8_t address);
218 
219 void dm9161DumpPhyReg(NetInterface *interface);
220 
221 //C++ guard
222 #ifdef __cplusplus
223 }
224 #endif
225 
226 #endif
error_t dm9161Init(NetInterface *interface)
DM9161 PHY transceiver initialization.
Definition: dm9161_driver.c:62
PHY driver.
Definition: nic.h:214
void dm9161WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
uint16_t dm9161ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
void dm9161EventHandler(NetInterface *interface)
DM9161 event handler.
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
const PhyDriver dm9161PhyDriver
DM9161 Ethernet PHY driver.
Definition: dm9161_driver.c:44
void dm9161DisableIrq(NetInterface *interface)
Disable interrupts.
Network interface controller abstraction layer.
Ipv6Addr address
uint8_t data[]
Definition: dtls_misc.h:176
void dm9161Tick(NetInterface *interface)
DM9161 timer handler.
void dm9161EnableIrq(NetInterface *interface)
Enable interrupts.
void dm9161DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.