dm9161_driver.h
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1 /**
2  * @file dm9161_driver.h
3  * @brief DM9161 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _DM9161_DRIVER_H
30 #define _DM9161_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef DM9161_PHY_ADDR
37  #define DM9161_PHY_ADDR 0
38 #elif (DM9161_PHY_ADDR < 0 || DM9161_PHY_ADDR > 31)
39  #error DM9161_PHY_ADDR parameter is not valid
40 #endif
41 
42 //DM9161 registers
43 #define DM9161_PHY_REG_BMCR 0x00
44 #define DM9161_PHY_REG_BMSR 0x01
45 #define DM9161_PHY_REG_PHYIDR1 0x02
46 #define DM9161_PHY_REG_PHYIDR2 0x03
47 #define DM9161_PHY_REG_ANAR 0x04
48 #define DM9161_PHY_REG_ANLPAR 0x05
49 #define DM9161_PHY_REG_ANER 0x06
50 #define DM9161_PHY_REG_DSCR 0x10
51 #define DM9161_PHY_REG_DSCSR 0x11
52 #define DM9161_PHY_REG_10BTCSR 0x12
53 #define DM9161_PHY_REG_MDINTR 0x15
54 #define DM9161_PHY_REG_RECR 0x16
55 #define DM9161_PHY_REG_DISCR 0x17
56 #define DM9161_PHY_REG_RLSR 0x18
57 
58 //BMCR register
59 #define BMCR_RESET (1 << 15)
60 #define BMCR_LOOPBACK (1 << 14)
61 #define BMCR_SPEED_SEL (1 << 13)
62 #define BMCR_AN_EN (1 << 12)
63 #define BMCR_POWER_DOWN (1 << 11)
64 #define BMCR_ISOLATE (1 << 10)
65 #define BMCR_RESTART_AN (1 << 9)
66 #define BMCR_DUPLEX_MODE (1 << 8)
67 #define BMCR_COL_TEST (1 << 7)
68 
69 //BMSR register
70 #define BMSR_100BT4 (1 << 15)
71 #define BMSR_100BTX_FD (1 << 14)
72 #define BMSR_100BTX (1 << 13)
73 #define BMSR_10BT_FD (1 << 12)
74 #define BMSR_10BT (1 << 11)
75 #define BMSR_NO_PREAMBLE (1 << 6)
76 #define BMSR_AN_COMPLETE (1 << 5)
77 #define BMSR_REMOTE_FAULT (1 << 4)
78 #define BMSR_AN_ABLE (1 << 3)
79 #define BMSR_LINK_STATUS (1 << 2)
80 #define BMSR_JABBER_DETECT (1 << 1)
81 #define BMSR_EXTENDED_CAP (1 << 0)
82 
83 //ANAR register
84 #define ANAR_NP (1 << 15)
85 #define ANAR_ACK (1 << 14)
86 #define ANAR_RF (1 << 13)
87 #define ANAR_FCS (1 << 10)
88 #define ANAR_100BT4 (1 << 9)
89 #define ANAR_100BTX_FD (1 << 8)
90 #define ANAR_100BTX (1 << 7)
91 #define ANAR_10BT_FD (1 << 6)
92 #define ANAR_10BT (1 << 5)
93 #define ANAR_SELECTOR4 (1 << 4)
94 #define ANAR_SELECTOR3 (1 << 3)
95 #define ANAR_SELECTOR2 (1 << 2)
96 #define ANAR_SELECTOR1 (1 << 1)
97 #define ANAR_SELECTOR0 (1 << 0)
98 
99 //ANLPAR register
100 #define ANLPAR_NP (1 << 15)
101 #define ANLPAR_ACK (1 << 14)
102 #define ANLPAR_RF (1 << 13)
103 #define ANLPAR_FCS (1 << 10)
104 #define ANLPAR_100BT4 (1 << 9)
105 #define ANLPAR_100BTX_FD (1 << 8)
106 #define ANLPAR_100BTX (1 << 7)
107 #define ANLPAR_10BT_FD (1 << 6)
108 #define ANLPAR_10BT (1 << 5)
109 #define ANLPAR_SELECTOR4 (1 << 4)
110 #define ANLPAR_SELECTOR3 (1 << 3)
111 #define ANLPAR_SELECTOR2 (1 << 2)
112 #define ANLPAR_SELECTOR1 (1 << 1)
113 #define ANLPAR_SELECTOR0 (1 << 0)
114 
115 //ANER register
116 #define ANER_PDF (1 << 4)
117 #define ANER_LP_NP_ABLE (1 << 3)
118 #define ANER_NP_ABLE (1 << 2)
119 #define ANER_PAGE_RX (1 << 1)
120 #define ANER_LP_AN_ABLE (1 << 0)
121 
122 //DSCR register
123 #define DSCR_BP_4B5B (1 << 15)
124 #define DSCR_BP_SCR (1 << 14)
125 #define DSCR_BP_ALIGN (1 << 13)
126 #define DSCR_BP_ADPOK (1 << 12)
127 #define DSCR_REPEATER (1 << 11)
128 #define DSCR_TX (1 << 10)
129 #define DSCR_FEF (1 << 9)
130 #define DSCR_RMII_EN (1 << 8)
131 #define DSCR_F_LINK_100 (1 << 7)
132 #define DSCR_SPLED_CTL (1 << 6)
133 #define DSCR_COLLED_CTL (1 << 5)
134 #define DSCR_RPDCTR_EN (1 << 4)
135 #define DSCR_SMRST (1 << 3)
136 #define DSCR_MFPSC (1 << 2)
137 #define DSCR_SLEEP (1 << 1)
138 #define DSCR_RLOUT (1 << 0)
139 
140 //DSCSR register
141 #define DSCSR_100FDX (1 << 15)
142 #define DSCSR_100HDX (1 << 14)
143 #define DSCSR_10FDX (1 << 13)
144 #define DSCSR_10HDX (1 << 12)
145 #define DSCSR_PHYADR4 (1 << 8)
146 #define DSCSR_PHYADR3 (1 << 7)
147 #define DSCSR_PHYADR2 (1 << 6)
148 #define DSCSR_PHYADR1 (1 << 5)
149 #define DSCSR_PHYADR0 (1 << 4)
150 #define DSCSR_ANMB3 (1 << 3)
151 #define DSCSR_ANMB2 (1 << 2)
152 #define DSCSR_ANMB1 (1 << 1)
153 #define DSCSR_ANMB0 (1 << 0)
154 
155 //10BTCSR register
156 #define _10BTCSR_LP_EN (1 << 14)
157 #define _10BTCSR_HBE (1 << 13)
158 #define _10BTCSR_SQUELCH (1 << 12)
159 #define _10BTCSR_JABEN (1 << 11)
160 #define _10BTCSR_10BT_SER (1 << 10)
161 #define _10BTCSR_POLR (1 << 0)
162 
163 //MDINTR register
164 #define MDINTR_INTR_PEND (1 << 15)
165 #define MDINTR_FDX_MASK (1 << 11)
166 #define MDINTR_SPD_MASK (1 << 10)
167 #define MDINTR_LINK_MASK (1 << 9)
168 #define MDINTR_INTR_MASK (1 << 8)
169 #define MDINTR_FDX_CHANGE (1 << 4)
170 #define MDINTR_SPD_CHANGE (1 << 3)
171 #define MDINTR_LINK_CHANGE (1 << 2)
172 #define MDINTR_INTR_STATUS (1 << 0)
173 
174 //RLSR register
175 #define RLSR_LH_LEDST (1 << 13)
176 #define RLSR_LH_CSTS (1 << 12)
177 #define RLSR_LH_RMII (1 << 11)
178 #define RLSR_LH_SCRAM (1 << 10)
179 #define RLSR_LH_REPTR (1 << 9)
180 #define RLSR_LH_TSTMOD (1 << 8)
181 #define RLSR_LH_OP2 (1 << 7)
182 #define RLSR_LH_OP1 (1 << 6)
183 #define RLSR_LH_OP0 (1 << 5)
184 #define RLSR_LH_PH4 (1 << 4)
185 #define RLSR_LH_PH3 (1 << 3)
186 #define RLSR_LH_PH2 (1 << 2)
187 #define RLSR_LH_PH1 (1 << 1)
188 #define RLSR_LH_PH0 (1 << 0)
189 
190 //Auto-negotiation state machine
191 #define DSCSR_ANMB_MASK 0x000F
192 #define DSCSR_ANMB_IDLE 0x0000
193 #define DSCSR_ANMB_ABILITY_MATCH 0x0001
194 #define DSCSR_ANMB_ACK_MATCH 0x0002
195 #define DSCSR_ANMB_ACK_MATCH_FAILED 0x0003
196 #define DSCSR_ANMB_CONSIST_MATCH 0x0004
197 #define DSCSR_ANMB_CONSIST_MATCH_FAILED 0x0005
198 #define DSCSR_ANMB_SIGNAL_LINK_READY 0x0006
199 #define DSCSR_ANMB_SIGNAL_LINK_READY_FAILED 0x0007
200 #define DSCSR_ANMB_AN_SUCCESS 0x0008
201 
202 //C++ guard
203 #ifdef __cplusplus
204  extern "C" {
205 #endif
206 
207 //DM9161 Ethernet PHY driver
208 extern const PhyDriver dm9161PhyDriver;
209 
210 //DM9161 related functions
211 error_t dm9161Init(NetInterface *interface);
212 
213 void dm9161Tick(NetInterface *interface);
214 
215 void dm9161EnableIrq(NetInterface *interface);
216 void dm9161DisableIrq(NetInterface *interface);
217 
218 void dm9161EventHandler(NetInterface *interface);
219 
220 void dm9161WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
221 uint16_t dm9161ReadPhyReg(NetInterface *interface, uint8_t address);
222 
223 void dm9161DumpPhyReg(NetInterface *interface);
224 
225 //C++ guard
226 #ifdef __cplusplus
227  }
228 #endif
229 
230 #endif
void dm9161DisableIrq(NetInterface *interface)
Disable interrupts.
void dm9161Tick(NetInterface *interface)
DM9161 timer handler.
Definition: dm9161_driver.c:95
PHY driver.
Definition: nic.h:196
void dm9161EventHandler(NetInterface *interface)
DM9161 event handler.
error_t dm9161Init(NetInterface *interface)
DM9161 PHY transceiver initialization.
Definition: dm9161_driver.c:58
void dm9161EnableIrq(NetInterface *interface)
Enable interrupts.
void dm9161DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
Ipv6Addr address
uint16_t dm9161ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
error_t
Error codes.
Definition: error.h:40
const PhyDriver dm9161PhyDriver
DM9161 Ethernet PHY driver.
Definition: dm9161_driver.c:42
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void dm9161WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
Network interface controller abstraction layer.