dp83620_driver.h
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1 /**
2  * @file dp83620_driver.h
3  * @brief DP83620 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _DP83620_DRIVER_H
30 #define _DP83620_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef DP83620_PHY_ADDR
37  #define DP83620_PHY_ADDR 1
38 #elif (DP83620_PHY_ADDR < 0 || DP83620_PHY_ADDR > 31)
39  #error DP83620_PHY_ADDR parameter is not valid
40 #endif
41 
42 //DP83620 registers
43 #define DP83620_PHY_REG_BMCR 0x00
44 #define DP83620_PHY_REG_BMSR 0x01
45 #define DP83620_PHY_REG_PHYIDR1 0x02
46 #define DP83620_PHY_REG_PHYIDR2 0x03
47 #define DP83620_PHY_REG_ANAR 0x04
48 #define DP83620_PHY_REG_ANLPAR 0x05
49 #define DP83620_PHY_REG_ANER 0x06
50 #define DP83620_PHY_REG_ANNPTR 0x07
51 #define DP83620_PHY_REG_PHYSTS 0x10
52 #define DP83620_PHY_REG_MICR 0x11
53 #define DP83620_PHY_REG_MISR 0x12
54 #define DP83620_PHY_REG_PAGESEL 0x13
55 
56 //Extended registers (page 0)
57 #define DP83620_PHY_REG_FCSCR 0x14
58 #define DP83620_PHY_REG_RECR 0x15
59 #define DP83620_PHY_REG_PCSR 0x16
60 #define DP83620_PHY_REG_RBR 0x17
61 #define DP83620_PHY_REG_LEDCR 0x18
62 #define DP83620_PHY_REG_PHYCR 0x19
63 #define DP83620_PHY_REG_10BTSCR 0x1A
64 #define DP83620_PHY_REG_CDCTRL1 0x1B
65 #define DP83620_PHY_REG_PHYCR2 0x1C
66 #define DP83620_PHY_REG_EDCR 0x1D
67 #define DP83620_PHY_REG_PCFCR 0x1F
68 
69 //Extended registers (page 1)
70 #define DP83620_PHY_REG_SD_CNFG 0x1E
71 
72 //Extended registers (page 2)
73 #define DP83620_PHY_REG_LEN100_DET 0x14
74 #define DP83620_PHY_REG_FREQ100 0x15
75 #define DP83620_PHY_REG_TDR_CTRL 0x16
76 #define DP83620_PHY_REG_TDR_WIN 0x17
77 #define DP83620_PHY_REG_TDR_PEAK 0x18
78 #define DP83620_PHY_REG_TDR_THR 0x19
79 #define DP83620_PHY_REG_VAR_CTRL 0x1A
80 #define DP83620_PHY_REG_VAR_DAT 0x1B
81 #define DP83620_PHY_REG_LQMR 0x1D
82 #define DP83620_PHY_REG_LQDR 0x1E
83 #define DP83620_PHY_REG_LQMR2 0x1F
84 
85 //Extended registers (page 5)
86 #define DP83620_PHY_REG_PSF_CFG 0x18
87 
88 //BMCR register
89 #define BMCR_RESET (1 << 15)
90 #define BMCR_LOOPBACK (1 << 14)
91 #define BMCR_SPEED_SEL (1 << 13)
92 #define BMCR_AN_EN (1 << 12)
93 #define BMCR_POWER_DOWN (1 << 11)
94 #define BMCR_ISOLATE (1 << 10)
95 #define BMCR_RESTART_AN (1 << 9)
96 #define BMCR_DUPLEX_MODE (1 << 8)
97 #define BMCR_COL_TEST (1 << 7)
98 #define BMCR_UNIDIRECTIONAL_EN (1 << 5)
99 
100 //BMSR register
101 #define BMSR_100BT4 (1 << 15)
102 #define BMSR_100BTX_FD (1 << 14)
103 #define BMSR_100BTX (1 << 13)
104 #define BMSR_10BT_FD (1 << 12)
105 #define BMSR_10BT (1 << 11)
106 #define BMSR_UNIDIRECTIONAL_ABLE (1 << 7)
107 #define BMSR_NO_PREAMBLE (1 << 6)
108 #define BMSR_AN_COMPLETE (1 << 5)
109 #define BMSR_REMOTE_FAULT (1 << 4)
110 #define BMSR_AN_ABLE (1 << 3)
111 #define BMSR_LINK_STATUS (1 << 2)
112 #define BMSR_JABBER_DETECT (1 << 1)
113 #define BMSR_EXTENDED_CAP (1 << 0)
114 
115 //ANAR register
116 #define ANAR_NP (1 << 15)
117 #define ANAR_RF (1 << 13)
118 #define ANAR_ASM_DIR (1 << 11)
119 #define ANAR_PAUSE (1 << 10)
120 #define ANAR_100BT4 (1 << 9)
121 #define ANAR_100BTX_FD (1 << 8)
122 #define ANAR_100BTX (1 << 7)
123 #define ANAR_10BT_FD (1 << 6)
124 #define ANAR_10BT (1 << 5)
125 #define ANAR_SELECTOR4 (1 << 4)
126 #define ANAR_SELECTOR3 (1 << 3)
127 #define ANAR_SELECTOR2 (1 << 2)
128 #define ANAR_SELECTOR1 (1 << 1)
129 #define ANAR_SELECTOR0 (1 << 0)
130 
131 //ANLPAR register
132 #define ANLPAR_NP (1 << 15)
133 #define ANLPAR_ACK (1 << 14)
134 #define ANLPAR_RF (1 << 13)
135 #define ANLPAR_ASM_DIR (1 << 11)
136 #define ANLPAR_PAUSE (1 << 10)
137 #define ANLPAR_100BT4 (1 << 9)
138 #define ANLPAR_100BTX_FD (1 << 8)
139 #define ANLPAR_100BTX (1 << 7)
140 #define ANLPAR_10BT_FD (1 << 6)
141 #define ANLPAR_10BT (1 << 5)
142 #define ANLPAR_SELECTOR4 (1 << 4)
143 #define ANLPAR_SELECTOR3 (1 << 3)
144 #define ANLPAR_SELECTOR2 (1 << 2)
145 #define ANLPAR_SELECTOR1 (1 << 1)
146 #define ANLPAR_SELECTOR0 (1 << 0)
147 
148 //ANER register
149 #define ANER_PDF (1 << 4)
150 #define ANER_LP_NP_ABLE (1 << 3)
151 #define ANER_NP_ABLE (1 << 2)
152 #define ANER_PAGE_RX (1 << 1)
153 #define ANER_LP_AN_ABLE (1 << 0)
154 
155 //ANNPTR register
156 #define ANNPTR_NP (1 << 15)
157 #define ANNPTR_MP (1 << 13)
158 #define ANNPTR_ACK2 (1 << 12)
159 #define ANNPTR_TOG_TX (1 << 11)
160 #define ANNPTR_CODE10 (1 << 10)
161 #define ANNPTR_CODE9 (1 << 9)
162 #define ANNPTR_CODE8 (1 << 8)
163 #define ANNPTR_CODE7 (1 << 7)
164 #define ANNPTR_CODE6 (1 << 6)
165 #define ANNPTR_CODE5 (1 << 5)
166 #define ANNPTR_CODE4 (1 << 4)
167 #define ANNPTR_CODE3 (1 << 3)
168 #define ANNPTR_CODE2 (1 << 2)
169 #define ANNPTR_CODE1 (1 << 1)
170 #define ANNPTR_CODE0 (1 << 0)
171 
172 //PHYSTS register
173 #define PHYSTS_MDIX_MODE (1 << 14)
174 #define PHYSTS_RX_ERROR_LATCH (1 << 13)
175 #define PHYSTS_POLARITY_STATUS (1 << 12)
176 #define PHYSTS_FALSE_CARRIER_SENSE (1 << 11)
177 #define PHYSTS_SIGNAL_DETECT (1 << 10)
178 #define PHYSTS_DESCRAMBLER_LOCK (1 << 9)
179 #define PHYSTS_PAGE_RECEIVED (1 << 8)
180 #define PHYSTS_MII_INTERRUPT (1 << 7)
181 #define PHYSTS_REMOTE_FAULT (1 << 6)
182 #define PHYSTS_JABBER_DETECT (1 << 5)
183 #define PHYSTS_AN_COMPLETE (1 << 4)
184 #define PHYSTS_LOOPBACK_STATUS (1 << 3)
185 #define PHYSTS_DUPLEX_STATUS (1 << 2)
186 #define PHYSTS_SPEED_STATUS (1 << 1)
187 #define PHYSTS_LINK_STATUS (1 << 0)
188 
189 //MICR register
190 #define MICR_TINT (1 << 2)
191 #define MICR_INTEN (1 << 1)
192 #define MICR_INT_OE (1 << 0)
193 
194 //MISR register
195 #define MISR_ED_INT (1 << 14)
196 #define MISR_LINK_INT (1 << 13)
197 #define MISR_SPD_INT (1 << 12)
198 #define MISR_DUP_INT (1 << 11)
199 #define MISR_ANC_INT (1 << 10)
200 #define MISR_FHF_INT (1 << 9)
201 #define MISR_RHF_INT (1 << 8)
202 #define MISR_LQ_INT_EN (1 << 7)
203 #define MISR_ED_INT_EN (1 << 6)
204 #define MISR_LINK_INT_EN (1 << 5)
205 #define MISR_SPD_INT_EN (1 << 4)
206 #define MISR_DUP_INT_EN (1 << 3)
207 #define MISR_ANC_INT_EN (1 << 2)
208 #define MISR_FHF_INT_EN (1 << 1)
209 #define MISR_RHF_INT_EN (1 << 0)
210 
211 //PAGESEL register
212 #define PAGESEL_PAGE_SEL2 (1 << 2)
213 #define PAGESEL_PAGE_SEL1 (1 << 1)
214 #define PAGESEL_PAGE_SEL0 (1 << 0)
215 
216 //FCSCR register
217 #define FCSCR_FCSCNT7 (1 << 7)
218 #define FCSCR_FCSCNT6 (1 << 6)
219 #define FCSCR_FCSCNT5 (1 << 5)
220 #define FCSCR_FCSCNT4 (1 << 4)
221 #define FCSCR_FCSCNT3 (1 << 3)
222 #define FCSCR_FCSCNT2 (1 << 2)
223 #define FCSCR_FCSCNT1 (1 << 1)
224 #define FCSCR_FCSCNT0 (1 << 0)
225 
226 //RECR register
227 #define RECR_RXERCNT7 (1 << 7)
228 #define RECR_RXERCNT6 (1 << 6)
229 #define RECR_RXERCNT5 (1 << 5)
230 #define RECR_RXERCNT4 (1 << 4)
231 #define RECR_RXERCNT3 (1 << 3)
232 #define RECR_RXERCNT2 (1 << 2)
233 #define RECR_RXERCNT1 (1 << 1)
234 #define RECR_RXERCNT0 (1 << 0)
235 
236 //PCSR register
237 #define PCSR_AUTO_CROSSOVER (1 << 15)
238 #define PCSR_FREE_CLK (1 << 11)
239 #define PCSR_TQ_EN (1 << 10)
240 #define PCSR_SD_FORCE_PMA (1 << 9)
241 #define PCSR_SD_OPTION (1 << 8)
242 #define PCSR_DESC_TIME (1 << 7)
243 #define PCSR_FX_EN (1 << 6)
244 #define PCSR_FORCE_100_OK (1 << 5)
245 #define PCSR_FEFI_EN (1 << 3)
246 #define PCSR_NRZI_BYPASS (1 << 2)
247 #define PCSR_SCRAM_BYPASS (1 << 1)
248 #define PCSR_DESCRAM_BYPASS (1 << 0)
249 
250 //RBR register
251 #define RBR_RMII_MASTER (1 << 14)
252 #define RBR_DIS_TX_OPT (1 << 13)
253 #define RBR_PMD_LOOP (1 << 8)
254 #define RBR_SCMII_RX (1 << 7)
255 #define RBR_SCMII_TX (1 << 6)
256 #define RBR_RMII_MODE (1 << 5)
257 #define RBR_RMII_REV1_0 (1 << 4)
258 #define RBR_RX_OVF_STS (1 << 3)
259 #define RBR_RX_UNF_STS (1 << 2)
260 #define RBR_ELAST_BUF1 (1 << 1)
261 #define RBR_ELAST_BUF0 (1 << 0)
262 
263 //LEDCR register
264 #define LEDCR_DIS_SPDLED (1 << 11)
265 #define LEDCR_DIS_LNKLED (1 << 10)
266 #define LEDCR_DIS_ACTLED (1 << 9)
267 #define LEDCR_LEDACT_RX (1 << 8)
268 #define LEDCR_BLINK_FREQ1 (1 << 7)
269 #define LEDCR_BLINK_FREQ0 (1 << 6)
270 #define LEDCR_DRV_SPDLED (1 << 5)
271 #define LEDCR_DRV_LNKLED (1 << 4)
272 #define LEDCR_DRV_ACTLED (1 << 3)
273 #define LEDCR_SPDLED (1 << 2)
274 #define LEDCR_LNKLED (1 << 1)
275 #define LEDCR_ACTLED (1 << 0)
276 
277 #define LEDCR_BLINK_FREQ_6HZ (0 << 6)
278 #define LEDCR_BLINK_FREQ_12HZ (1 << 6)
279 #define LEDCR_BLINK_FREQ_24HZ (2 << 6)
280 #define LEDCR_BLINK_FREQ_48HZ (3 << 6)
281 
282 //PHYCR register
283 #define PHYCR_MDIX_EN (1 << 15)
284 #define PHYCR_FORCE_MDIX (1 << 14)
285 #define PHYCR_PAUSE_RX (1 << 13)
286 #define PHYCR_PAUSE_TX (1 << 12)
287 #define PHYCR_BIST_FE (1 << 11)
288 #define PHYCR_PSR_15 (1 << 10)
289 #define PHYCR_BIST_STATUS (1 << 9)
290 #define PHYCR_BIST_START (1 << 8)
291 #define PHYCR_BP_STRETCH (1 << 7)
292 #define PHYCR_LED_CNFG1 (1 << 6)
293 #define PHYCR_LED_CNFG0 (1 << 5)
294 #define PHYCR_PHYADDR4 (1 << 4)
295 #define PHYCR_PHYADDR3 (1 << 3)
296 #define PHYCR_PHYADDR2 (1 << 2)
297 #define PHYCR_PHYADDR1 (1 << 1)
298 #define PHYCR_PHYADDR0 (1 << 0)
299 
300 //10BTSCR register
301 #define _10BTSCR_10BT_SERIAL (1 << 15)
302 #define _10BTSCR_SQUELCH2 (1 << 11)
303 #define _10BTSCR_SQUELCH1 (1 << 10)
304 #define _10BTSCR_SQUELCH0 (1 << 9)
305 #define _10BTSCR_LOOPBACK_10_DIS (1 << 8)
306 #define _10BTSCR_LP_DIS (1 << 7)
307 #define _10BTSCR_FORCE_LINK_10 (1 << 6)
308 #define _10BTSCR_POLARITY (1 << 4)
309 #define _10BTSCR_AUTOPOL_DIS (1 << 3)
310 #define _10BTSCR_10BT_SCALE_MSB (1 << 2)
311 #define _10BTSCR_HEARTBEAT_DIS (1 << 1)
312 #define _10BTSCR_JABBER_DIS (1 << 0)
313 
314 //CDCTRL1 register
315 #define CDCTRL1_BIST_ERROR_COUNT7 (1 << 15)
316 #define CDCTRL1_BIST_ERROR_COUNT6 (1 << 14)
317 #define CDCTRL1_BIST_ERROR_COUNT5 (1 << 13)
318 #define CDCTRL1_BIST_ERROR_COUNT4 (1 << 12)
319 #define CDCTRL1_BIST_ERROR_COUNT3 (1 << 11)
320 #define CDCTRL1_BIST_ERROR_COUNT2 (1 << 10)
321 #define CDCTRL1_BIST_ERROR_COUNT1 (1 << 9)
322 #define CDCTRL1_BIST_ERROR_COUNT0 (1 << 8)
323 #define CDCTRL1_MII_CLOCK_EN (1 << 6)
324 #define CDCTRL1_BIST_CONT (1 << 5)
325 #define CDCTRL1_CDPATTEN_10 (1 << 4)
326 #define CDCTRL1_MDIO_PULL_EN (1 << 3)
327 #define CDCTRL1_PATT_GAP_10M (1 << 2)
328 #define CDCTRL1_CDPATTSEL1 (1 << 1)
329 #define CDCTRL1_CDPATTSEL0 (1 << 0)
330 
331 //PHYCR2 register
332 #define PHYCR2_SYNC_ENET_EN (1 << 13)
333 #define PHYCR2_CLK_OUT RXCLK (1 << 12)
334 #define PHYCR2_BC_WRITE (1 << 11)
335 #define PHYCR2_PHYTER_COMP (1 << 10)
336 #define PHYCR2_SOFT_RESET (1 << 9)
337 #define PHYCR2_CLK_OUT_DIS (1 << 1)
338 
339 //EDCR register
340 #define EDCR_ED_EN (1 << 15)
341 #define EDCR_ED_AUTO_UP (1 << 14)
342 #define EDCR_ED_AUTO_DOWN (1 << 13)
343 #define EDCR_ED_MAN (1 << 12)
344 #define EDCR_ED_BURST_DIS (1 << 11)
345 #define EDCR_ED_PWR_STATE (1 << 10)
346 #define EDCR_ED_ERR_MET (1 << 9)
347 #define EDCR_ED_DATA_MET (1 << 8)
348 #define EDCR_ED_ERR_COUNT3 (1 << 7)
349 #define EDCR_ED_ERR_COUNT2 (1 << 6)
350 #define EDCR_ED_ERR_COUNT1 (1 << 5)
351 #define EDCR_ED_ERR_COUNT0 (1 << 4)
352 #define EDCR_ED_DATA_COUNT3 (1 << 3)
353 #define EDCR_ED_DATA_COUNT2 (1 << 2)
354 #define EDCR_ED_DATA_COUNT1 (1 << 1)
355 #define EDCR_ED_DATA_COUNT0 (1 << 0)
356 
357 //PCFCR register
358 #define PCFCR_PCF_STS_ERR (1 << 15)
359 #define PCFCR_PCF_STS_OK (1 << 14)
360 #define PCFCR_PCF_DA_SEL (1 << 8)
361 #define PCFCR_PCF_INT_CTL1 (1 << 7)
362 #define PCFCR_PCF_INT_CTL0 (1 << 6)
363 #define PCFCR_PCF_BC_DIS (1 << 5)
364 #define PCFCR_PCF_BUF3 (1 << 4)
365 #define PCFCR_PCF_BUF2 (1 << 3)
366 #define PCFCR_PCF_BUF1 (1 << 2)
367 #define PCFCR_PCF_BUF0 (1 << 1)
368 #define PCFCR_PCF_EN (1 << 0)
369 
370 //SD_CNFG register
371 #define SD_CNFG_SD_TIME (1 << 8)
372 
373 //LEN100_DET register
374 #define LEN100_DET_CABLE_LEN7 (1 << 7)
375 #define LEN100_DET_CABLE_LEN6 (1 << 6)
376 #define LEN100_DET_CABLE_LEN5 (1 << 5)
377 #define LEN100_DET_CABLE_LEN4 (1 << 4)
378 #define LEN100_DET_CABLE_LEN3 (1 << 3)
379 #define LEN100_DET_CABLE_LEN2 (1 << 2)
380 #define LEN100_DET_CABLE_LEN1 (1 << 1)
381 #define LEN100_DET_CABLE_LEN0 (1 << 0)
382 
383 //FREQ100 register
384 #define FREQ100_SAMPLE_FREQ (1 << 15)
385 #define FREQ100_SEL_FC (1 << 8)
386 #define FREQ100_FREQ_OFFSET7 (1 << 7)
387 #define FREQ100_FREQ_OFFSET6 (1 << 6)
388 #define FREQ100_FREQ_OFFSET5 (1 << 5)
389 #define FREQ100_FREQ_OFFSET4 (1 << 4)
390 #define FREQ100_FREQ_OFFSET3 (1 << 3)
391 #define FREQ100_FREQ_OFFSET2 (1 << 2)
392 #define FREQ100_FREQ_OFFSET1 (1 << 1)
393 #define FREQ100_FREQ_OFFSET0 (1 << 0)
394 
395 //TDR_CTRL register
396 #define TDR_CTRL_TDR_ENABLE (1 << 15)
397 #define TDR_CTRL_TDR_100MB (1 << 14)
398 #define TDR_CTRL_TX_CHANNEL (1 << 13)
399 #define TDR_CTRL_RX_CHANNEL (1 << 12)
400 #define TDR_CTRL_SEND_TDR (1 << 11)
401 #define TDR_CTRL_TDR_WIDTH2 (1 << 10)
402 #define TDR_CTRL_TDR_WIDTH1 (1 << 9)
403 #define TDR_CTRL_TDR_WIDTH0 (1 << 8)
404 #define TDR_CTRL_TDR_MIN_MODE (1 << 7)
405 #define TDR_CTRL_RX_THRESHOLD5 (1 << 5)
406 #define TDR_CTRL_RX_THRESHOLD4 (1 << 4)
407 #define TDR_CTRL_RX_THRESHOLD3 (1 << 3)
408 #define TDR_CTRL_RX_THRESHOLD2 (1 << 2)
409 #define TDR_CTRL_RX_THRESHOLD1 (1 << 1)
410 #define TDR_CTRL_RX_THRESHOLD0 (1 << 0)
411 
412 //TDR_WIN register
413 #define TDR_WIN_TDR_START7 (1 << 15)
414 #define TDR_WIN_TDR_START6 (1 << 14)
415 #define TDR_WIN_TDR_START5 (1 << 13)
416 #define TDR_WIN_TDR_START4 (1 << 12)
417 #define TDR_WIN_TDR_START3 (1 << 11)
418 #define TDR_WIN_TDR_START2 (1 << 10)
419 #define TDR_WIN_TDR_START1 (1 << 9)
420 #define TDR_WIN_TDR_START0 (1 << 8)
421 #define TDR_WIN_TDR_STOP7 (1 << 7)
422 #define TDR_WIN_TDR_STOP6 (1 << 6)
423 #define TDR_WIN_TDR_STOP5 (1 << 5)
424 #define TDR_WIN_TDR_STOP4 (1 << 4)
425 #define TDR_WIN_TDR_STOP3 (1 << 3)
426 #define TDR_WIN_TDR_STOP2 (1 << 2)
427 #define TDR_WIN_TDR_STOP1 (1 << 1)
428 #define TDR_WIN_TDR_STOP0 (1 << 0)
429 
430 //TDR_PEAK register
431 #define TDR_PEAK_TDR_PEAK5 (1 << 13)
432 #define TDR_PEAK_TDR_PEAK4 (1 << 12)
433 #define TDR_PEAK_TDR_PEAK3 (1 << 11)
434 #define TDR_PEAK_TDR_PEAK2 (1 << 10)
435 #define TDR_PEAK_TDR_PEAK1 (1 << 9)
436 #define TDR_PEAK_TDR_PEAK0 (1 << 8)
437 #define TDR_PEAK_TDR_PEAK_TIME7 (1 << 7)
438 #define TDR_PEAK_TDR_PEAK_TIME6 (1 << 6)
439 #define TDR_PEAK_TDR_PEAK_TIME5 (1 << 5)
440 #define TDR_PEAK_TDR_PEAK_TIME4 (1 << 4)
441 #define TDR_PEAK_TDR_PEAK_TIME3 (1 << 3)
442 #define TDR_PEAK_TDR_PEAK_TIME2 (1 << 2)
443 #define TDR_PEAK_TDR_PEAK_TIME1 (1 << 1)
444 #define TDR_PEAK_TDR_PEAK_TIME0 (1 << 0)
445 
446 //TDR_THR register
447 #define TDR_THR_TDR_THR_MET (1 << 8)
448 #define TDR_THR_TDR_THR_TIME7 (1 << 7)
449 #define TDR_THR_TDR_THR_TIME6 (1 << 6)
450 #define TDR_THR_TDR_THR_TIME5 (1 << 5)
451 #define TDR_THR_TDR_THR_TIME4 (1 << 4)
452 #define TDR_THR_TDR_THR_TIME3 (1 << 3)
453 #define TDR_THR_TDR_THR_TIME2 (1 << 2)
454 #define TDR_THR_TDR_THR_TIME1 (1 << 1)
455 #define TDR_THR_TDR_THR_TIME0 (1 << 0)
456 
457 //VAR_CTRL register
458 #define VAR_CTRL_VAR_RDY (1 << 15)
459 #define VAR_CTRL_VAR_FREEZE (1 << 3)
460 #define VAR_CTRL_VAR_TIMER1 (1 << 2)
461 #define VAR_CTRL_VAR_TIMER0 (1 << 1)
462 #define VAR_CTRL_VAR_ENABLE (1 << 0)
463 
464 //LQMR register
465 #define LQMR_LQM_ENABLE (1 << 15)
466 #define LQMR_RESTART_ON_FC (1 << 14)
467 #define LQMR_RESTART_ON_FREQ (1 << 13)
468 #define LQMR_RESTART_ON_DBLW (1 << 12)
469 #define LQMR_RESTART_ON_DAGC (1 << 11)
470 #define LQMR_RESTART_ON_C1 (1 << 10)
471 #define LQMR_FC_HI_WARN (1 << 9)
472 #define LQMR_FC_LO_WARN (1 << 8)
473 #define LQMR_FREQ_HI_WARN (1 << 7)
474 #define LQMR_FREQ_LO_WARN (1 << 6)
475 #define LQMR_DBLW_HI_WARN (1 << 5)
476 #define LQMR_DBLW_LO_WARN (1 << 4)
477 #define LQMR_DAGC_HI_WARN (1 << 3)
478 #define LQMR_DAGC_LO_WARN (1 << 2)
479 #define LQMR_C1_HI_WARN (1 << 1)
480 #define LQMR_C1_LO_WARN (1 << 0)
481 
482 //LQDR register
483 #define LQDR_SAMPLE_PARAM (1 << 13)
484 #define LQDR_WRITE_LQ_THR (1 << 12)
485 #define LQDR_LQ_PARAM_SEL2 (1 << 11)
486 #define LQDR_LQ_PARAM_SEL1 (1 << 10)
487 #define LQDR_LQ_PARAM_SEL0 (1 << 9)
488 #define LQDR_LQ_THR_SEL (1 << 8)
489 #define LQDR_LQ_THR_DATA7 (1 << 7)
490 #define LQDR_LQ_THR_DATA6 (1 << 6)
491 #define LQDR_LQ_THR_DATA5 (1 << 5)
492 #define LQDR_LQ_THR_DATA4 (1 << 4)
493 #define LQDR_LQ_THR_DATA3 (1 << 3)
494 #define LQDR_LQ_THR_DATA2 (1 << 2)
495 #define LQDR_LQ_THR_DATA1 (1 << 1)
496 #define LQDR_LQ_THR_DATA0 (1 << 0)
497 
498 //LQMR2 register
499 #define LQMR2_RESTART_ON_VAR (1 << 10)
500 #define LQMR2_VAR_HI_WARN (1 << 1)
501 
502 //PSF_CFG register
503 #define PSF_CFG_MAC_SRC_ADD1 (1 << 12)
504 #define PSF_CFG_MAC_SRC_ADD0 (1 << 11)
505 #define PSF_CFG_MIN_PRE2 (1 << 10)
506 #define PSF_CFG_MIN_PRE1 (1 << 9)
507 #define PSF_CFG_MIN_PRE0 (1 << 8)
508 #define PSF_CFG_PSF_ENDIAN (1 << 7)
509 #define PSF_CFG_PSF_IPV4 (1 << 6)
510 #define PSF_CFG_PSF_PCF_RD (1 << 5)
511 #define PSF_CFG_PSF_ERR_EN (1 << 4)
512 
513 //C++ guard
514 #ifdef __cplusplus
515  extern "C" {
516 #endif
517 
518 //DP83620 Ethernet PHY driver
519 extern const PhyDriver dp83620PhyDriver;
520 
521 //DP83620 related functions
522 error_t dp83620Init(NetInterface *interface);
523 
524 void dp83620Tick(NetInterface *interface);
525 
526 void dp83620EnableIrq(NetInterface *interface);
527 void dp83620DisableIrq(NetInterface *interface);
528 
529 void dp83620EventHandler(NetInterface *interface);
530 
531 void dp83620WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
532 uint16_t dp83620ReadPhyReg(NetInterface *interface, uint8_t address);
533 
534 void dp83620DumpPhyReg(NetInterface *interface);
535 
536 //C++ guard
537 #ifdef __cplusplus
538  }
539 #endif
540 
541 #endif
void dp83620DisableIrq(NetInterface *interface)
Disable interrupts.
void dp83620EventHandler(NetInterface *interface)
DP83620 event handler.
void dp83620DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
void dp83620WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
const PhyDriver dp83620PhyDriver
DP83620 Ethernet PHY driver.
PHY driver.
Definition: nic.h:196
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
uint16_t dp83620ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
Network interface controller abstraction layer.
void dp83620EnableIrq(NetInterface *interface)
Enable interrupts.
void dp83620Tick(NetInterface *interface)
DP83620 timer handler.
error_t dp83620Init(NetInterface *interface)
DP83620 PHY transceiver initialization.