dp83620_driver.h
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1 /**
2  * @file dp83620_driver.h
3  * @brief DP83620 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _DP83620_DRIVER_H
32 #define _DP83620_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //PHY address
38 #ifndef DP83620_PHY_ADDR
39  #define DP83620_PHY_ADDR 1
40 #elif (DP83620_PHY_ADDR < 0 || DP83620_PHY_ADDR > 31)
41  #error DP83620_PHY_ADDR parameter is not valid
42 #endif
43 
44 //DP83620 PHY registers (page 0)
45 #define DP83620_BMCR 0x00
46 #define DP83620_BMSR 0x01
47 #define DP83620_PHYID1 0x02
48 #define DP83620_PHYID2 0x03
49 #define DP83620_ANAR 0x04
50 #define DP83620_ANLPAR 0x05
51 #define DP83620_ANER 0x06
52 #define DP83620_ANNPR 0x07
53 #define DP83620_PHYSTS 0x10
54 #define DP83620_MICR 0x11
55 #define DP83620_MISR 0x12
56 #define DP83620_PAGSR 0x13
57 #define DP83620_FCSCR 0x14
58 #define DP83620_RECR 0x15
59 #define DP83620_PCSR 0x16
60 #define DP83620_RBR 0x17
61 #define DP83620_LEDCR 0x18
62 #define DP83620_PHYCR 0x19
63 #define DP83620_10BTSCR 0x1A
64 #define DP83620_CDCTRL1 0x1B
65 #define DP83620_PHYCR2 0x1C
66 #define DP83620_EDCR 0x1D
67 #define DP83620_PCFCR 0x1E
68 
69 //DP83620 PHY registers (page 1)
70 #define DP83620_SD_CNFG 0x1E
71 
72 //DP83620 PHY registers (page 2)
73 #define DP83620_LEN100_DET 0x14
74 #define DP83620_FREQ100 0x15
75 #define DP83620_TDR_CTRL 0x16
76 #define DP83620_TDR_WIN 0x17
77 #define DP83620_TDR_PEAK 0x18
78 #define DP83620_TDR_THR 0x19
79 #define DP83620_VAR_CTRL 0x1A
80 #define DP83620_VAR_DAT 0x1B
81 #define DP83620_LQMR 0x1D
82 #define DP83620_LQDR 0x1E
83 #define DP83620_LQMR2 0x1F
84 
85 //DP83620 PHY registers (page 5)
86 #define DP83620_PSF_CFG 0x18
87 
88 //Basic Mode Control register
89 #define DP83620_BMCR_RESET 0x8000
90 #define DP83620_BMCR_LOOPBACK 0x4000
91 #define DP83620_BMCR_SPEED_SEL 0x2000
92 #define DP83620_BMCR_AN_EN 0x1000
93 #define DP83620_BMCR_POWER_DOWN 0x0800
94 #define DP83620_BMCR_ISOLATE 0x0400
95 #define DP83620_BMCR_RESTART_AN 0x0200
96 #define DP83620_BMCR_DUPLEX_MODE 0x0100
97 #define DP83620_BMCR_COL_TEST 0x0080
98 #define DP83620_BMCR_UNIDIRECTIONAL_EN 0x0020
99 
100 //Basic Mode Status register
101 #define DP83620_BMSR_100BT4 0x8000
102 #define DP83620_BMSR_100BTX_FD 0x4000
103 #define DP83620_BMSR_100BTX_HD 0x2000
104 #define DP83620_BMSR_10BT_FD 0x1000
105 #define DP83620_BMSR_10BT_HD 0x0800
106 #define DP83620_BMSR_UNIDIRECTIONAL_ABLE 0x0080
107 #define DP83620_BMSR_MF_PREAMBLE_SUPPR 0x0040
108 #define DP83620_BMSR_AN_COMPLETE 0x0020
109 #define DP83620_BMSR_REMOTE_FAULT 0x0010
110 #define DP83620_BMSR_AN_CAPABLE 0x0008
111 #define DP83620_BMSR_LINK_STATUS 0x0004
112 #define DP83620_BMSR_JABBER_DETECT 0x0002
113 #define DP83620_BMSR_EXTENDED_CAPABLE 0x0001
114 
115 //PHY Identifier 1 register
116 #define DP83620_PHYID1_OUI_MSB 0xFFFF
117 #define DP83620_PHYID1_OUI_MSB_DEFAULT 0x2000
118 
119 //PHY Identifier 2 register
120 #define DP83620_PHYID2_OUI_LSB 0xFC00
121 #define DP83620_PHYID2_OUI_LSB_DEFAULT 0x5C00
122 #define DP83620_PHYID2_VNDR_MDL 0x03F0
123 #define DP83620_PHYID2_VNDR_MDL_DEFAULT 0x00E0
124 #define DP83620_PHYID2_MDL_REV 0x000F
125 
126 //Auto-Negotiation Advertisement register
127 #define DP83620_ANAR_NEXT_PAGE 0x8000
128 #define DP83620_ANAR_REMOTE_FAULT 0x2000
129 #define DP83620_ANAR_ASM_DIR 0x0800
130 #define DP83620_ANAR_PAUSE 0x0400
131 #define DP83620_ANAR_100BT4 0x0200
132 #define DP83620_ANAR_100BTX_FD 0x0100
133 #define DP83620_ANAR_100BTX_HD 0x0080
134 #define DP83620_ANAR_10BT_FD 0x0040
135 #define DP83620_ANAR_10BT_HD 0x0020
136 #define DP83620_ANAR_SELECTOR 0x001F
137 #define DP83620_ANAR_SELECTOR_DEFAULT 0x0001
138 
139 //Auto-Negotiation Link Partner Ability register
140 #define DP83620_ANLPAR_NEXT_PAGE 0x8000
141 #define DP83620_ANLPAR_ACK 0x4000
142 #define DP83620_ANLPAR_REMOTE_FAULT 0x2000
143 #define DP83620_ANLPAR_ASM_DIR 0x0800
144 #define DP83620_ANLPAR_PAUSE 0x0400
145 #define DP83620_ANLPAR_100BT4 0x0200
146 #define DP83620_ANLPAR_100BTX_FD 0x0100
147 #define DP83620_ANLPAR_100BTX_HD 0x0080
148 #define DP83620_ANLPAR_10BT_FD 0x0040
149 #define DP83620_ANLPAR_10BT_HD 0x0020
150 #define DP83620_ANLPAR_SELECTOR 0x001F
151 #define DP83620_ANLPAR_SELECTOR_DEFAULT 0x0001
152 
153 //Auto-Negotiation Expansion register
154 #define DP83620_ANER_PAR_DETECT_FAULT 0x0010
155 #define DP83620_ANER_LP_NP_ABLE 0x0008
156 #define DP83620_ANER_NP_ABLE 0x0004
157 #define DP83620_ANER_PAGE_RX 0x0002
158 #define DP83620_ANER_LP_AN_ABLE 0x0001
159 
160 //Auto-Negotiation Next Page TX register
161 #define DP83620_ANNPR_NEXT_PAGE 0x8000
162 #define DP83620_ANNPR_MSG_PAGE 0x2000
163 #define DP83620_ANNPR_ACK2 0x1000
164 #define DP83620_ANNPR_TOGGLE 0x0800
165 #define DP83620_ANNPR_CODE 0x07FF
166 
167 //PHY Status register
168 #define DP83620_PHYSTS_MDIX_MODE 0x4000
169 #define DP83620_PHYSTS_RECEIVE_ERROR_LATCH 0x2000
170 #define DP83620_PHYSTS_POLARITY_STATUS 0x1000
171 #define DP83620_PHYSTS_FCS_LATCH 0x0800
172 #define DP83620_PHYSTS_SIGNAL_DETECT 0x0400
173 #define DP83620_PHYSTS_DESCRAMBLER_LOCK 0x0200
174 #define DP83620_PHYSTS_PAGE_RECEIVED 0x0100
175 #define DP83620_PHYSTS_MII_INTERRUPT 0x0080
176 #define DP83620_PHYSTS_REMOTE_FAULT 0x0040
177 #define DP83620_PHYSTS_JABBER_DETECT 0x0020
178 #define DP83620_PHYSTS_AN_COMPLETE 0x0010
179 #define DP83620_PHYSTS_LOOPBACK_STATUS 0x0008
180 #define DP83620_PHYSTS_DUPLEX_STATUS 0x0004
181 #define DP83620_PHYSTS_SPEED_STATUS 0x0002
182 #define DP83620_PHYSTS_LINK_STATUS 0x0001
183 
184 //MII Interrupt Control register
185 #define DP83620_MICR_TINT 0x0004
186 #define DP83620_MICR_INTEN 0x0002
187 #define DP83620_MICR_INT_OE 0x0001
188 
189 //MII Interrupt Status register
190 #define DP83620_MISR_LQ_INT 0x8000
191 #define DP83620_MISR_ED_INT 0x4000
192 #define DP83620_MISR_LINK_INT 0x2000
193 #define DP83620_MISR_SPD_INT 0x1000
194 #define DP83620_MISR_DUP_INT 0x0800
195 #define DP83620_MISR_ANC_INT 0x0400
196 #define DP83620_MISR_FHF_INT 0x0200
197 #define DP83620_MISR_RHF_INT 0x0100
198 #define DP83620_MISR_LQ_INT_EN 0x0080
199 #define DP83620_MISR_ED_INT_EN 0x0040
200 #define DP83620_MISR_LINK_INT_EN 0x0020
201 #define DP83620_MISR_SPD_INT_EN 0x0010
202 #define DP83620_MISR_DUP_INT_EN 0x0008
203 #define DP83620_MISR_ANC_INT_EN 0x0004
204 #define DP83620_MISR_FHF_INT_EN 0x0002
205 #define DP83620_MISR_RHF_INT_EN 0x0001
206 
207 //Page Select register
208 #define DP83620_PAGSR_PAGE_SEL 0x0007
209 
210 //False Carrier Sense Counter register
211 #define DP83620_FCSCR_FCSCNT 0x00FF
212 
213 //Receive Error Counter register
214 #define DP83620_RECR_RXERCNT 0x00FF
215 
216 //PCS Configuration and Status register
217 #define DP83620_PCSR_AUTO_CROSSOVER 0x8000
218 #define DP83620_PCSR_FREE_CLK 0x0800
219 #define DP83620_PCSR_TQ_EN 0x0400
220 #define DP83620_PCSR_SD_FORCE_PMA 0x0200
221 #define DP83620_PCSR_SD_OPTION 0x0100
222 #define DP83620_PCSR_DESC_TIME 0x0080
223 #define DP83620_PCSR_FX_EN 0x0040
224 #define DP83620_PCSR_FORCE_100_OK 0x0020
225 #define DP83620_PCSR_FEFI_EN 0x0008
226 #define DP83620_PCSR_NRZI_BYPASS 0x0004
227 #define DP83620_PCSR_SCRAM_BYPASS 0x0002
228 #define DP83620_PCSR_DESCRAM_BYPASS 0x0001
229 
230 //RMII and Bypass register
231 #define DP83620_RBR_RMII_MASTER 0x4000
232 #define DP83620_RBR_DIS_TX_OPT 0x2000
233 #define DP83620_RBR_PMD_LOOP 0x0100
234 #define DP83620_RBR_SCMII_RX 0x0080
235 #define DP83620_RBR_SCMII_TX 0x0040
236 #define DP83620_RBR_RMII_MODE 0x0020
237 #define DP83620_RBR_RMII_REV1_0 0x0010
238 #define DP83620_RBR_RX_OVF_STS 0x0008
239 #define DP83620_RBR_RX_UNF_STS 0x0004
240 #define DP83620_RBR_ELAST_BUF 0x0003
241 
242 //LED Direct Control register
243 #define DP83620_LEDCR_DIS_SPDLED 0x0800
244 #define DP83620_LEDCR_DIS_LNKLED 0x0400
245 #define DP83620_LEDCR_DIS_ACTLED 0x0200
246 #define DP83620_LEDCR_LEDACT_RX 0x0100
247 #define DP83620_LEDCR_BLINK_FREQ 0x00C0
248 #define DP83620_LEDCR_BLINK_FREQ_6HZ 0x0000
249 #define DP83620_LEDCR_BLINK_FREQ_12HZ 0x0040
250 #define DP83620_LEDCR_BLINK_FREQ_24HZ 0x0080
251 #define DP83620_LEDCR_BLINK_FREQ_48HZ 0x00C0
252 #define DP83620_LEDCR_DRV_SPDLED 0x0020
253 #define DP83620_LEDCR_DRV_LNKLED 0x0010
254 #define DP83620_LEDCR_DRV_ACTLED 0x0008
255 #define DP83620_LEDCR_SPDLED 0x0004
256 #define DP83620_LEDCR_LNKLED 0x0002
257 #define DP83620_LEDCR_ACTLED 0x0001
258 
259 //PHY Control register
260 #define DP83620_PHYCR_MDIX_EN 0x8000
261 #define DP83620_PHYCR_FORCE_MDIX 0x4000
262 #define DP83620_PHYCR_PAUSE_RX 0x2000
263 #define DP83620_PHYCR_PAUSE_TX 0x1000
264 #define DP83620_PHYCR_BIST_FE 0x0800
265 #define DP83620_PHYCR_PSR_15 0x0400
266 #define DP83620_PHYCR_BIST_STATUS 0x0200
267 #define DP83620_PHYCR_BIST_START 0x0100
268 #define DP83620_PHYCR_BP_STRETCH 0x0080
269 #define DP83620_PHYCR_LED_CNFG 0x0060
270 #define DP83620_PHYCR_PHYADDR 0x001F
271 
272 //10Base-T Status/Control register
273 #define DP83620_10BTSCR_SQUELCH 0x0E00
274 #define DP83620_10BTSCR_LOOPBACK_10_DIS 0x0100
275 #define DP83620_10BTSCR_LP_DIS 0x0080
276 #define DP83620_10BTSCR_FORCE_LINK_10 0x0040
277 #define DP83620_10BTSCR_FORCE_POL_COR 0x0020
278 #define DP83620_10BTSCR_POLARITY 0x0010
279 #define DP83620_10BTSCR_AUTOPOL_DIS 0x0008
280 #define DP83620_10BTSCR_10BT_SCALE_MSB 0x0004
281 #define DP83620_10BTSCR_HEARTBEAT_DIS 0x0002
282 #define DP83620_10BTSCR_JABBER_DIS 0x0001
283 
284 //CD Test Control and BIST Extensions register
285 #define DP83620_CDCTRL1_BIST_ERROR_COUNT 0xFF00
286 #define DP83620_CDCTRL1_MII_CLOCK_EN 0x0040
287 #define DP83620_CDCTRL1_BIST_CONT 0x0020
288 #define DP83620_CDCTRL1_CDPATTEN_10 0x0010
289 #define DP83620_CDCTRL1_MDIO_PULL_EN 0x0008
290 #define DP83620_CDCTRL1_PATT_GAP_10M 0x0004
291 #define DP83620_CDCTRL1_CDPATTSEL 0x0003
292 
293 //PHY Control 2 register
294 #define DP83620_PHYCR2_SYNC_ENET_EN 0x2000
295 #define DP83620_PHYCR2_CLK_OUT_RXCLK 0x1000
296 #define DP83620_PHYCR2_BC_WRITE 0x0800
297 #define DP83620_PHYCR2_PHYTER_COMP 0x0400
298 #define DP83620_PHYCR2_SOFT_RESET 0x0200
299 #define DP83620_PHYCR2_CLK_OUT_DIS 0x0002
300 
301 //Energy Detect Control register
302 #define DP83620_EDCR_ED_EN 0x8000
303 #define DP83620_EDCR_ED_AUTO_UP 0x4000
304 #define DP83620_EDCR_ED_AUTO_DOWN 0x2000
305 #define DP83620_EDCR_ED_MAN 0x1000
306 #define DP83620_EDCR_ED_BURST_DIS 0x0800
307 #define DP83620_EDCR_ED_PWR_STATE 0x0400
308 #define DP83620_EDCR_ED_ERR_MET 0x0200
309 #define DP83620_EDCR_ED_DATA_MET 0x0100
310 #define DP83620_EDCR_ED_ERR_COUNT 0x00F0
311 #define DP83620_EDCR_ED_DATA_COUNT 0x000F
312 
313 //PHY Control Frames Configuration register
314 #define DP83620_PCFCR_PCF_STS_ERR 0x8000
315 #define DP83620_PCFCR_PCF_STS_OK 0x4000
316 #define DP83620_PCFCR_PCF_DA_SEL 0x0100
317 #define DP83620_PCFCR_PCF_INT_CTL 0x00C0
318 #define DP83620_PCFCR_PCF_BC_DIS 0x0020
319 #define DP83620_PCFCR_PCF_BUF 0x001E
320 #define DP83620_PCFCR_PCF_EN 0x0001
321 
322 //Signal Detect Configuration register
323 #define DP83620_SD_CNFG_SD_TIME 0x0100
324 
325 //100 Mb Length Detect register
326 #define DP83620_LEN100_DET_CABLE_LEN 0x00FF
327 
328 //100 Mb Frequency Offset Indication register
329 #define DP83620_FREQ100_SAMPLE_FREQ 0x8000
330 #define DP83620_FREQ100_SEL_FC 0x0100
331 #define DP83620_FREQ100_FREQ_OFFSET 0x00FF
332 
333 //TDR Control register
334 #define DP83620_TDR_CTRL_TDR_ENABLE 0x8000
335 #define DP83620_TDR_CTRL_TDR_100MB 0x4000
336 #define DP83620_TDR_CTRL_TX_CHANNEL 0x2000
337 #define DP83620_TDR_CTRL_RX_CHANNEL 0x1000
338 #define DP83620_TDR_CTRL_SEND_TDR 0x0800
339 #define DP83620_TDR_CTRL_TDR_WIDTH 0x0700
340 #define DP83620_TDR_CTRL_TDR_MIN_MODE 0x0080
341 #define DP83620_TDR_CTRL_RX_THRESHOLD 0x003F
342 
343 //TDR Window register
344 #define DP83620_TDR_WIN_TDR_START 0xFF00
345 #define DP83620_TDR_WIN_TDR_STOP 0x00FF
346 
347 //TDR Peak register
348 #define DP83620_TDR_PEAK_TDR_PEAK 0x3F00
349 #define DP83620_TDR_PEAK_TDR_PEAK_TIME 0x00FF
350 
351 //TDR Threshold register
352 #define DP83620_TDR_THR_TDR_THR_MET 0x0100
353 #define DP83620_TDR_THR_TDR_THR_TIME 0x00FF
354 
355 //Variance Control register
356 #define DP83620_VAR_CTRL_VAR_RDY 0x8000
357 #define DP83620_VAR_CTRL_VAR_FREEZE 0x0008
358 #define DP83620_VAR_CTRL_VAR_TIMER 0x0006
359 #define DP83620_VAR_CTRL_VAR_ENABLE 0x0001
360 
361 //Link Quality Monitor register
362 #define DP83620_LQMR_LQM_ENABLE 0x8000
363 #define DP83620_LQMR_RESTART_ON_FC 0x4000
364 #define DP83620_LQMR_RESTART_ON_FREQ 0x2000
365 #define DP83620_LQMR_RESTART_ON_DBLW 0x1000
366 #define DP83620_LQMR_RESTART_ON_DAGC 0x0800
367 #define DP83620_LQMR_RESTART_ON_C1 0x0400
368 #define DP83620_LQMR_FC_HI_WARN 0x0200
369 #define DP83620_LQMR_FC_LO_WARN 0x0100
370 #define DP83620_LQMR_FREQ_HI_WARN 0x0080
371 #define DP83620_LQMR_FREQ_LO_WARN 0x0040
372 #define DP83620_LQMR_DBLW_HI_WARN 0x0020
373 #define DP83620_LQMR_DBLW_LO_WARN 0x0010
374 #define DP83620_LQMR_DAGC_HI_WARN 0x0008
375 #define DP83620_LQMR_DAGC_LO_WARN 0x0004
376 #define DP83620_LQMR_C1_HI_WARN 0x0002
377 #define DP83620_LQMR_C1_LO_WARN 0x0001
378 
379 //Link Quality Data register
380 #define DP83620_LQDR_SAMPLE_PARAM 0x2000
381 #define DP83620_LQDR_WRITE_LQ_THR 0x1000
382 #define DP83620_LQDR_LQ_PARAM_SEL 0x0E00
383 #define DP83620_LQDR_LQ_THR_SEL 0x0100
384 #define DP83620_LQDR_LQ_THR_DATA 0x00FF
385 
386 //Link Quality Monitor 2 register
387 #define DP83620_LQMR2_RESTART_ON_VAR 0x0400
388 #define DP83620_LQMR2_VAR_HI_WARN 0x0002
389 
390 //PHY Status Frame Configuration register
391 #define DP83620_PSF_CFG_MAC_SRC_ADD 0x1800
392 #define DP83620_PSF_CFG_MIN_PRE 0x0700
393 #define DP83620_PSF_CFG_PSF_ENDIAN 0x0080
394 #define DP83620_PSF_CFG_PSF_IPV4 0x0040
395 #define DP83620_PSF_CFG_PSF_PCF_RD 0x0020
396 #define DP83620_PSF_CFG_PSF_ERR_EN 0x0010
397 
398 //C++ guard
399 #ifdef __cplusplus
400 extern "C" {
401 #endif
402 
403 //DP83620 Ethernet PHY driver
404 extern const PhyDriver dp83620PhyDriver;
405 
406 //DP83620 related functions
407 error_t dp83620Init(NetInterface *interface);
408 
409 void dp83620Tick(NetInterface *interface);
410 
411 void dp83620EnableIrq(NetInterface *interface);
412 void dp83620DisableIrq(NetInterface *interface);
413 
414 void dp83620EventHandler(NetInterface *interface);
415 
416 void dp83620WritePhyReg(NetInterface *interface, uint8_t address,
417  uint16_t data);
418 
419 uint16_t dp83620ReadPhyReg(NetInterface *interface, uint8_t address);
420 
421 void dp83620DumpPhyReg(NetInterface *interface);
422 
423 //C++ guard
424 #ifdef __cplusplus
425 }
426 #endif
427 
428 #endif
void dp83620EnableIrq(NetInterface *interface)
Enable interrupts.
PHY driver.
Definition: nic.h:214
void dp83620WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
void dp83620DisableIrq(NetInterface *interface)
Disable interrupts.
void dp83620EventHandler(NetInterface *interface)
DP83620 event handler.
error_t dp83620Init(NetInterface *interface)
DP83620 PHY transceiver initialization.
void dp83620Tick(NetInterface *interface)
DP83620 timer handler.
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
void dp83620DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
uint16_t dp83620ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
Network interface controller abstraction layer.
Ipv6Addr address
uint8_t data[]
Definition: dtls_misc.h:176
const PhyDriver dp83620PhyDriver
DP83620 Ethernet PHY driver.