enc28j60_driver.h
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1 /**
2  * @file enc28j60_driver.h
3  * @brief ENC28J60 Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _ENC28J60_DRIVER_H
32 #define _ENC28J60_DRIVER_H
33 
34 //Full-duplex support
35 #ifndef ENC28J60_FULL_DUPLEX_SUPPORT
36  #define ENC28J60_FULL_DUPLEX_SUPPORT ENABLED
37 #elif (ENC28J60_FULL_DUPLEX_SUPPORT != ENABLED && ENC28J60_FULL_DUPLEX_SUPPORT != DISABLED)
38  #error ENC28J60_FULL_DUPLEX_SUPPORT parameter is not valid
39 #endif
40 
41 //Silicon revision identifiers
42 #define ENC28J60_REV_B1 0x02
43 #define ENC28J60_REV_B4 0x04
44 #define ENC28J60_REV_B5 0x05
45 #define ENC28J60_REV_B7 0x06
46 
47 //Receive and transmit buffers
48 #define ENC28J60_RX_BUFFER_START 0x0000
49 #define ENC28J60_RX_BUFFER_STOP 0x17FF
50 #define ENC28J60_TX_BUFFER_START 0x1800
51 #define ENC28J60_TX_BUFFER_STOP 0x1FFF
52 
53 //SPI command set
54 #define ENC28J60_CMD_RCR 0x00
55 #define ENC28J60_CMD_RBM 0x3A
56 #define ENC28J60_CMD_WCR 0x40
57 #define ENC28J60_CMD_WBM 0x7A
58 #define ENC28J60_CMD_BFS 0x80
59 #define ENC28J60_CMD_BFC 0xA0
60 #define ENC28J60_CMD_SRC 0xFF
61 
62 //ENC28J60 register types
63 #define ETH_REG_TYPE 0x0000
64 #define MAC_REG_TYPE 0x1000
65 #define MII_REG_TYPE 0x2000
66 #define PHY_REG_TYPE 0x3000
67 
68 //ENC28J60 banks
69 #define BANK_0 0x0000
70 #define BANK_1 0x0100
71 #define BANK_2 0x0200
72 #define BANK_3 0x0300
73 
74 //Related masks
75 #define REG_TYPE_MASK 0xF000
76 #define REG_BANK_MASK 0x0F00
77 #define REG_ADDR_MASK 0x001F
78 
79 //Bank 0 registers
80 #define ENC28J60_REG_ERDPTL (ETH_REG_TYPE | BANK_0 | 0x00)
81 #define ENC28J60_REG_ERDPTH (ETH_REG_TYPE | BANK_0 | 0x01)
82 #define ENC28J60_REG_EWRPTL (ETH_REG_TYPE | BANK_0 | 0x02)
83 #define ENC28J60_REG_EWRPTH (ETH_REG_TYPE | BANK_0 | 0x03)
84 #define ENC28J60_REG_ETXSTL (ETH_REG_TYPE | BANK_0 | 0x04)
85 #define ENC28J60_REG_ETXSTH (ETH_REG_TYPE | BANK_0 | 0x05)
86 #define ENC28J60_REG_ETXNDL (ETH_REG_TYPE | BANK_0 | 0x06)
87 #define ENC28J60_REG_ETXNDH (ETH_REG_TYPE | BANK_0 | 0x07)
88 #define ENC28J60_REG_ERXSTL (ETH_REG_TYPE | BANK_0 | 0x08)
89 #define ENC28J60_REG_ERXSTH (ETH_REG_TYPE | BANK_0 | 0x09)
90 #define ENC28J60_REG_ERXNDL (ETH_REG_TYPE | BANK_0 | 0x0A)
91 #define ENC28J60_REG_ERXNDH (ETH_REG_TYPE | BANK_0 | 0x0B)
92 #define ENC28J60_REG_ERXRDPTL (ETH_REG_TYPE | BANK_0 | 0x0C)
93 #define ENC28J60_REG_ERXRDPTH (ETH_REG_TYPE | BANK_0 | 0x0D)
94 #define ENC28J60_REG_ERXWRPTL (ETH_REG_TYPE | BANK_0 | 0x0E)
95 #define ENC28J60_REG_ERXWRPTH (ETH_REG_TYPE | BANK_0 | 0x0F)
96 #define ENC28J60_REG_EDMASTL (ETH_REG_TYPE | BANK_0 | 0x10)
97 #define ENC28J60_REG_EDMASTH (ETH_REG_TYPE | BANK_0 | 0x11)
98 #define ENC28J60_REG_EDMANDL (ETH_REG_TYPE | BANK_0 | 0x12)
99 #define ENC28J60_REG_EDMANDH (ETH_REG_TYPE | BANK_0 | 0x13)
100 #define ENC28J60_REG_EDMADSTL (ETH_REG_TYPE | BANK_0 | 0x14)
101 #define ENC28J60_REG_EDMADSTH (ETH_REG_TYPE | BANK_0 | 0x15)
102 #define ENC28J60_REG_EDMACSL (ETH_REG_TYPE | BANK_0 | 0x16)
103 #define ENC28J60_REG_EDMACSH (ETH_REG_TYPE | BANK_0 | 0x17)
104 #define ENC28J60_REG_EIE (ETH_REG_TYPE | BANK_0 | 0x1B)
105 #define ENC28J60_REG_EIR (ETH_REG_TYPE | BANK_0 | 0x1C)
106 #define ENC28J60_REG_ESTAT (ETH_REG_TYPE | BANK_0 | 0x1D)
107 #define ENC28J60_REG_ECON2 (ETH_REG_TYPE | BANK_0 | 0x1E)
108 #define ENC28J60_REG_ECON1 (ETH_REG_TYPE | BANK_0 | 0x1F)
109 
110 //Bank 1 registers
111 #define ENC28J60_REG_EHT0 (ETH_REG_TYPE | BANK_1 | 0x00)
112 #define ENC28J60_REG_EHT1 (ETH_REG_TYPE | BANK_1 | 0x01)
113 #define ENC28J60_REG_EHT2 (ETH_REG_TYPE | BANK_1 | 0x02)
114 #define ENC28J60_REG_EHT3 (ETH_REG_TYPE | BANK_1 | 0x03)
115 #define ENC28J60_REG_EHT4 (ETH_REG_TYPE | BANK_1 | 0x04)
116 #define ENC28J60_REG_EHT5 (ETH_REG_TYPE | BANK_1 | 0x05)
117 #define ENC28J60_REG_EHT6 (ETH_REG_TYPE | BANK_1 | 0x06)
118 #define ENC28J60_REG_EHT7 (ETH_REG_TYPE | BANK_1 | 0x07)
119 #define ENC28J60_REG_EPMM0 (ETH_REG_TYPE | BANK_1 | 0x08)
120 #define ENC28J60_REG_EPMM1 (ETH_REG_TYPE | BANK_1 | 0x09)
121 #define ENC28J60_REG_EPMM2 (ETH_REG_TYPE | BANK_1 | 0x0A)
122 #define ENC28J60_REG_EPMM3 (ETH_REG_TYPE | BANK_1 | 0x0B)
123 #define ENC28J60_REG_EPMM4 (ETH_REG_TYPE | BANK_1 | 0x0C)
124 #define ENC28J60_REG_EPMM5 (ETH_REG_TYPE | BANK_1 | 0x0D)
125 #define ENC28J60_REG_EPMM6 (ETH_REG_TYPE | BANK_1 | 0x0E)
126 #define ENC28J60_REG_EPMM7 (ETH_REG_TYPE | BANK_1 | 0x0F)
127 #define ENC28J60_REG_EPMCSL (ETH_REG_TYPE | BANK_1 | 0x10)
128 #define ENC28J60_REG_EPMCSH (ETH_REG_TYPE | BANK_1 | 0x11)
129 #define ENC28J60_REG_EPMOL (ETH_REG_TYPE | BANK_1 | 0x14)
130 #define ENC28J60_REG_EPMOH (ETH_REG_TYPE | BANK_1 | 0x15)
131 #define ENC28J60_REG_EWOLIE (ETH_REG_TYPE | BANK_1 | 0x16)
132 #define ENC28J60_REG_EWOLIR (ETH_REG_TYPE | BANK_1 | 0x17)
133 #define ENC28J60_REG_ERXFCON (ETH_REG_TYPE | BANK_1 | 0x18)
134 #define ENC28J60_REG_EPKTCNT (ETH_REG_TYPE | BANK_1 | 0x19)
135 
136 //Bank 2 registers
137 #define ENC28J60_REG_MACON1 (MAC_REG_TYPE | BANK_2 | 0x00)
138 #define ENC28J60_REG_MACON2 (MAC_REG_TYPE | BANK_2 | 0x01)
139 #define ENC28J60_REG_MACON3 (MAC_REG_TYPE | BANK_2 | 0x02)
140 #define ENC28J60_REG_MACON4 (MAC_REG_TYPE | BANK_2 | 0x03)
141 #define ENC28J60_REG_MABBIPG (MAC_REG_TYPE | BANK_2 | 0x04)
142 #define ENC28J60_REG_MAIPGL (MAC_REG_TYPE | BANK_2 | 0x06)
143 #define ENC28J60_REG_MAIPGH (MAC_REG_TYPE | BANK_2 | 0x07)
144 #define ENC28J60_REG_MACLCON1 (MAC_REG_TYPE | BANK_2 | 0x08)
145 #define ENC28J60_REG_MACLCON2 (MAC_REG_TYPE | BANK_2 | 0x09)
146 #define ENC28J60_REG_MAMXFLL (MAC_REG_TYPE | BANK_2 | 0x0A)
147 #define ENC28J60_REG_MAMXFLH (MAC_REG_TYPE | BANK_2 | 0x0B)
148 #define ENC28J60_REG_MAPHSUP (MAC_REG_TYPE | BANK_2 | 0x0D)
149 #define ENC28J60_REG_MICON (MII_REG_TYPE | BANK_2 | 0x11)
150 #define ENC28J60_REG_MICMD (MII_REG_TYPE | BANK_2 | 0x12)
151 #define ENC28J60_REG_MIREGADR (MII_REG_TYPE | BANK_2 | 0x14)
152 #define ENC28J60_REG_MIWRL (MII_REG_TYPE | BANK_2 | 0x16)
153 #define ENC28J60_REG_MIWRH (MII_REG_TYPE | BANK_2 | 0x17)
154 #define ENC28J60_REG_MIRDL (MII_REG_TYPE | BANK_2 | 0x18)
155 #define ENC28J60_REG_MIRDH (MII_REG_TYPE | BANK_2 | 0x19)
156 
157 //Bank 3 registers
158 #define ENC28J60_REG_MAADR5 (MAC_REG_TYPE | BANK_3 | 0x00)
159 #define ENC28J60_REG_MAADR6 (MAC_REG_TYPE | BANK_3 | 0x01)
160 #define ENC28J60_REG_MAADR3 (MAC_REG_TYPE | BANK_3 | 0x02)
161 #define ENC28J60_REG_MAADR4 (MAC_REG_TYPE | BANK_3 | 0x03)
162 #define ENC28J60_REG_MAADR1 (MAC_REG_TYPE | BANK_3 | 0x04)
163 #define ENC28J60_REG_MAADR2 (MAC_REG_TYPE | BANK_3 | 0x05)
164 #define ENC28J60_REG_EBSTSD (ETH_REG_TYPE | BANK_3 | 0x06)
165 #define ENC28J60_REG_EBSTCON (ETH_REG_TYPE | BANK_3 | 0x07)
166 #define ENC28J60_REG_EBSTCSL (ETH_REG_TYPE | BANK_3 | 0x08)
167 #define ENC28J60_REG_EBSTCSH (ETH_REG_TYPE | BANK_3 | 0x09)
168 #define ENC28J60_REG_MISTAT (MII_REG_TYPE | BANK_3 | 0x0A)
169 #define ENC28J60_REG_EREVID (ETH_REG_TYPE | BANK_3 | 0x12)
170 #define ENC28J60_REG_ECOCON (ETH_REG_TYPE | BANK_3 | 0x15)
171 #define ENC28J60_REG_EFLOCON (ETH_REG_TYPE | BANK_3 | 0x17)
172 #define ENC28J60_REG_EPAUSL (ETH_REG_TYPE | BANK_3 | 0x18)
173 #define ENC28J60_REG_EPAUSH (ETH_REG_TYPE | BANK_3 | 0x19)
174 
175 //PHY registers
176 #define ENC28J60_PHY_REG_PHCON1 (PHY_REG_TYPE | 0x00)
177 #define ENC28J60_PHY_REG_PHSTAT1 (PHY_REG_TYPE | 0x01)
178 #define ENC28J60_PHY_REG_PHID1 (PHY_REG_TYPE | 0x02)
179 #define ENC28J60_PHY_REG_PHID2 (PHY_REG_TYPE | 0x03)
180 #define ENC28J60_PHY_REG_PHCON2 (PHY_REG_TYPE | 0x10)
181 #define ENC28J60_PHY_REG_PHSTAT2 (PHY_REG_TYPE | 0x11)
182 #define ENC28J60_PHY_REG_PHIE (PHY_REG_TYPE | 0x12)
183 #define ENC28J60_PHY_REG_PHIR (PHY_REG_TYPE | 0x13)
184 #define ENC28J60_PHY_REG_PHLCON (PHY_REG_TYPE | 0x14)
185 
186 //EIE register
187 #define EIE_INTIE (1 << 7)
188 #define EIE_PKTIE (1 << 6)
189 #define EIE_DMAIE (1 << 5)
190 #define EIE_LINKIE (1 << 4)
191 #define EIE_TXIE (1 << 3)
192 #define EIE_WOLIE (1 << 2)
193 #define EIE_TXERIE (1 << 1)
194 #define EIE_RXERIE (1 << 0)
195 
196 //EIR register
197 #define EIR_PKTIF (1 << 6)
198 #define EIR_DMAIF (1 << 5)
199 #define EIR_LINKIF (1 << 4)
200 #define EIR_TXIF (1 << 3)
201 #define EIR_WOLIF (1 << 2)
202 #define EIR_TXERIF (1 << 1)
203 #define EIR_RXERIF (1 << 0)
204 
205 //ESTAT register
206 #define ESTAT_INT (1 << 7)
207 #define ESTAT_LATECOL (1 << 4)
208 #define ESTAT_RXBUSY (1 << 2)
209 #define ESTAT_TXABRT (1 << 1)
210 #define ESTAT_CLKRDY (1 << 0)
211 
212 //ECON2 register
213 #define ECON2_AUTOINC (1 << 7)
214 #define ECON2_PKTDEC (1 << 6)
215 #define ECON2_PWRSV (1 << 5)
216 #define ECON2_VRPS (1 << 3)
217 
218 //ECON1 register
219 #define ECON1_TXRST (1 << 7)
220 #define ECON1_RXRST (1 << 6)
221 #define ECON1_DMAST (1 << 5)
222 #define ECON1_CSUMEN (1 << 4)
223 #define ECON1_TXRTS (1 << 3)
224 #define ECON1_RXEN (1 << 2)
225 #define ECON1_BSEL1 (1 << 1)
226 #define ECON1_BSEL0 (1 << 0)
227 
228 //ERXFCON register
229 #define ERXFCON_UCEN (1 << 7)
230 #define ERXFCON_ANDOR (1 << 6)
231 #define ERXFCON_CRCEN (1 << 5)
232 #define ERXFCON_PMEN (1 << 4)
233 #define ERXFCON_MPEN (1 << 3)
234 #define ERXFCON_HTEN (1 << 2)
235 #define ERXFCON_MCEN (1 << 1)
236 #define ERXFCON_BCEN (1 << 0)
237 
238 //MACON1 register
239 #define MACON1_LOOPBK (1 << 4)
240 #define MACON1_TXPAUS (1 << 3)
241 #define MACON1_RXPAUS (1 << 2)
242 #define MACON1_PASSALL (1 << 1)
243 #define MACON1_MARXEN (1 << 0)
244 
245 //MACON2 register
246 #define MACON2_MARST (1 << 7)
247 #define MACON2_RNDRST (1 << 6)
248 #define MACON2_MARXRST (1 << 3)
249 #define MACON2_RFUNRST (1 << 2)
250 #define MACON2_MATXRST (1 << 1)
251 #define MACON2_TFUNRST (1 << 0)
252 
253 //MACON3 register
254 #define MACON3_PADCFG2 (1 << 7)
255 #define MACON3_PADCFG1 (1 << 6)
256 #define MACON3_PADCFG0 (1 << 5)
257 #define MACON3_TXCRCEN (1 << 4)
258 #define MACON3_PHDRLEN (1 << 3)
259 #define MACON3_HFRMLEN (1 << 2)
260 #define MACON3_FRMLNEN (1 << 1)
261 #define MACON3_FULDPX (1 << 0)
262 
263 #define MACON3_PADCFG(x) ((x) << 5)
264 
265 //MACON4 register
266 #define MACON4_DEFER (1 << 6)
267 #define MACON4_BPEN (1 << 5)
268 #define MACON4_NOBKOFF (1 << 4)
269 #define MACON4_LONGPRE (1 << 1)
270 #define MACON4_PUREPRE (1 << 0)
271 
272 //MAPHSUP register
273 #define MAPHSUP_RSTINTFC (1 << 7)
274 #define MAPHSUP_RSTRMII (1 << 3)
275 
276 //MICON register
277 #define MICON_RSTMII (1 << 7)
278 
279 //MICMD register
280 #define MICMD_MIISCAN (1 << 1)
281 #define MICMD_MIIRD (1 << 0)
282 
283 //EBSTCON register
284 #define EBSTCON_PSV2 (1 << 7)
285 #define EBSTCON_PSV1 (1 << 6)
286 #define EBSTCON_PSV0 (1 << 5)
287 #define EBSTCON_PSEL (1 << 4)
288 #define EBSTCON_TMSEL1 (1 << 3)
289 #define EBSTCON_TMSEL0 (1 << 2)
290 #define EBSTCON_TME (1 << 1)
291 #define EBSTCON_BISTST (1 << 0)
292 
293 //MISTAT register
294 #define MISTAT_NVALID (1 << 2)
295 #define MISTAT_SCAN (1 << 1)
296 #define MISTAT_BUSY (1 << 0)
297 
298 //ECOCON register
299 #define ECOCON_COCON2 (1 << 2)
300 #define ECOCON_COCON1 (1 << 1)
301 #define ECOCON_COCON0 (1 << 0)
302 
303 //EFLOCON register
304 #define EFLOCON_FULDPXS (1 << 2)
305 #define EFLOCON_FCEN1 (1 << 1)
306 #define EFLOCON_FCEN0 (1 << 0)
307 
308 //PHCON1 register
309 #define PHCON1_PRST (1 << 15)
310 #define PHCON1_PLOOPBK (1 << 14)
311 #define PHCON1_PPWRSV (1 << 11)
312 #define PHCON1_PDPXMD (1 << 8)
313 
314 //PHSTAT1 register
315 #define PHSTAT1_PFDPX (1 << 12)
316 #define PHSTAT1_PHDPX (1 << 11)
317 #define PHSTAT1_LLSTAT (1 << 2)
318 #define PHSTAT1_JBSTAT (1 << 1)
319 
320 //PHCON2 register
321 #define PHCON2_FRCLINK (1 << 14)
322 #define PHCON2_TXDIS (1 << 13)
323 #define PHCON2_JABBER (1 << 10)
324 #define PHCON2_HDLDIS (1 << 8)
325 
326 //PHSTAT2 register
327 #define PHSTAT2_TXSTAT (1 << 13)
328 #define PHSTAT2_RXSTAT (1 << 12)
329 #define PHSTAT2_COLSTAT (1 << 11)
330 #define PHSTAT2_LSTAT (1 << 10)
331 #define PHSTAT2_DPXSTAT (1 << 9)
332 #define PHSTAT2_PLRITY (1 << 4)
333 
334 //PHIE register
335 #define PHIE_PLNKIE (1 << 4)
336 #define PHIE_PGEIE (1 << 1)
337 
338 //PHIR register
339 #define PHIR_PLNKIF (1 << 4)
340 #define PHIR_PGIF (1 << 2)
341 
342 //PHLCON register
343 #define PHLCON_LACFG3 (1 << 11)
344 #define PHLCON_LACFG2 (1 << 10)
345 #define PHLCON_LACFG1 (1 << 9)
346 #define PHLCON_LACFG0 (1 << 8)
347 #define PHLCON_LBCFG3 (1 << 7)
348 #define PHLCON_LBCFG2 (1 << 6)
349 #define PHLCON_LBCFG1 (1 << 5)
350 #define PHLCON_LBCFG0 (1 << 4)
351 #define PHLCON_LFRQ1 (1 << 3)
352 #define PHLCON_LFRQ0 (1 << 2)
353 #define PHLCON_STRCH (1 << 1)
354 
355 #define PHLCON_LACFG(x) ((x) << 8)
356 #define PHLCON_LBCFG(x) ((x) << 4)
357 #define PHLCON_LFRQ(x) ((x) << 2)
358 
359 //Per-packet control byte
360 #define TX_CTRL_PHUGEEN (1 << 3)
361 #define TX_CTRL_PPADEN (1 << 2)
362 #define TX_CTRL_PCRCEN (1 << 1)
363 #define TX_CTRL_POVERRIDE (1 << 0)
364 
365 //Receive status vector
366 #define RSV_VLAN_TYPE 0x4000
367 #define RSV_UNKNOWN_OPCODE 0x2000
368 #define RSV_PAUSE_CONTROL_FRAME 0x1000
369 #define RSV_CONTROL_FRAME 0x0800
370 #define RSV_DRIBBLE_NIBBLE 0x0400
371 #define RSV_BROADCAST_PACKET 0x0200
372 #define RSV_MULTICAST_PACKET 0x0100
373 #define RSV_RECEIVED_OK 0x0080
374 #define RSV_LENGTH_OUT_OF_RANGE 0x0040
375 #define RSV_LENGTH_CHECK_ERROR 0x0020
376 #define RSV_CRC_ERROR 0x0010
377 #define RSV_CARRIER_EVENT 0x0004
378 #define RSV_DROP_EVENT 0x0001
379 
380 //C++ guard
381 #ifdef __cplusplus
382 extern "C" {
383 #endif
384 
385 
386 /**
387  * @brief ENC28J60 driver context
388  **/
389 
390 typedef struct
391 {
392  uint16_t currentBank; ///<Current bank
393  uint16_t nextPacket; ///<Next packet in the receive buffer
394  uint8_t *rxBuffer; ///<Receive buffer
396 
397 
398 //ENC28J60 driver
399 extern const NicDriver enc28j60Driver;
400 
401 //ENC28J60 related functions
402 error_t enc28j60Init(NetInterface *interface);
403 
404 void enc28j60Tick(NetInterface *interface);
405 
406 void enc28j60EnableIrq(NetInterface *interface);
407 void enc28j60DisableIrq(NetInterface *interface);
409 void enc28j60EventHandler(NetInterface *interface);
410 
412  const NetBuffer *buffer, size_t offset);
413 
415 
417 
418 void enc28j60SoftReset(NetInterface *interface);
419 void enc28j60SelectBank(NetInterface *interface, uint16_t address);
420 
421 void enc28j60WriteReg(NetInterface *interface, uint16_t address, uint8_t data);
422 uint8_t enc28j60ReadReg(NetInterface *interface, uint16_t address);
423 
424 void enc28j60WritePhyReg(NetInterface *interface, uint16_t address,
425  uint16_t data);
426 
427 uint16_t enc28j60ReadPhyReg(NetInterface *interface, uint16_t address);
428 
429 void enc28j60WriteBuffer(NetInterface *interface,
430  const NetBuffer *buffer, size_t offset);
431 
432 void enc28j60ReadBuffer(NetInterface *interface,
433  uint8_t *data, size_t length);
434 
435 void enc28j60SetBit(NetInterface *interface, uint16_t address, uint16_t mask);
436 void enc28j60ClearBit(NetInterface *interface, uint16_t address, uint16_t mask);
437 
438 uint32_t enc28j60CalcCrc(const void *data, size_t length);
439 
440 void enc28j60DumpReg(NetInterface *interface);
441 void enc28j60DumpPhyReg(NetInterface *interface);
442 
443 //C++ guard
444 #ifdef __cplusplus
445 }
446 #endif
447 
448 #endif
uint8_t length
Definition: dtls_misc.h:149
int bool_t
Definition: compiler_port.h:49
uint8_t * rxBuffer
Receive buffer.
void enc28j60SoftReset(NetInterface *interface)
ENC28J60 controller reset.
error_t enc28j60Init(NetInterface *interface)
ENC28J60 controller initialization.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
uint16_t enc28j60ReadPhyReg(NetInterface *interface, uint16_t address)
Read PHY register.
void enc28j60ReadBuffer(NetInterface *interface, uint8_t *data, size_t length)
Read SRAM buffer.
void enc28j60WriteReg(NetInterface *interface, uint16_t address, uint8_t data)
Write ENC28J60 register.
void enc28j60DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
void enc28j60EnableIrq(NetInterface *interface)
Enable interrupts.
error_t enc28j60SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint16_t nextPacket
Next packet in the receive buffer.
error_t
Error codes.
Definition: error.h:42
uint8_t enc28j60ReadReg(NetInterface *interface, uint16_t address)
Read ENC28J60 register.
void enc28j60SetBit(NetInterface *interface, uint16_t address, uint16_t mask)
Set bit field.
#define NetInterface
Definition: net.h:36
uint16_t currentBank
Current bank.
uint8_t mask
Definition: web_socket.h:317
bool_t enc28j60IrqHandler(NetInterface *interface)
ENC28J60 interrupt service routine.
void enc28j60Tick(NetInterface *interface)
ENC28J60 timer handler.
ENC28J60 driver context.
uint32_t enc28j60CalcCrc(const void *data, size_t length)
CRC calculation using the polynomial 0x4C11DB7.
error_t enc28j60UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void enc28j60EventHandler(NetInterface *interface)
ENC28J60 event handler.
void enc28j60SelectBank(NetInterface *interface, uint16_t address)
Bank selection.
void enc28j60WriteBuffer(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Write SRAM buffer.
Ipv6Addr address
void enc28j60DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
void enc28j60WritePhyReg(NetInterface *interface, uint16_t address, uint16_t data)
Write PHY register.
const NicDriver enc28j60Driver
ENC28J60 driver.
uint8_t data[]
Definition: dtls_misc.h:176
error_t enc28j60ReceivePacket(NetInterface *interface)
Receive a packet.
NIC driver.
Definition: nic.h:179
void enc28j60ClearBit(NetInterface *interface, uint16_t address, uint16_t mask)
Clear bit field.
void enc28j60DisableIrq(NetInterface *interface)
Disable interrupts.