enc28j60_driver.h
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1 /**
2  * @file enc28j60_driver.h
3  * @brief ENC28J60 Ethernet controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _ENC28J60_DRIVER_H
30 #define _ENC28J60_DRIVER_H
31 
32 //Full-duplex support
33 #ifndef ENC28J60_FULL_DUPLEX_SUPPORT
34  #define ENC28J60_FULL_DUPLEX_SUPPORT ENABLED
35 #elif (ENC28J60_FULL_DUPLEX_SUPPORT != ENABLED && ENC28J60_FULL_DUPLEX_SUPPORT != DISABLED)
36  #error ENC28J60_FULL_DUPLEX_SUPPORT parameter is not valid
37 #endif
38 
39 //Silicon revision identifiers
40 #define ENC28J60_REV_B1 0x02
41 #define ENC28J60_REV_B4 0x04
42 #define ENC28J60_REV_B5 0x05
43 #define ENC28J60_REV_B7 0x06
44 
45 //Receive and transmit buffers
46 #define ENC28J60_RX_BUFFER_START 0x0000
47 #define ENC28J60_RX_BUFFER_STOP 0x17FF
48 #define ENC28J60_TX_BUFFER_START 0x1800
49 #define ENC28J60_TX_BUFFER_STOP 0x1FFF
50 
51 //SPI command set
52 #define ENC28J60_CMD_RCR 0x00
53 #define ENC28J60_CMD_RBM 0x3A
54 #define ENC28J60_CMD_WCR 0x40
55 #define ENC28J60_CMD_WBM 0x7A
56 #define ENC28J60_CMD_BFS 0x80
57 #define ENC28J60_CMD_BFC 0xA0
58 #define ENC28J60_CMD_SRC 0xFF
59 
60 //ENC28J60 register types
61 #define ETH_REG_TYPE 0x0000
62 #define MAC_REG_TYPE 0x1000
63 #define MII_REG_TYPE 0x2000
64 #define PHY_REG_TYPE 0x3000
65 
66 //ENC28J60 banks
67 #define BANK_0 0x0000
68 #define BANK_1 0x0100
69 #define BANK_2 0x0200
70 #define BANK_3 0x0300
71 
72 //Related masks
73 #define REG_TYPE_MASK 0xF000
74 #define REG_BANK_MASK 0x0F00
75 #define REG_ADDR_MASK 0x001F
76 
77 //Bank 0 registers
78 #define ENC28J60_REG_ERDPTL (ETH_REG_TYPE | BANK_0 | 0x00)
79 #define ENC28J60_REG_ERDPTH (ETH_REG_TYPE | BANK_0 | 0x01)
80 #define ENC28J60_REG_EWRPTL (ETH_REG_TYPE | BANK_0 | 0x02)
81 #define ENC28J60_REG_EWRPTH (ETH_REG_TYPE | BANK_0 | 0x03)
82 #define ENC28J60_REG_ETXSTL (ETH_REG_TYPE | BANK_0 | 0x04)
83 #define ENC28J60_REG_ETXSTH (ETH_REG_TYPE | BANK_0 | 0x05)
84 #define ENC28J60_REG_ETXNDL (ETH_REG_TYPE | BANK_0 | 0x06)
85 #define ENC28J60_REG_ETXNDH (ETH_REG_TYPE | BANK_0 | 0x07)
86 #define ENC28J60_REG_ERXSTL (ETH_REG_TYPE | BANK_0 | 0x08)
87 #define ENC28J60_REG_ERXSTH (ETH_REG_TYPE | BANK_0 | 0x09)
88 #define ENC28J60_REG_ERXNDL (ETH_REG_TYPE | BANK_0 | 0x0A)
89 #define ENC28J60_REG_ERXNDH (ETH_REG_TYPE | BANK_0 | 0x0B)
90 #define ENC28J60_REG_ERXRDPTL (ETH_REG_TYPE | BANK_0 | 0x0C)
91 #define ENC28J60_REG_ERXRDPTH (ETH_REG_TYPE | BANK_0 | 0x0D)
92 #define ENC28J60_REG_ERXWRPTL (ETH_REG_TYPE | BANK_0 | 0x0E)
93 #define ENC28J60_REG_ERXWRPTH (ETH_REG_TYPE | BANK_0 | 0x0F)
94 #define ENC28J60_REG_EDMASTL (ETH_REG_TYPE | BANK_0 | 0x10)
95 #define ENC28J60_REG_EDMASTH (ETH_REG_TYPE | BANK_0 | 0x11)
96 #define ENC28J60_REG_EDMANDL (ETH_REG_TYPE | BANK_0 | 0x12)
97 #define ENC28J60_REG_EDMANDH (ETH_REG_TYPE | BANK_0 | 0x13)
98 #define ENC28J60_REG_EDMADSTL (ETH_REG_TYPE | BANK_0 | 0x14)
99 #define ENC28J60_REG_EDMADSTH (ETH_REG_TYPE | BANK_0 | 0x15)
100 #define ENC28J60_REG_EDMACSL (ETH_REG_TYPE | BANK_0 | 0x16)
101 #define ENC28J60_REG_EDMACSH (ETH_REG_TYPE | BANK_0 | 0x17)
102 #define ENC28J60_REG_EIE (ETH_REG_TYPE | BANK_0 | 0x1B)
103 #define ENC28J60_REG_EIR (ETH_REG_TYPE | BANK_0 | 0x1C)
104 #define ENC28J60_REG_ESTAT (ETH_REG_TYPE | BANK_0 | 0x1D)
105 #define ENC28J60_REG_ECON2 (ETH_REG_TYPE | BANK_0 | 0x1E)
106 #define ENC28J60_REG_ECON1 (ETH_REG_TYPE | BANK_0 | 0x1F)
107 
108 //Bank 1 registers
109 #define ENC28J60_REG_EHT0 (ETH_REG_TYPE | BANK_1 | 0x00)
110 #define ENC28J60_REG_EHT1 (ETH_REG_TYPE | BANK_1 | 0x01)
111 #define ENC28J60_REG_EHT2 (ETH_REG_TYPE | BANK_1 | 0x02)
112 #define ENC28J60_REG_EHT3 (ETH_REG_TYPE | BANK_1 | 0x03)
113 #define ENC28J60_REG_EHT4 (ETH_REG_TYPE | BANK_1 | 0x04)
114 #define ENC28J60_REG_EHT5 (ETH_REG_TYPE | BANK_1 | 0x05)
115 #define ENC28J60_REG_EHT6 (ETH_REG_TYPE | BANK_1 | 0x06)
116 #define ENC28J60_REG_EHT7 (ETH_REG_TYPE | BANK_1 | 0x07)
117 #define ENC28J60_REG_EPMM0 (ETH_REG_TYPE | BANK_1 | 0x08)
118 #define ENC28J60_REG_EPMM1 (ETH_REG_TYPE | BANK_1 | 0x09)
119 #define ENC28J60_REG_EPMM2 (ETH_REG_TYPE | BANK_1 | 0x0A)
120 #define ENC28J60_REG_EPMM3 (ETH_REG_TYPE | BANK_1 | 0x0B)
121 #define ENC28J60_REG_EPMM4 (ETH_REG_TYPE | BANK_1 | 0x0C)
122 #define ENC28J60_REG_EPMM5 (ETH_REG_TYPE | BANK_1 | 0x0D)
123 #define ENC28J60_REG_EPMM6 (ETH_REG_TYPE | BANK_1 | 0x0E)
124 #define ENC28J60_REG_EPMM7 (ETH_REG_TYPE | BANK_1 | 0x0F)
125 #define ENC28J60_REG_EPMCSL (ETH_REG_TYPE | BANK_1 | 0x10)
126 #define ENC28J60_REG_EPMCSH (ETH_REG_TYPE | BANK_1 | 0x11)
127 #define ENC28J60_REG_EPMOL (ETH_REG_TYPE | BANK_1 | 0x14)
128 #define ENC28J60_REG_EPMOH (ETH_REG_TYPE | BANK_1 | 0x15)
129 #define ENC28J60_REG_EWOLIE (ETH_REG_TYPE | BANK_1 | 0x16)
130 #define ENC28J60_REG_EWOLIR (ETH_REG_TYPE | BANK_1 | 0x17)
131 #define ENC28J60_REG_ERXFCON (ETH_REG_TYPE | BANK_1 | 0x18)
132 #define ENC28J60_REG_EPKTCNT (ETH_REG_TYPE | BANK_1 | 0x19)
133 
134 //Bank 2 registers
135 #define ENC28J60_REG_MACON1 (MAC_REG_TYPE | BANK_2 | 0x00)
136 #define ENC28J60_REG_MACON2 (MAC_REG_TYPE | BANK_2 | 0x01)
137 #define ENC28J60_REG_MACON3 (MAC_REG_TYPE | BANK_2 | 0x02)
138 #define ENC28J60_REG_MACON4 (MAC_REG_TYPE | BANK_2 | 0x03)
139 #define ENC28J60_REG_MABBIPG (MAC_REG_TYPE | BANK_2 | 0x04)
140 #define ENC28J60_REG_MAIPGL (MAC_REG_TYPE | BANK_2 | 0x06)
141 #define ENC28J60_REG_MAIPGH (MAC_REG_TYPE | BANK_2 | 0x07)
142 #define ENC28J60_REG_MACLCON1 (MAC_REG_TYPE | BANK_2 | 0x08)
143 #define ENC28J60_REG_MACLCON2 (MAC_REG_TYPE | BANK_2 | 0x09)
144 #define ENC28J60_REG_MAMXFLL (MAC_REG_TYPE | BANK_2 | 0x0A)
145 #define ENC28J60_REG_MAMXFLH (MAC_REG_TYPE | BANK_2 | 0x0B)
146 #define ENC28J60_REG_MAPHSUP (MAC_REG_TYPE | BANK_2 | 0x0D)
147 #define ENC28J60_REG_MICON (MII_REG_TYPE | BANK_2 | 0x11)
148 #define ENC28J60_REG_MICMD (MII_REG_TYPE | BANK_2 | 0x12)
149 #define ENC28J60_REG_MIREGADR (MII_REG_TYPE | BANK_2 | 0x14)
150 #define ENC28J60_REG_MIWRL (MII_REG_TYPE | BANK_2 | 0x16)
151 #define ENC28J60_REG_MIWRH (MII_REG_TYPE | BANK_2 | 0x17)
152 #define ENC28J60_REG_MIRDL (MII_REG_TYPE | BANK_2 | 0x18)
153 #define ENC28J60_REG_MIRDH (MII_REG_TYPE | BANK_2 | 0x19)
154 
155 //Bank 3 registers
156 #define ENC28J60_REG_MAADR5 (MAC_REG_TYPE | BANK_3 | 0x00)
157 #define ENC28J60_REG_MAADR6 (MAC_REG_TYPE | BANK_3 | 0x01)
158 #define ENC28J60_REG_MAADR3 (MAC_REG_TYPE | BANK_3 | 0x02)
159 #define ENC28J60_REG_MAADR4 (MAC_REG_TYPE | BANK_3 | 0x03)
160 #define ENC28J60_REG_MAADR1 (MAC_REG_TYPE | BANK_3 | 0x04)
161 #define ENC28J60_REG_MAADR2 (MAC_REG_TYPE | BANK_3 | 0x05)
162 #define ENC28J60_REG_EBSTSD (ETH_REG_TYPE | BANK_3 | 0x06)
163 #define ENC28J60_REG_EBSTCON (ETH_REG_TYPE | BANK_3 | 0x07)
164 #define ENC28J60_REG_EBSTCSL (ETH_REG_TYPE | BANK_3 | 0x08)
165 #define ENC28J60_REG_EBSTCSH (ETH_REG_TYPE | BANK_3 | 0x09)
166 #define ENC28J60_REG_MISTAT (MII_REG_TYPE | BANK_3 | 0x0A)
167 #define ENC28J60_REG_EREVID (ETH_REG_TYPE | BANK_3 | 0x12)
168 #define ENC28J60_REG_ECOCON (ETH_REG_TYPE | BANK_3 | 0x15)
169 #define ENC28J60_REG_EFLOCON (ETH_REG_TYPE | BANK_3 | 0x17)
170 #define ENC28J60_REG_EPAUSL (ETH_REG_TYPE | BANK_3 | 0x18)
171 #define ENC28J60_REG_EPAUSH (ETH_REG_TYPE | BANK_3 | 0x19)
172 
173 //PHY registers
174 #define ENC28J60_PHY_REG_PHCON1 (PHY_REG_TYPE | 0x00)
175 #define ENC28J60_PHY_REG_PHSTAT1 (PHY_REG_TYPE | 0x01)
176 #define ENC28J60_PHY_REG_PHID1 (PHY_REG_TYPE | 0x02)
177 #define ENC28J60_PHY_REG_PHID2 (PHY_REG_TYPE | 0x03)
178 #define ENC28J60_PHY_REG_PHCON2 (PHY_REG_TYPE | 0x10)
179 #define ENC28J60_PHY_REG_PHSTAT2 (PHY_REG_TYPE | 0x11)
180 #define ENC28J60_PHY_REG_PHIE (PHY_REG_TYPE | 0x12)
181 #define ENC28J60_PHY_REG_PHIR (PHY_REG_TYPE | 0x13)
182 #define ENC28J60_PHY_REG_PHLCON (PHY_REG_TYPE | 0x14)
183 
184 //EIE register
185 #define EIE_INTIE (1 << 7)
186 #define EIE_PKTIE (1 << 6)
187 #define EIE_DMAIE (1 << 5)
188 #define EIE_LINKIE (1 << 4)
189 #define EIE_TXIE (1 << 3)
190 #define EIE_WOLIE (1 << 2)
191 #define EIE_TXERIE (1 << 1)
192 #define EIE_RXERIE (1 << 0)
193 
194 //EIR register
195 #define EIR_PKTIF (1 << 6)
196 #define EIR_DMAIF (1 << 5)
197 #define EIR_LINKIF (1 << 4)
198 #define EIR_TXIF (1 << 3)
199 #define EIR_WOLIF (1 << 2)
200 #define EIR_TXERIF (1 << 1)
201 #define EIR_RXERIF (1 << 0)
202 
203 //ESTAT register
204 #define ESTAT_INT (1 << 7)
205 #define ESTAT_LATECOL (1 << 4)
206 #define ESTAT_RXBUSY (1 << 2)
207 #define ESTAT_TXABRT (1 << 1)
208 #define ESTAT_CLKRDY (1 << 0)
209 
210 //ECON2 register
211 #define ECON2_AUTOINC (1 << 7)
212 #define ECON2_PKTDEC (1 << 6)
213 #define ECON2_PWRSV (1 << 5)
214 #define ECON2_VRPS (1 << 3)
215 
216 //ECON1 register
217 #define ECON1_TXRST (1 << 7)
218 #define ECON1_RXRST (1 << 6)
219 #define ECON1_DMAST (1 << 5)
220 #define ECON1_CSUMEN (1 << 4)
221 #define ECON1_TXRTS (1 << 3)
222 #define ECON1_RXEN (1 << 2)
223 #define ECON1_BSEL1 (1 << 1)
224 #define ECON1_BSEL0 (1 << 0)
225 
226 //ERXFCON register
227 #define ERXFCON_UCEN (1 << 7)
228 #define ERXFCON_ANDOR (1 << 6)
229 #define ERXFCON_CRCEN (1 << 5)
230 #define ERXFCON_PMEN (1 << 4)
231 #define ERXFCON_MPEN (1 << 3)
232 #define ERXFCON_HTEN (1 << 2)
233 #define ERXFCON_MCEN (1 << 1)
234 #define ERXFCON_BCEN (1 << 0)
235 
236 //MACON1 register
237 #define MACON1_LOOPBK (1 << 4)
238 #define MACON1_TXPAUS (1 << 3)
239 #define MACON1_RXPAUS (1 << 2)
240 #define MACON1_PASSALL (1 << 1)
241 #define MACON1_MARXEN (1 << 0)
242 
243 //MACON2 register
244 #define MACON2_MARST (1 << 7)
245 #define MACON2_RNDRST (1 << 6)
246 #define MACON2_MARXRST (1 << 3)
247 #define MACON2_RFUNRST (1 << 2)
248 #define MACON2_MATXRST (1 << 1)
249 #define MACON2_TFUNRST (1 << 0)
250 
251 //MACON3 register
252 #define MACON3_PADCFG2 (1 << 7)
253 #define MACON3_PADCFG1 (1 << 6)
254 #define MACON3_PADCFG0 (1 << 5)
255 #define MACON3_TXCRCEN (1 << 4)
256 #define MACON3_PHDRLEN (1 << 3)
257 #define MACON3_HFRMLEN (1 << 2)
258 #define MACON3_FRMLNEN (1 << 1)
259 #define MACON3_FULDPX (1 << 0)
260 
261 #define MACON3_PADCFG(x) ((x) << 5)
262 
263 //MACON4 register
264 #define MACON4_DEFER (1 << 6)
265 #define MACON4_BPEN (1 << 5)
266 #define MACON4_NOBKOFF (1 << 4)
267 #define MACON4_LONGPRE (1 << 1)
268 #define MACON4_PUREPRE (1 << 0)
269 
270 //MAPHSUP register
271 #define MAPHSUP_RSTINTFC (1 << 7)
272 #define MAPHSUP_RSTRMII (1 << 3)
273 
274 //MICON register
275 #define MICON_RSTMII (1 << 7)
276 
277 //MICMD register
278 #define MICMD_MIISCAN (1 << 1)
279 #define MICMD_MIIRD (1 << 0)
280 
281 //EBSTCON register
282 #define EBSTCON_PSV2 (1 << 7)
283 #define EBSTCON_PSV1 (1 << 6)
284 #define EBSTCON_PSV0 (1 << 5)
285 #define EBSTCON_PSEL (1 << 4)
286 #define EBSTCON_TMSEL1 (1 << 3)
287 #define EBSTCON_TMSEL0 (1 << 2)
288 #define EBSTCON_TME (1 << 1)
289 #define EBSTCON_BISTST (1 << 0)
290 
291 //MISTAT register
292 #define MISTAT_NVALID (1 << 2)
293 #define MISTAT_SCAN (1 << 1)
294 #define MISTAT_BUSY (1 << 0)
295 
296 //ECOCON register
297 #define ECOCON_COCON2 (1 << 2)
298 #define ECOCON_COCON1 (1 << 1)
299 #define ECOCON_COCON0 (1 << 0)
300 
301 //EFLOCON register
302 #define EFLOCON_FULDPXS (1 << 2)
303 #define EFLOCON_FCEN1 (1 << 1)
304 #define EFLOCON_FCEN0 (1 << 0)
305 
306 //PHCON1 register
307 #define PHCON1_PRST (1 << 15)
308 #define PHCON1_PLOOPBK (1 << 14)
309 #define PHCON1_PPWRSV (1 << 11)
310 #define PHCON1_PDPXMD (1 << 8)
311 
312 //PHSTAT1 register
313 #define PHSTAT1_PFDPX (1 << 12)
314 #define PHSTAT1_PHDPX (1 << 11)
315 #define PHSTAT1_LLSTAT (1 << 2)
316 #define PHSTAT1_JBSTAT (1 << 1)
317 
318 //PHCON2 register
319 #define PHCON2_FRCLINK (1 << 14)
320 #define PHCON2_TXDIS (1 << 13)
321 #define PHCON2_JABBER (1 << 10)
322 #define PHCON2_HDLDIS (1 << 8)
323 
324 //PHSTAT2 register
325 #define PHSTAT2_TXSTAT (1 << 13)
326 #define PHSTAT2_RXSTAT (1 << 12)
327 #define PHSTAT2_COLSTAT (1 << 11)
328 #define PHSTAT2_LSTAT (1 << 10)
329 #define PHSTAT2_DPXSTAT (1 << 9)
330 #define PHSTAT2_PLRITY (1 << 4)
331 
332 //PHIE register
333 #define PHIE_PLNKIE (1 << 4)
334 #define PHIE_PGEIE (1 << 1)
335 
336 //PHIR register
337 #define PHIR_PLNKIF (1 << 4)
338 #define PHIR_PGIF (1 << 2)
339 
340 //PHLCON register
341 #define PHLCON_LACFG3 (1 << 11)
342 #define PHLCON_LACFG2 (1 << 10)
343 #define PHLCON_LACFG1 (1 << 9)
344 #define PHLCON_LACFG0 (1 << 8)
345 #define PHLCON_LBCFG3 (1 << 7)
346 #define PHLCON_LBCFG2 (1 << 6)
347 #define PHLCON_LBCFG1 (1 << 5)
348 #define PHLCON_LBCFG0 (1 << 4)
349 #define PHLCON_LFRQ1 (1 << 3)
350 #define PHLCON_LFRQ0 (1 << 2)
351 #define PHLCON_STRCH (1 << 1)
352 
353 #define PHLCON_LACFG(x) ((x) << 8)
354 #define PHLCON_LBCFG(x) ((x) << 4)
355 #define PHLCON_LFRQ(x) ((x) << 2)
356 
357 //Per-packet control byte
358 #define TX_CTRL_PHUGEEN (1 << 3)
359 #define TX_CTRL_PPADEN (1 << 2)
360 #define TX_CTRL_PCRCEN (1 << 1)
361 #define TX_CTRL_POVERRIDE (1 << 0)
362 
363 //Receive status vector
364 #define RSV_VLAN_TYPE 0x4000
365 #define RSV_UNKNOWN_OPCODE 0x2000
366 #define RSV_PAUSE_CONTROL_FRAME 0x1000
367 #define RSV_CONTROL_FRAME 0x0800
368 #define RSV_DRIBBLE_NIBBLE 0x0400
369 #define RSV_BROADCAST_PACKET 0x0200
370 #define RSV_MULTICAST_PACKET 0x0100
371 #define RSV_RECEIVED_OK 0x0080
372 #define RSV_LENGTH_OUT_OF_RANGE 0x0040
373 #define RSV_LENGTH_CHECK_ERROR 0x0020
374 #define RSV_CRC_ERROR 0x0010
375 #define RSV_CARRIER_EVENT 0x0004
376 #define RSV_DROP_EVENT 0x0001
377 
378 //C++ guard
379 #ifdef __cplusplus
380  extern "C" {
381 #endif
382 
383 
384 /**
385  * @brief ENC28J60 driver context
386  **/
387 
388 typedef struct
389 {
390  uint16_t currentBank; ///<Current bank
391  uint16_t nextPacket; ///<Next packet in the receive buffer
392  uint8_t *rxBuffer; ///<Receive buffer
394 
395 
396 //ENC28J60 driver
397 extern const NicDriver enc28j60Driver;
398 
399 //ENC28J60 related functions
400 error_t enc28j60Init(NetInterface *interface);
401 
402 void enc28j60Tick(NetInterface *interface);
403 
404 void enc28j60EnableIrq(NetInterface *interface);
405 void enc28j60DisableIrq(NetInterface *interface);
407 void enc28j60EventHandler(NetInterface *interface);
408 
410  const NetBuffer *buffer, size_t offset);
411 
413 
415 
416 void enc28j60SoftReset(NetInterface *interface);
417 void enc28j60SelectBank(NetInterface *interface, uint16_t address);
418 
419 void enc28j60WriteReg(NetInterface *interface, uint16_t address, uint8_t data);
420 uint8_t enc28j60ReadReg(NetInterface *interface, uint16_t address);
421 
422 void enc28j60WritePhyReg(NetInterface *interface, uint16_t address, uint16_t data);
423 uint16_t enc28j60ReadPhyReg(NetInterface *interface, uint16_t address);
424 
425 void enc28j60WriteBuffer(NetInterface *interface,
426  const NetBuffer *buffer, size_t offset);
427 
428 void enc28j60ReadBuffer(NetInterface *interface,
429  uint8_t *data, size_t length);
430 
431 void enc28j60SetBit(NetInterface *interface, uint16_t address, uint16_t mask);
432 void enc28j60ClearBit(NetInterface *interface, uint16_t address, uint16_t mask);
433 
434 uint32_t enc28j60CalcCrc(const void *data, size_t length);
435 
436 void enc28j60DumpReg(NetInterface *interface);
437 void enc28j60DumpPhyReg(NetInterface *interface);
438 
439 //C++ guard
440 #ifdef __cplusplus
441  }
442 #endif
443 
444 #endif
uint16_t enc28j60ReadPhyReg(NetInterface *interface, uint16_t address)
Read PHY register.
uint16_t currentBank
Current bank.
error_t enc28j60Init(NetInterface *interface)
ENC28J60 controller initialization.
void enc28j60WriteReg(NetInterface *interface, uint16_t address, uint8_t data)
Write ENC28J60 register.
void enc28j60DisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver enc28j60Driver
ENC28J60 driver.
ENC28J60 driver context.
void enc28j60DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
uint8_t * rxBuffer
Receive buffer.
uint8_t enc28j60ReadReg(NetInterface *interface, uint16_t address)
Read ENC28J60 register.
error_t enc28j60SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void enc28j60SetBit(NetInterface *interface, uint16_t address, uint16_t mask)
Set bit field.
uint8_t mask
Definition: web_socket.h:315
void enc28j60ReadBuffer(NetInterface *interface, uint8_t *data, size_t length)
Read SRAM buffer.
void enc28j60EnableIrq(NetInterface *interface)
Enable interrupts.
void enc28j60Tick(NetInterface *interface)
ENC28J60 timer handler.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
error_t enc28j60UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void enc28j60EventHandler(NetInterface *interface)
ENC28J60 event handler.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
void enc28j60DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
error_t enc28j60ReceivePacket(NetInterface *interface)
Receive a packet.
uint32_t enc28j60CalcCrc(const void *data, size_t length)
CRC calculation using the polynomial 0x4C11DB7.
void enc28j60ClearBit(NetInterface *interface, uint16_t address, uint16_t mask)
Clear bit field.
void enc28j60SoftReset(NetInterface *interface)
ENC28J60 controller reset.
void enc28j60WriteBuffer(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Write SRAM buffer.
bool_t enc28j60IrqHandler(NetInterface *interface)
ENC28J60 interrupt service routine.
uint16_t nextPacket
Next packet in the receive buffer.
uint8_t length
Definition: dtls_misc.h:140
int bool_t
Definition: compiler_port.h:47
void enc28j60SelectBank(NetInterface *interface, uint16_t address)
Bank selection.
void enc28j60WritePhyReg(NetInterface *interface, uint16_t address, uint16_t data)
Write PHY register.