ksz8463_driver.c
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1 /**
2  * @file ksz8463_driver.c
3  * @brief KSZ8463 3-port Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "core/net.h"
36 #include "core/ethernet_misc.h"
38 #include "debug.h"
39 
40 
41 /**
42  * @brief KSZ8463 Ethernet switch driver
43  **/
44 
46 {
54 };
55 
56 
57 /**
58  * @brief Tail tag rules (host to KSZ8463)
59  **/
60 
61 const uint8_t ksz8463IngressTailTag[3] =
62 {
63  0,
66 };
67 
68 
69 /**
70  * @brief KSZ8463 Ethernet switch initialization
71  * @param[in] interface Underlying network interface
72  * @return Error code
73  **/
74 
76 {
77  uint_t port;
78  uint16_t temp;
79 
80  //Debug message
81  TRACE_INFO("Initializing KSZ8463...\r\n");
82 
83  //SPI slave mode?
84  if(interface->spiDriver != NULL)
85  {
86  //Initialize SPI
87  interface->spiDriver->init();
88 
89  //Wait for the serial interface to be ready
90  do
91  {
92  //Read CIDER register
93  temp = ksz8463ReadSwitchReg(interface, KSZ8463_CIDER);
94 
95  //The returned data is invalid until the serial interface is ready
97 
98 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
99  //Tail tagging mode?
100  if(interface->port != 0)
101  {
102  //Enable tail tag feature
103  temp = ksz8463ReadSwitchReg(interface, KSZ8463_SGCR8);
105  ksz8463WriteSwitchReg(interface, KSZ8463_SGCR8, temp);
106 
107  //Loop through ports
109  {
110  //Disable packet transmission and switch address learning
111  temp = ksz8463ReadSwitchReg(interface, KSZ8463_PnCR2(port));
112  temp &= ~KSZ8463_PnCR2_TRANSMIT_EN;
114  ksz8463WriteSwitchReg(interface, KSZ8463_PnCR2(port), temp);
115  }
116  }
117  else
118 #endif
119  {
120  //Disable tail tag feature
121  temp = ksz8463ReadSwitchReg(interface, KSZ8463_SGCR8);
122  temp &= ~KSZ8463_SGCR8_TAIL_TAG_EN;
123  ksz8463WriteSwitchReg(interface, KSZ8463_SGCR8, temp);
124 
125  //Loop through ports
127  {
128  //Enable transmission, reception and switch address learning
129  temp = ksz8463ReadSwitchReg(interface, KSZ8463_PnCR2(port));
132  ksz8463WriteSwitchReg(interface, KSZ8463_PnCR2(port), temp);
133  }
134  }
135 
136  //Dump switch registers for debugging purpose
137  ksz8463DumpSwitchReg(interface);
138  }
139  else
140  {
141  //Loop through ports
143  {
144  //Debug message
145  TRACE_DEBUG("Port %u:\r\n", port);
146  //Dump PHY registers for debugging purpose
147  ksz8463DumpPhyReg(interface, port);
148  }
149  }
150 
151  //Force the TCP/IP stack to poll the link state at startup
152  interface->phyEvent = TRUE;
153  //Notify the TCP/IP stack of the event
155 
156  //Successful initialization
157  return NO_ERROR;
158 }
159 
160 
161 /**
162  * @brief Get link state
163  * @param[in] interface Underlying network interface
164  * @param[in] port Port number
165  * @return Link state
166  **/
167 
169 {
170  uint16_t status;
171  bool_t linkState;
172 
173  //Check port number
174  if(port >= KSZ8463_PORT1 && port <= KSZ8463_PORT2)
175  {
176  //Get exclusive access
178 
179  //SPI slave mode?
180  if(interface->spiDriver != NULL)
181  {
182  //Read port status register
183  status = ksz8463ReadSwitchReg(interface, KSZ8463_PnSR(port));
184 
185  //Retrieve current link state
186  linkState = (status & KSZ8463_PnSR_LINK_STATUS) ? TRUE : FALSE;
187  }
188  else
189  {
190  //Read status register
191  status = ksz8463ReadPhyReg(interface, port, KSZ8463_BMSR);
192 
193  //Retrieve current link state
194  linkState = (status & KSZ8463_BMSR_LINK_STATUS) ? TRUE : FALSE;
195  }
196 
197  //Release exclusive access
199  }
200  else
201  {
202  //The specified port number is not valid
203  linkState = FALSE;
204  }
205 
206  //Return link status
207  return linkState;
208 }
209 
210 
211 /**
212  * @brief KSZ8463 timer handler
213  * @param[in] interface Underlying network interface
214  **/
215 
216 void ksz8463Tick(NetInterface *interface)
217 {
218  uint_t port;
219  uint16_t status;
220  bool_t linkState;
221 
222 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
223  //Tail tagging mode?
224  if(interface->port != 0)
225  {
226  uint_t i;
227  NetInterface *virtualInterface;
228 
229  //SPI slave mode?
230  if(interface->spiDriver != NULL)
231  {
232  //Loop through network interfaces
233  for(i = 0; i < NET_INTERFACE_COUNT; i++)
234  {
235  //Point to the current interface
236  virtualInterface = &netInterface[i];
237 
238  //Check whether the current virtual interface is attached to the
239  //physical interface
240  if(virtualInterface == interface || virtualInterface->parent == interface)
241  {
242  //The tail tag is used to indicate the source/destination port
243  port = virtualInterface->port;
244 
245  //Valid port?
246  if(port >= KSZ8463_PORT1 && port <= KSZ8463_PORT2)
247  {
248  //Read port status register
249  status = ksz8463ReadSwitchReg(interface, KSZ8463_PnSR(port));
250 
251  //Retrieve current link state
252  linkState = (status & KSZ8463_PnSR_LINK_STATUS) ? TRUE : FALSE;
253 
254  //Link up or link down event?
255  if(linkState != virtualInterface->linkState)
256  {
257  //Set event flag
258  interface->phyEvent = TRUE;
259  //Notify the TCP/IP stack of the event
261  }
262  }
263  }
264  }
265  }
266  }
267  else
268 #endif
269  {
270  //Initialize link state
271  linkState = FALSE;
272 
273  //Loop through ports
275  {
276  //SPI slave mode?
277  if(interface->spiDriver != NULL)
278  {
279  //Read port status register
280  status = ksz8463ReadSwitchReg(interface, KSZ8463_PnSR(port));
281 
282  //Retrieve current link state
283  if(status & KSZ8463_PnSR_LINK_STATUS)
284  linkState = TRUE;
285  }
286  else
287  {
288  //Read status register
289  status = ksz8463ReadPhyReg(interface, port, KSZ8463_BMSR);
290 
291  //Retrieve current link state
292  if(status & KSZ8463_BMSR_LINK_STATUS)
293  linkState = TRUE;
294  }
295  }
296 
297  //Link up or link down event?
298  if(linkState != interface->linkState)
299  {
300  //Set event flag
301  interface->phyEvent = TRUE;
302  //Notify the TCP/IP stack of the event
304  }
305  }
306 }
307 
308 
309 /**
310  * @brief Enable interrupts
311  * @param[in] interface Underlying network interface
312  **/
313 
315 {
316 }
317 
318 
319 /**
320  * @brief Disable interrupts
321  * @param[in] interface Underlying network interface
322  **/
323 
325 {
326 }
327 
328 
329 /**
330  * @brief KSZ8463 event handler
331  * @param[in] interface Underlying network interface
332  **/
333 
335 {
336  uint_t port;
337  uint16_t status;
338  bool_t linkState;
339 
340 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
341  //Tail tagging mode?
342  if(interface->port != 0)
343  {
344  uint_t i;
345  NetInterface *virtualInterface;
346 
347  //SPI slave mode?
348  if(interface->spiDriver != NULL)
349  {
350  //Loop through network interfaces
351  for(i = 0; i < NET_INTERFACE_COUNT; i++)
352  {
353  //Point to the current interface
354  virtualInterface = &netInterface[i];
355 
356  //Check whether the current virtual interface is attached to the
357  //physical interface
358  if(virtualInterface == interface ||
359  virtualInterface->parent == interface)
360  {
361  //The tail tag is used to indicate the source/destination port
362  port = virtualInterface->port;
363 
364  //Valid port?
365  if(port >= KSZ8463_PORT1 && port <= KSZ8463_PORT2)
366  {
367  //Read port status register
368  status = ksz8463ReadSwitchReg(interface, KSZ8463_PnSR(port));
369 
370  //Retrieve current link state
371  linkState = (status & KSZ8463_PnSR_LINK_STATUS) ? TRUE : FALSE;
372 
373  //Link up event?
374  if(linkState && !virtualInterface->linkState)
375  {
376  //Adjust MAC configuration parameters for proper operation
377  interface->linkSpeed = NIC_LINK_SPEED_100MBPS;
378  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
379  interface->nicDriver->updateMacConfig(interface);
380 
381  //Check current speed
382  if(status & KSZ8463_PnSR_OP_SPEED)
383  virtualInterface->linkSpeed = NIC_LINK_SPEED_100MBPS;
384  else
385  virtualInterface->linkSpeed = NIC_LINK_SPEED_10MBPS;
386 
387  //Check duplex mode
388  if(status & KSZ8463_PnSR_OP_DUPLEX)
389  virtualInterface->duplexMode = NIC_FULL_DUPLEX_MODE;
390  else
391  virtualInterface->duplexMode = NIC_HALF_DUPLEX_MODE;
392 
393  //Update link state
394  virtualInterface->linkState = TRUE;
395 
396  //Process link state change event
397  nicNotifyLinkChange(virtualInterface);
398  }
399  //Link down event
400  else if(!linkState && virtualInterface->linkState)
401  {
402  //Update link state
403  virtualInterface->linkState = FALSE;
404 
405  //Process link state change event
406  nicNotifyLinkChange(virtualInterface);
407  }
408  }
409  }
410  }
411  }
412  }
413  else
414 #endif
415  {
416  //Initialize link state
417  linkState = FALSE;
418 
419  //Loop through ports
421  {
422  //SPI slave mode?
423  if(interface->spiDriver != NULL)
424  {
425  //Read port status register
426  status = ksz8463ReadSwitchReg(interface, KSZ8463_PnSR(port));
427 
428  //Retrieve current link state
429  if(status & KSZ8463_PnSR_LINK_STATUS)
430  linkState = TRUE;
431  }
432  else
433  {
434  //Read status register
435  status = ksz8463ReadPhyReg(interface, port, KSZ8463_BMSR);
436 
437  //Retrieve current link state
438  if(status & KSZ8463_BMSR_LINK_STATUS)
439  linkState = TRUE;
440  }
441  }
442 
443  //Link up event?
444  if(linkState)
445  {
446  //Adjust MAC configuration parameters for proper operation
447  interface->linkSpeed = NIC_LINK_SPEED_100MBPS;
448  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
449  interface->nicDriver->updateMacConfig(interface);
450 
451  //Update link state
452  interface->linkState = TRUE;
453  }
454  else
455  {
456  //Update link state
457  interface->linkState = FALSE;
458  }
459 
460  //Process link state change event
461  nicNotifyLinkChange(interface);
462  }
463 }
464 
465 
466 /**
467  * @brief Add tail tag to Ethernet frame
468  * @param[in] interface Underlying network interface
469  * @param[in] buffer Multi-part buffer containing the payload
470  * @param[in,out] offset Offset to the first payload byte
471  * @param[in] port Switch port identifier
472  * @param[in,out] type Ethernet type
473  * @return Error code
474  **/
475 
477  size_t *offset, uint8_t port, uint16_t *type)
478 {
479 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
480  error_t error;
481  size_t length;
482  const uint8_t *tailTag;
483 
484  //Valid port?
485  if(port >= KSZ8463_PORT1 && port <= KSZ8463_PORT2)
486  {
487  //The one byte tail tagging is used to indicate the destination port
488  tailTag = &ksz8463IngressTailTag[port];
489 
490  //Retrieve the length of the frame
491  length = netBufferGetLength(buffer) - *offset;
492 
493  //The host controller should manually add padding to the packet before
494  //inserting the tail tag
495  error = ethPadFrame(buffer, &length);
496 
497  //Check status code
498  if(!error)
499  {
500  //The tail tag is inserted at the end of the packet, just before the CRC
501  error = netBufferAppend(buffer, tailTag, sizeof(uint8_t));
502  }
503  }
504  else
505  {
506  //Invalid port identifier
507  error = ERROR_WRONG_IDENTIFIER;
508  }
509 
510  //Return status code
511  return error;
512 #else
513  //Tail tagging mode is not implemented
514  return NO_ERROR;
515 #endif
516 }
517 
518 
519 /**
520  * @brief Decode tail tag from incoming Ethernet frame
521  * @param[in] interface Underlying network interface
522  * @param[in,out] frame Pointer to the received Ethernet frame
523  * @param[in,out] length Length of the frame, in bytes
524  * @param[out] port Switch port identifier
525  * @return Error code
526  **/
527 
528 error_t ksz8463UntagFrame(NetInterface *interface, uint8_t **frame,
529  size_t *length, uint8_t *port)
530 {
531 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
532  error_t error;
533  uint8_t *tailTag;
534 
535  //Valid Ethernet frame received?
536  if(*length >= (sizeof(EthHeader) + sizeof(uint8_t)))
537  {
538  //The tail tag is inserted at the end of the packet, just before the CRC
539  tailTag = *frame + *length - sizeof(uint8_t);
540 
541  //The one byte tail tagging is used to indicate the source port
542  *port = KSZ8463_TAIL_TAG_DECODE(*tailTag);
543 
544  //Strip tail tag from Ethernet frame
545  *length -= sizeof(uint8_t);
546 
547  //Successful processing
548  error = NO_ERROR;
549  }
550  else
551  {
552  //Drop the received frame
553  error = ERROR_INVALID_LENGTH;
554  }
555 
556  //Return status code
557  return error;
558 #else
559  //Tail tagging mode is not implemented
560  return NO_ERROR;
561 #endif
562 }
563 
564 
565 /**
566  * @brief Write PHY register
567  * @param[in] interface Underlying network interface
568  * @param[in] port Port number
569  * @param[in] address PHY register address
570  * @param[in] data Register value
571  **/
572 
573 void ksz8463WritePhyReg(NetInterface *interface, uint8_t port,
574  uint8_t address, uint16_t data)
575 {
576  //Write the specified PHY register
577  interface->nicDriver->writePhyReg(SMI_OPCODE_WRITE, port, address, data);
578 }
579 
580 
581 /**
582  * @brief Read PHY register
583  * @param[in] interface Underlying network interface
584  * @param[in] port Port number
585  * @param[in] address PHY register address
586  * @return Register value
587  **/
588 
589 uint16_t ksz8463ReadPhyReg(NetInterface *interface, uint8_t port,
590  uint8_t address)
591 {
592  //Read the specified PHY register
593  return interface->nicDriver->readPhyReg(SMI_OPCODE_READ, port, address);
594 }
595 
596 
597 /**
598  * @brief Dump PHY registers for debugging purpose
599  * @param[in] interface Underlying network interface
600  * @param[in] port Port number
601  **/
602 
603 void ksz8463DumpPhyReg(NetInterface *interface, uint8_t port)
604 {
605  uint8_t i;
606 
607  //Loop through PHY registers
608  for(i = 0; i < 32; i++)
609  {
610  //Display current PHY register
611  TRACE_DEBUG("%02" PRIu8 ": 0x%04" PRIX16 "\r\n", i,
612  ksz8463ReadPhyReg(interface, port, i));
613  }
614 
615  //Terminate with a line feed
616  TRACE_DEBUG("\r\n");
617 }
618 
619 
620 /**
621  * @brief Write switch register
622  * @param[in] interface Underlying network interface
623  * @param[in] address Switch register address
624  * @param[in] data Register value
625  **/
626 
627 void ksz8463WriteSwitchReg(NetInterface *interface, uint16_t address,
628  uint16_t data)
629 {
630  uint16_t command;
631 
632  //SPI slave mode?
633  if(interface->spiDriver != NULL)
634  {
635  //Set up a write operation
636  command = KSZ8463_SPI_CMD_WRITE;
637 
638  //The byte enable bits are set to indicate which bytes will be
639  //transferred in the data phase
640  if(address & 0x02)
642  else
644 
645  //Set register address
646  command |= (address << 4) & KSZ8463_SPI_CMD_ADDR;
647 
648  //Pull the CS pin low
649  interface->spiDriver->assertCs();
650 
651  //Write 16-bit command
652  interface->spiDriver->transfer(MSB(command));
653  interface->spiDriver->transfer(LSB(command));
654 
655  //Write 16-bit data
656  interface->spiDriver->transfer(LSB(data));
657  interface->spiDriver->transfer(MSB(data));
658 
659  //Terminate the operation by raising the CS pin
660  interface->spiDriver->deassertCs();
661  }
662  else
663  {
664  //The MDC/MDIO interface does not have access to all the configuration
665  //registers. It can only access the standard MIIM registers
666  }
667 }
668 
669 
670 /**
671  * @brief Read switch register
672  * @param[in] interface Underlying network interface
673  * @param[in] address Switch register address
674  * @return Register value
675  **/
676 
677 uint16_t ksz8463ReadSwitchReg(NetInterface *interface, uint16_t address)
678 {
679  uint16_t data;
680  uint16_t command;
681 
682  //SPI slave mode?
683  if(interface->spiDriver != NULL)
684  {
685  //Set up a read operation
686  command = KSZ8463_SPI_CMD_READ;
687 
688  //The byte enable bits are set to indicate which bytes will be
689  //transferred in the data phase
690  if(address & 0x02)
692  else
694 
695  //Set register address
696  command |= (address << 4) & KSZ8463_SPI_CMD_ADDR;
697 
698  //Pull the CS pin low
699  interface->spiDriver->assertCs();
700 
701  //Write 16-bit command
702  interface->spiDriver->transfer(MSB(command));
703  interface->spiDriver->transfer(LSB(command));
704 
705  //Read 16-bit data
706  data = interface->spiDriver->transfer(0xFF);
707  data |= interface->spiDriver->transfer(0xFF) << 8;
708 
709  //Terminate the operation by raising the CS pin
710  interface->spiDriver->deassertCs();
711  }
712  else
713  {
714  //The MDC/MDIO interface does not have access to all the configuration
715  //registers. It can only access the standard MIIM registers
716  data = 0;
717  }
718 
719  //Return register value
720  return data;
721 }
722 
723 
724 /**
725  * @brief Dump switch registers for debugging purpose
726  * @param[in] interface Underlying network interface
727  **/
728 
730 {
731  uint16_t i;
732 
733  //Loop through switch registers
734  for(i = 0; i < 256; i += 2)
735  {
736  //Display current switch register
737  TRACE_DEBUG("0x%02" PRIX16 " (%02" PRIu16 ") : 0x%04" PRIX16 "\r\n",
738  i, i, ksz8463ReadSwitchReg(interface, i));
739  }
740 
741  //Terminate with a line feed
742  TRACE_DEBUG("\r\n");
743 }
#define KSZ8463_PnCR2(port)
#define KSZ8463_SPI_CMD_READ
void nicNotifyLinkChange(NetInterface *interface)
Process link state change notification.
Definition: nic.c:536
#define KSZ8463_CIDER
#define MSB(x)
Definition: os_port.h:58
void ksz8463WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
TCP/IP stack core.
#define KSZ8463_CIDER_FAMILY_ID_DEFAULT
Debugging facilities.
#define KSZ8463_TAIL_TAG_ENCODE(port)
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define KSZ8463_PnSR_OP_SPEED
#define KSZ8463_PnSR_OP_DUPLEX
#define KSZ8463_BMSR_LINK_STATUS
#define KSZ8463_SGCR8_TAIL_TAG_EN
Helper functions for Ethernet.
bool_t ksz8463GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
error_t ksz8463TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
#define KSZ8463_PnSR(port)
char_t type
#define SMI_OPCODE_READ
Definition: nic.h:63
void ksz8463DisableIrq(NetInterface *interface)
Disable interrupts.
#define LSB(x)
Definition: os_port.h:54
#define KSZ8463_SPI_CMD_B2
#define KSZ8463_BMSR
error_t ethPadFrame(NetBuffer *buffer, size_t *length)
Ethernet frame padding.
__start_packed struct @110 EthHeader
Ethernet frame header.
#define TRUE
Definition: os_port.h:50
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define KSZ8463_SPI_CMD_B3
#define KSZ8463_SPI_CMD_B1
#define KSZ8463_CIDER_FAMILY_ID
PHY driver.
Definition: nic.h:214
#define KSZ8463_SPI_CMD_WRITE
#define KSZ8463_PnCR2_TRANSMIT_EN
#define KSZ8463_SPI_CMD_B0
#define NET_INTERFACE_COUNT
Definition: net.h:109
#define KSZ8463_PORT1
uint16_t ksz8463ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
#define KSZ8463_PnSR_LINK_STATUS
error_t ksz8463Init(NetInterface *interface)
KSZ8463 Ethernet switch initialization.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
NetInterface netInterface[NET_INTERFACE_COUNT]
Definition: net.c:76
#define KSZ8463_PnCR2_LEARNING_DIS
#define TRACE_INFO(...)
Definition: debug.h:94
#define KSZ8463_SPI_CMD_ADDR
Success.
Definition: error.h:44
Ipv6Addr address
OsEvent netEvent
Definition: net.c:74
uint16_t ksz8463ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
KSZ8463 3-port Ethernet switch.
unsigned int uint_t
Definition: compiler_port.h:45
error_t netBufferAppend(NetBuffer *dest, const void *src, size_t length)
Append data a multi-part buffer.
Definition: net_mem.c:586
void osReleaseMutex(OsMutex *mutex)
Release ownership of the specified mutex object.
void ksz8463DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
void ksz8463EnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t port
Definition: dns_common.h:223
void ksz8463Tick(NetInterface *interface)
KSZ8463 timer handler.
#define KSZ8463_SGCR8
void ksz8463DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
#define KSZ8463_PORT2
OsMutex netMutex
Definition: net.c:72
const uint8_t ksz8463IngressTailTag[3]
Tail tag rules (host to KSZ8463)
void ksz8463EventHandler(NetInterface *interface)
KSZ8463 event handler.
error_t ksz8463UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
uint8_t length
Definition: dtls_misc.h:142
#define FALSE
Definition: os_port.h:46
void ksz8463WriteSwitchReg(NetInterface *interface, uint16_t address, uint16_t data)
Write switch register.
int bool_t
Definition: compiler_port.h:49
const PhyDriver ksz8463PhyDriver
KSZ8463 Ethernet switch driver.
void osAcquireMutex(OsMutex *mutex)
Acquire ownership of the specified mutex object.
#define KSZ8463_TAIL_TAG_DECODE(tag)
#define KSZ8463_PnCR2_RECEIVE_EN
#define TRACE_DEBUG(...)
Definition: debug.h:106