ksz8463_driver.h
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1 /**
2  * @file ksz8463_driver.h
3  * @brief KSZ8463 3-port Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 #ifndef _KSZ8463_DRIVER_H
32 #define _KSZ8463_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ8463 ports
38 #define KSZ8463_PORT1 1
39 #define KSZ8463_PORT2 2
40 
41 //SPI command byte
42 #define KSZ8463_SPI_CMD_READ 0x0000
43 #define KSZ8463_SPI_CMD_WRITE 0x8000
44 #define KSZ8463_SPI_CMD_ADDR 0x7FC0
45 #define KSZ8463_SPI_CMD_B3 0x0020
46 #define KSZ8463_SPI_CMD_B2 0x0010
47 #define KSZ8463_SPI_CMD_B1 0x0008
48 #define KSZ8463_SPI_CMD_B0 0x0004
49 
50 //KSZ8463 PHY registers
51 #define KSZ8463_BMCR 0x00
52 #define KSZ8463_BMSR 0x01
53 #define KSZ8463_PHYID1 0x02
54 #define KSZ8463_PHYID2 0x03
55 #define KSZ8463_ANAR 0x04
56 #define KSZ8463_ANLPAR 0x05
57 #define KSZ8463_LINKMD 0x1D
58 #define KSZ8463_PHYSCS 0x1F
59 
60 //KSZ8463 Switch registers
61 #define KSZ8463_CIDER 0x00
62 #define KSZ8463_SGCR1 0x02
63 #define KSZ8463_SGCR2 0x04
64 #define KSZ8463_SGCR3 0x06
65 #define KSZ8463_SGCR6 0x0C
66 #define KSZ8463_SGCR7 0x0E
67 #define KSZ8463_P1CR1 0x6C
68 #define KSZ8463_P1CR2 0x6E
69 #define KSZ8463_P1SR 0x80
70 #define KSZ8463_P2CR1 0x84
71 #define KSZ8463_P2CR2 0x86
72 #define KSZ8463_P2SR 0x98
73 #define KSZ8463_P3CR1 0x9C
74 #define KSZ8463_P3CR2 0x9E
75 #define KSZ8463_SGCR8 0xAC
76 
77 //KSZ8463 Switch register access macros
78 #define KSZ8463_PnCR1(port) (0x54 + ((port) * 0x18))
79 #define KSZ8463_PnCR2(port) (0x56 + ((port) * 0x18))
80 #define KSZ8463_PnSR(port) (0x68 + ((port) * 0x18))
81 
82 //Basic Control register
83 #define KSZ8463_BMCR_LOOPBACK 0x4000
84 #define KSZ8463_BMCR_FORCE_100 0x2000
85 #define KSZ8463_BMCR_AN_EN 0x1000
86 #define KSZ8463_BMCR_POWER_DOWN 0x0800
87 #define KSZ8463_BMCR_ISOLATE 0x0400
88 #define KSZ8463_BMCR_RESTART_AN 0x0200
89 #define KSZ8463_BMCR_FORCE_FULL_DUPLEX 0x0100
90 #define KSZ8463_BMCR_COL_TEST 0x0080
91 #define KSZ8463_BMCR_HP_MDIX 0x0020
92 #define KSZ8463_BMCR_FORCE_MDI 0x0010
93 #define KSZ8463_BMCR_AUTO_MDIX_DIS 0x0008
94 #define KSZ8463_BMCR_FAR_END_FAULT_DIS 0x0004
95 #define KSZ8463_BMCR_TRANSMIT_DIS 0x0002
96 #define KSZ8463_BMCR_LED_DIS 0x0001
97 
98 //Basic Status register
99 #define KSZ8463_BMSR_100BT4 0x8000
100 #define KSZ8463_BMSR_100BTX_FD 0x4000
101 #define KSZ8463_BMSR_100BTX_HD 0x2000
102 #define KSZ8463_BMSR_10BT_FD 0x1000
103 #define KSZ8463_BMSR_10BT_HD 0x0800
104 #define KSZ8463_BMSR_PREAMBLE_SUPPR 0x0040
105 #define KSZ8463_BMSR_AN_COMPLETE 0x0020
106 #define KSZ8463_BMSR_FAR_END_FAULT 0x0010
107 #define KSZ8463_BMSR_AN_CAPABLE 0x0008
108 #define KSZ8463_BMSR_LINK_STATUS 0x0004
109 #define KSZ8463_BMSR_JABBER_TEST 0x0002
110 #define KSZ8463_BMSR_EXTENDED_CAPABLE 0x0001
111 
112 //PHYID High register
113 #define KSZ8463_PHYID1_DEFAULT 0x0022
114 
115 //PHYID Low register
116 #define KSZ8463_PHYID2_DEFAULT 0x1430
117 
118 //Auto-Negotiation Advertisement Ability register
119 #define KSZ8463_ANAR_NEXT_PAGE 0x8000
120 #define KSZ8463_ANAR_REMOTE_FAULT 0x2000
121 #define KSZ8463_ANAR_PAUSE 0x0400
122 #define KSZ8463_ANAR_100BTX_FD 0x0100
123 #define KSZ8463_ANAR_100BTX_HD 0x0080
124 #define KSZ8463_ANAR_10BT_FD 0x0040
125 #define KSZ8463_ANAR_10BT_HD 0x0020
126 #define KSZ8463_ANAR_SELECTOR 0x001F
127 #define KSZ8463_ANAR_SELECTOR_DEFAULT 0x0001
128 
129 //Auto-Negotiation Link Partner Ability register
130 #define KSZ8463_ANLPAR_NEXT_PAGE 0x8000
131 #define KSZ8463_ANLPAR_LP_ACK 0x4000
132 #define KSZ8463_ANLPAR_REMOTE_FAULT 0x2000
133 #define KSZ8463_ANLPAR_PAUSE 0x0400
134 #define KSZ8463_ANLPAR_100BTX_FD 0x0100
135 #define KSZ8463_ANLPAR_100BTX_HD 0x0080
136 #define KSZ8463_ANLPAR_10BT_FD 0x0040
137 #define KSZ8463_ANLPAR_10BT_HD 0x0020
138 
139 //LinkMD Control/Status register
140 #define KSZ8463_LINKMD_TEST_EN 0x8000
141 #define KSZ8463_LINKMD_RESULT 0x6000
142 #define KSZ8463_LINKMD_SHORT 0x1000
143 #define KSZ8463_LINKMD_FAULT_COUNT 0x01FF
144 
145 //PHY Special Control/Status register
146 #define KSZ8463_PHYSCS_POL_REVERSE 0x0020
147 #define KSZ8463_PHYSCS_MDIX_STATUS 0x0010
148 #define KSZ8463_PHYSCS_FORCE_LINK 0x0008
149 #define KSZ8463_PHYSCS_EEE_EN 0x0004
150 #define KSZ8463_PHYSCS_REMOTE_LOOPBACK 0x0002
151 
152 //Chip ID And Enable register
153 #define KSZ8463_CIDER_FAMILY_ID 0xFF00
154 #define KSZ8463_CIDER_FAMILY_ID_DEFAULT 0x8400
155 #define KSZ8463_CIDER_CHIP_ID 0x00F0
156 #define KSZ8463_CIDER_CHIP_ID_ML_FML 0x0040
157 #define KSZ8463_CIDER_CHIP_ID_RL_FRL 0x0050
158 #define KSZ8463_CIDER_REVISION_ID 0x000E
159 #define KSZ8463_CIDER_START_SWITCH 0x0001
160 
161 //Port N Control 2 register
162 #define KSZ8463_PnCR2_INGRESS_VLAN_FILT 0x4000
163 #define KSZ8463_PnCR2_DISCARD_NON_PVID_PACKETS 0x2000
164 #define KSZ8463_PnCR2_FORCE_FLOW_CTRL 0x1000
165 #define KSZ8463_PnCR2_BACK_PRESSURE_EN 0x0800
166 #define KSZ8463_PnCR2_TRANSMIT_EN 0x0400
167 #define KSZ8463_PnCR2_RECEIVE_EN 0x0200
168 #define KSZ8463_PnCR2_LEARNING_DIS 0x0100
169 #define KSZ8463_PnCR2_SNIFFER_PORT 0x0080
170 #define KSZ8463_PnCR2_RECEIVE_SNIFF 0x0040
171 #define KSZ8463_PnCR2_TRANSMIT_SNIFF 0x0020
172 #define KSZ8463_PnCR2_USER_PRIO_CEILING 0x0008
173 #define KSZ8463_PnCR2_PORT_VLAN_MEMBERSHIP 0x0007
174 
175 //Port N Status register
176 #define KSZ8463_PnSR_HP_MDIX 0x8000
177 #define KSZ8463_PnSR_POL_REVERSE 0x2000
178 #define KSZ8463_PnSR_TX_FLOW_CTRL_EN 0x1000
179 #define KSZ8463_PnSR_RX_FLOW_CTRL_EN 0x0800
180 #define KSZ8463_PnSR_OP_SPEED 0x0400
181 #define KSZ8463_PnSR_OP_DUPLEX 0x0200
182 #define KSZ8463_PnSR_FAR_END_FAULT 0x0100
183 #define KSZ8463_PnSR_MDIX_STATUS 0x0080
184 #define KSZ8463_PnSR_AN_DONE 0x0040
185 #define KSZ8463_PnSR_LINK_STATUS 0x0020
186 #define KSZ8463_PnSR_LP_FLOW_CTRL_CAPABLE 0x0010
187 #define KSZ8463_PnSR_LP_100BTX_FD_CAPABLE 0x0008
188 #define KSZ8463_PnSR_LP_100BTX_HF_CAPABLE 0x0004
189 #define KSZ8463_PnSR_LP_10BT_FD_CAPABLE 0x0002
190 #define KSZ8463_PnSR_LP_10BT_HD_CAPABLE 0x0001
191 
192 //Switch Global Control 8 register
193 #define KSZ8463_SGCR8_QUEUE_PRIO_MAPPING 0xC000
194 #define KSZ8463_SGCR8_FLUSH_DYNAMIC_MAC_TABLE 0x0400
195 #define KSZ8463_SGCR8_FLUSH_STATIC_MAC_TABLE 0x0200
196 #define KSZ8463_SGCR8_TAIL_TAG_EN 0x0100
197 #define KSZ8463_SGCR8_PAUSE_OFF_LIMIT_TIME 0x00FF
198 
199 //Tail tag encoding
200 #define KSZ8463_TAIL_TAG_ENCODE(port) ((port) & 0x03)
201 //Tail tag decoding
202 #define KSZ8463_TAIL_TAG_DECODE(tag) (((tag) & 0x01) + 1)
203 
204 //C++ guard
205 #ifdef __cplusplus
206  extern "C" {
207 #endif
208 
209 //KSZ8463 Ethernet switch driver
210 extern const PhyDriver ksz8463PhyDriver;
211 
212 //KSZ8463 related functions
213 error_t ksz8463Init(NetInterface *interface);
214 
215 bool_t ksz8463GetLinkState(NetInterface *interface, uint8_t port);
216 
217 void ksz8463Tick(NetInterface *interface);
218 
219 void ksz8463EnableIrq(NetInterface *interface);
220 void ksz8463DisableIrq(NetInterface *interface);
221 
222 void ksz8463EventHandler(NetInterface *interface);
223 
224 error_t ksz8463TagFrame(NetInterface *interface, NetBuffer *buffer,
225  size_t *offset, uint8_t port, uint16_t *type);
226 
227 error_t ksz8463UntagFrame(NetInterface *interface, uint8_t **frame,
228  size_t *length, uint8_t *port);
229 
230 void ksz8463WritePhyReg(NetInterface *interface, uint8_t port,
231  uint8_t address, uint16_t data);
232 
233 uint16_t ksz8463ReadPhyReg(NetInterface *interface, uint8_t port,
234  uint8_t address);
235 
236 void ksz8463DumpPhyReg(NetInterface *interface, uint8_t port);
237 
238 void ksz8463WriteSwitchReg(NetInterface *interface, uint16_t address,
239  uint16_t data);
240 
241 uint16_t ksz8463ReadSwitchReg(NetInterface *interface, uint16_t address);
242 
243 void ksz8463DumpSwitchReg(NetInterface *interface);
244 
245 //C++ guard
246 #ifdef __cplusplus
247  }
248 #endif
249 
250 #endif
error_t ksz8463TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
void ksz8463EnableIrq(NetInterface *interface)
Enable interrupts.
void ksz8463DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
char_t type
uint16_t ksz8463ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
uint16_t ksz8463ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
error_t ksz8463UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
PHY driver.
Definition: nic.h:214
void ksz8463DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
void ksz8463WriteSwitchReg(NetInterface *interface, uint16_t address, uint16_t data)
Write switch register.
const PhyDriver ksz8463PhyDriver
KSZ8463 Ethernet switch driver.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void ksz8463Tick(NetInterface *interface)
KSZ8463 timer handler.
void ksz8463EventHandler(NetInterface *interface)
KSZ8463 event handler.
Ipv6Addr address
void ksz8463DisableIrq(NetInterface *interface)
Disable interrupts.
error_t
Error codes.
Definition: error.h:42
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint16_t port
Definition: dns_common.h:223
bool_t ksz8463GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz8463WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
uint8_t length
Definition: dtls_misc.h:142
error_t ksz8463Init(NetInterface *interface)
KSZ8463 Ethernet switch initialization.
int bool_t
Definition: compiler_port.h:49
Network interface controller abstraction layer.