ksz8463_driver.h
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1 /**
2  * @file ksz8463_driver.h
3  * @brief KSZ8463 Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 #ifndef _KSZ8463_DRIVER_H
32 #define _KSZ8463_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ8463 ports
38 #define KSZ8463_PORT1 1
39 #define KSZ8463_PORT2 2
40 
41 //SPI command byte
42 #define KSZ8463_SPI_CMD_READ 0x0000
43 #define KSZ8463_SPI_CMD_WRITE 0x8000
44 #define KSZ8463_SPI_CMD_ADDR 0x7FC0
45 #define KSZ8463_SPI_CMD_B3 0x0020
46 #define KSZ8463_SPI_CMD_B2 0x0010
47 #define KSZ8463_SPI_CMD_B1 0x0008
48 #define KSZ8463_SPI_CMD_B0 0x0004
49 
50 //KSZ8463 PHY registers
51 #define KSZ8463_PHY_REG_BMCR 0x00
52 #define KSZ8463_PHY_REG_BMSR 0x01
53 #define KSZ8463_PHY_REG_PHYIDR1 0x02
54 #define KSZ8463_PHY_REG_PHYIDR2 0x03
55 #define KSZ8463_PHY_REG_ANAR 0x04
56 #define KSZ8463_PHY_REG_ANLPAR 0x05
57 #define KSZ8463_PHY_REG_LINKMDCS 0x1D
58 #define KSZ8463_PHY_REG_PHYSCS 0x1F
59 
60 //BMCR register
61 #define BMCR_LOOPBACK (1 << 14)
62 #define BMCR_FORCE_100 (1 << 13)
63 #define BMCR_AN_EN (1 << 12)
64 #define BMCR_POWER_DOWN (1 << 11)
65 #define BMCR_ISOLATE (1 << 10)
66 #define BMCR_RESTART_AN (1 << 9)
67 #define BMCR_FORCE_FULL_DUPLEX (1 << 8)
68 #define BMCR_COL_TEST (1 << 7)
69 #define BMCR_HP_MDIX (1 << 5)
70 #define BMCR_FORCE_MDI (1 << 4)
71 #define BMCR_DIS_AUTO_MDIX (1 << 3)
72 #define BMCR_DIS_FAR_END_FAULT (1 << 2)
73 #define BMCR_DIS_TRANSMIT (1 << 1)
74 #define BMCR_DIS_LED (1 << 0)
75 
76 //BMSR register
77 #define BMSR_100BT4 (1 << 15)
78 #define BMSR_100BTX_FD (1 << 14)
79 #define BMSR_100BTX (1 << 13)
80 #define BMSR_10BT_FD (1 << 12)
81 #define BMSR_10BT (1 << 11)
82 #define BMSR_NO_PREAMBLE (1 << 6)
83 #define BMSR_AN_COMPLETE (1 << 5)
84 #define BMSR_FAR_END_FAULT (1 << 4)
85 #define BMSR_AN_ABLE (1 << 3)
86 #define BMSR_LINK_STATUS (1 << 2)
87 #define BMSR_JABBER_TEST (1 << 1)
88 #define BMSR_EXTENDED_CAP (1 << 0)
89 
90 //ANAR register
91 #define ANAR_NEXT_PAGE (1 << 15)
92 #define ANAR_REMOTE_FAULT (1 << 13)
93 #define ANAR_PAUSE (1 << 10)
94 #define ANAR_100BTX_FD (1 << 8)
95 #define ANAR_100BTX (1 << 7)
96 #define ANAR_10BT_FD (1 << 6)
97 #define ANAR_10BT (1 << 5)
98 #define ANAR_SELECTOR4 (1 << 4)
99 #define ANAR_SELECTOR3 (1 << 3)
100 #define ANAR_SELECTOR2 (1 << 2)
101 #define ANAR_SELECTOR1 (1 << 1)
102 #define ANAR_SELECTOR0 (1 << 0)
103 
104 //ANLPAR register
105 #define ANLPAR_NEXT_PAGE (1 << 15)
106 #define ANLPAR_LP_ACK (1 << 14)
107 #define ANLPAR_REMOTE_FAULT (1 << 13)
108 #define ANLPAR_PAUSE (1 << 10)
109 #define ANLPAR_100BTX_FD (1 << 8)
110 #define ANLPAR_100BTX (1 << 7)
111 #define ANLPAR_10BT_FD (1 << 6)
112 #define ANLPAR_10BT (1 << 5)
113 
114 //LINKMDCS register
115 #define LINKMDCS_CDT_EN (1 << 15)
116 #define LINKMDCS_CDT_RESULT1 (1 << 14)
117 #define LINKMDCS_CDT_RESULT0 (1 << 13)
118 #define LINKMDCS_CDT_10M_SHORT (1 << 12)
119 #define LINKMDCS_CDT_FAULT_COUNT8 (1 << 8)
120 #define LINKMDCS_CDT_FAULT_COUNT7 (1 << 7)
121 #define LINKMDCS_CDT_FAULT_COUNT6 (1 << 6)
122 #define LINKMDCS_CDT_FAULT_COUNT5 (1 << 5)
123 #define LINKMDCS_CDT_FAULT_COUNT4 (1 << 4)
124 #define LINKMDCS_CDT_FAULT_COUNT3 (1 << 3)
125 #define LINKMDCS_CDT_FAULT_COUNT2 (1 << 2)
126 #define LINKMDCS_CDT_FAULT_COUNT1 (1 << 1)
127 #define LINKMDCS_CDT_FAULT_COUNT0 (1 << 0)
128 
129 //PHYSCS register
130 #define PHYSCS_POL_REVERSE (1 << 5)
131 #define PHYSCS_MDIX_STATUS (1 << 4)
132 #define PHYSCS_FORCE_LINK (1 << 3)
133 #define PHYSCS_EEE_EN (1 << 2)
134 #define PHYSCS_REMOTE_LOOPBACK (1 << 1)
135 
136 //KSZ8463 switch registers
137 #define KSZ8463_SW_REG_PORT_CTRL2(n) (0x006E + (((n) - 1) * 0x18))
138 #define KSZ8463_SW_REG_PORT_STAT(n) (0x0080 + (((n) - 1) * 0x18))
139 #define KSZ8463_SW_REG_GLOBAL_CTRL8 0x00AC
140 
141 //Port control 2 register
142 #define PORT_CTRL2_INGRESS_VLAN_FILT (1 << 14)
143 #define PORT_CTRL2_DISCARD_NON_PVID_PACKETS (1 << 13)
144 #define PORT_CTRL2_FORCE_FLOW_CTRL (1 << 12)
145 #define PORT_CTRL2_BACK_PRESSURE_EN (1 << 11)
146 #define PORT_CTRL2_TRANSMIT_EN (1 << 10)
147 #define PORT_CTRL2_RECEIVE_EN (1 << 9)
148 #define PORT_CTRL2_LEARNING_DIS (1 << 8)
149 #define PORT_CTRL2_SNIFFER_PORT (1 << 7)
150 #define PORT_CTRL2_RECEIVE_SNIFF (1 << 6)
151 #define PORT_CTRL2_TRANSMIT_SNIFF (1 << 5)
152 #define PORT_CTRL2_USER_PRIO_CEILING (1 << 3)
153 #define PORT_CTRL2_PORT_VLAN_MEMBERSHIP2 (1 << 2)
154 #define PORT_CTRL2_PORT_VLAN_MEMBERSHIP1 (1 << 1)
155 #define PORT_CTRL2_PORT_VLAN_MEMBERSHIP0 (1 << 0)
156 
157 //Port status register
158 #define PORT_STAT_HP_MDIX (1 << 15)
159 #define PORT_STAT_POL_REVERSE (1 << 13)
160 #define PORT_STAT_TX_FLOW_CTRL_EN (1 << 12)
161 #define PORT_STAT_RX_FLOW_CTRL_EN (1 << 11)
162 #define PORT_STAT_OP_SPEED (1 << 10)
163 #define PORT_STAT_OP_MODE (1 << 9)
164 #define PORT_STAT_FAR_END_FAULT (1 << 8)
165 #define PORT_STAT_MDIX_STATUS (1 << 7)
166 #define PORT_STAT_AN_DONE (1 << 6)
167 #define PORT_STAT_LINK_STATUS (1 << 5)
168 #define PORT_STAT_LP_FLOW_CTRL_CAPABLE (1 << 4)
169 #define PORT_STAT_100BTX_FD_CAPABLE (1 << 3)
170 #define PORT_STAT_100BTX_HF_CAPABLE (1 << 2)
171 #define PORT_STAT_10BT_FD_CAPABLE (1 << 1)
172 #define PORT_STAT_10BT_HD_CAPABLE (1 << 0)
173 
174 //Global control 8 register
175 #define GLOBAL_CTRL8_QUEUE_PRIO_MAPPING1 (1 << 15)
176 #define GLOBAL_CTRL8_QUEUE_PRIO_MAPPING0 (1 << 14)
177 #define GLOBAL_CTRL8_FLUSH_DYNAMIC_MAC_TABLE (1 << 10)
178 #define GLOBAL_CTRL8_FLUSH_STATIC_MAC_TABLE (1 << 9)
179 #define GLOBAL_CTRL8_TAIL_TAG_EN (1 << 8)
180 #define GLOBAL_CTRL8_PAUSE_OFF_TIME7 (1 << 7)
181 #define GLOBAL_CTRL8_PAUSE_OFF_TIME6 (1 << 6)
182 #define GLOBAL_CTRL8_PAUSE_OFF_TIME5 (1 << 5)
183 #define GLOBAL_CTRL8_PAUSE_OFF_TIME4 (1 << 4)
184 #define GLOBAL_CTRL8_PAUSE_OFF_TIME3 (1 << 3)
185 #define GLOBAL_CTRL8_PAUSE_OFF_TIME2 (1 << 2)
186 #define GLOBAL_CTRL8_PAUSE_OFF_TIME1 (1 << 1)
187 #define GLOBAL_CTRL8_PAUSE_OFF_TIME0 (1 << 0)
188 
189 //Tail tag encoding
190 #define KSZ8463_TAIL_TAG_ENCODE(port) ((port) & 0x03)
191 //Tail tag decoding
192 #define KSZ8463_TAIL_TAG_DECODE(tag) (((tag) & 0x01) + 1)
193 
194 //C++ guard
195 #ifdef __cplusplus
196  extern "C" {
197 #endif
198 
199 //KSZ8463 Ethernet switch driver
200 extern const PhyDriver ksz8463PhyDriver;
201 
202 //KSZ8463 related functions
203 error_t ksz8463Init(NetInterface *interface);
204 
205 bool_t ksz8463GetLinkState(NetInterface *interface, uint8_t port);
206 
207 void ksz8463Tick(NetInterface *interface);
208 
209 void ksz8463EnableIrq(NetInterface *interface);
210 void ksz8463DisableIrq(NetInterface *interface);
211 
212 void ksz8463EventHandler(NetInterface *interface);
213 
214 error_t ksz8463TagFrame(NetInterface *interface, NetBuffer *buffer,
215  size_t *offset, uint8_t port, uint16_t *type);
216 
217 error_t ksz8463UntagFrame(NetInterface *interface, uint8_t **frame,
218  size_t *length, uint8_t *port);
219 
220 void ksz8463WritePhyReg(NetInterface *interface, uint8_t port,
221  uint8_t address, uint16_t data);
222 
223 uint16_t ksz8463ReadPhyReg(NetInterface *interface, uint8_t port,
224  uint8_t address);
225 
226 void ksz8463DumpPhyReg(NetInterface *interface, uint8_t port);
227 
228 void ksz8463WriteSwitchReg(NetInterface *interface, uint16_t address,
229  uint16_t data);
230 
231 uint16_t ksz8463ReadSwitchReg(NetInterface *interface, uint16_t address);
232 
233 void ksz8463DumpSwitchReg(NetInterface *interface);
234 
235 //C++ guard
236 #ifdef __cplusplus
237  }
238 #endif
239 
240 #endif
error_t ksz8463TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
void ksz8463EnableIrq(NetInterface *interface)
Enable interrupts.
void ksz8463DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
char_t type
uint16_t ksz8463ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
uint16_t ksz8463ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
error_t ksz8463UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
PHY driver.
Definition: nic.h:199
void ksz8463DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
void ksz8463WriteSwitchReg(NetInterface *interface, uint16_t address, uint16_t data)
Write switch register.
const PhyDriver ksz8463PhyDriver
KSZ8463 Ethernet switch driver.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void ksz8463Tick(NetInterface *interface)
KSZ8463 timer handler.
void ksz8463EventHandler(NetInterface *interface)
KSZ8463 event handler.
Ipv6Addr address
void ksz8463DisableIrq(NetInterface *interface)
Disable interrupts.
error_t
Error codes.
Definition: error.h:42
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint16_t port
Definition: dns_common.h:223
bool_t ksz8463GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz8463WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
uint8_t length
Definition: dtls_misc.h:142
error_t ksz8463Init(NetInterface *interface)
KSZ8463 Ethernet switch initialization.
int bool_t
Definition: compiler_port.h:49
Network interface controller abstraction layer.