ksz8794_driver.h
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1 /**
2  * @file ksz8794_driver.h
3  * @brief KSZ8794 4-port Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _KSZ8794_DRIVER_H
32 #define _KSZ8794_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ8794 ports
38 #define KSZ8794_PORT1 1
39 #define KSZ8794_PORT2 2
40 #define KSZ8794_PORT3 3
41 
42 //SPI command byte
43 #define KSZ8794_SPI_CMD_WRITE 0x4000
44 #define KSZ8794_SPI_CMD_READ 0x6000
45 #define KSZ8794_SPI_CMD_ADDR 0x1FFE
46 
47 //KSZ8794 PHY registers
48 #define KSZ8794_BMCR 0x00
49 #define KSZ8794_BMSR 0x01
50 #define KSZ8794_PHYID1 0x02
51 #define KSZ8794_PHYID2 0x03
52 #define KSZ8794_ANAR 0x04
53 #define KSZ8794_ANLPAR 0x05
54 #define KSZ8794_LINKMD 0x1D
55 #define KSZ8794_PHYSCS 0x1F
56 
57 //KSZ8794 Switch registers
58 #define KSZ8794_CHIP_ID0 0x00
59 #define KSZ8794_CHIP_ID1 0x01
60 #define KSZ8794_GLOBAL_CTRL0 0x02
61 #define KSZ8794_GLOBAL_CTRL1 0x03
62 #define KSZ8794_GLOBAL_CTRL2 0x04
63 #define KSZ8794_GLOBAL_CTRL3 0x05
64 #define KSZ8794_GLOBAL_CTRL4 0x06
65 #define KSZ8794_GLOBAL_CTRL5 0x07
66 #define KSZ8794_GLOBAL_CTRL6_MIB_CTRL 0x08
67 #define KSZ8794_GLOBAL_CTRL7 0x09
68 #define KSZ8794_GLOBAL_CTRL8 0x0A
69 #define KSZ8794_GLOBAL_CTRL9 0x0B
70 #define KSZ8794_GLOBAL_CTRL10 0x0C
71 #define KSZ8794_GLOBAL_CTRL11 0x0D
72 #define KSZ8794_PD_MGMT_CTRL1 0x0E
73 #define KSZ8794_PD_MGMT_CTRL2 0x0F
74 #define KSZ8794_PORT1_CTRL0 0x10
75 #define KSZ8794_PORT1_CTRL1 0x11
76 #define KSZ8794_PORT1_CTRL2 0x12
77 #define KSZ8794_PORT1_CTRL3 0x13
78 #define KSZ8794_PORT1_CTRL4 0x14
79 #define KSZ8794_PORT1_CTRL5 0x15
80 #define KSZ8794_PORT1_CTRL7 0x17
81 #define KSZ8794_PORT1_STAT0 0x18
82 #define KSZ8794_PORT1_STAT1 0x19
83 #define KSZ8794_PORT1_PHY_CTRL8 0x1A
84 #define KSZ8794_PORT1_LINKMD 0x1B
85 #define KSZ8794_PORT1_PHY_CTRL9 0x1C
86 #define KSZ8794_PORT1_PHY_CTRL10 0x1D
87 #define KSZ8794_PORT1_STAT2 0x1E
88 #define KSZ8794_PORT1_CTRL11_STAT3 0x1F
89 #define KSZ8794_PORT2_CTRL0 0x20
90 #define KSZ8794_PORT2_CTRL1 0x21
91 #define KSZ8794_PORT2_CTRL2 0x22
92 #define KSZ8794_PORT2_CTRL3 0x23
93 #define KSZ8794_PORT2_CTRL4 0x24
94 #define KSZ8794_PORT2_CTRL5 0x25
95 #define KSZ8794_PORT2_CTRL7 0x27
96 #define KSZ8794_PORT2_STAT0 0x28
97 #define KSZ8794_PORT2_STAT1 0x29
98 #define KSZ8794_PORT2_PHY_CTRL8 0x2A
99 #define KSZ8794_PORT2_LINKMD 0x2B
100 #define KSZ8794_PORT2_PHY_CTRL9 0x2C
101 #define KSZ8794_PORT2_PHY_CTRL10 0x2D
102 #define KSZ8794_PORT2_STAT2 0x2E
103 #define KSZ8794_PORT2_CTRL11_STAT3 0x2F
104 #define KSZ8794_PORT3_CTRL0 0x30
105 #define KSZ8794_PORT3_CTRL1 0x31
106 #define KSZ8794_PORT3_CTRL2 0x32
107 #define KSZ8794_PORT3_CTRL3 0x33
108 #define KSZ8794_PORT3_CTRL4 0x34
109 #define KSZ8794_PORT3_CTRL5 0x35
110 #define KSZ8794_PORT3_CTRL7 0x37
111 #define KSZ8794_PORT3_STAT0 0x38
112 #define KSZ8794_PORT3_STAT1 0x39
113 #define KSZ8794_PORT3_PHY_CTRL8 0x3A
114 #define KSZ8794_PORT3_LINKMD 0x3B
115 #define KSZ8794_PORT3_PHY_CTRL9 0x3C
116 #define KSZ8794_PORT3_PHY_CTRL10 0x3D
117 #define KSZ8794_PORT3_STAT2 0x3E
118 #define KSZ8794_PORT3_CTRL11_STAT3 0x3F
119 #define KSZ8794_PORT4_CTRL0 0x50
120 #define KSZ8794_PORT4_CTRL1 0x51
121 #define KSZ8794_PORT4_CTRL2 0x52
122 #define KSZ8794_PORT4_CTRL3 0x53
123 #define KSZ8794_PORT4_CTRL4 0x54
124 #define KSZ8794_PORT4_CTRL5 0x55
125 #define KSZ8794_PORT4_IF_CTRL6 0x56
126 #define KSZ8794_MAC_ADDR0 0x68
127 #define KSZ8794_MAC_ADDR1 0x69
128 #define KSZ8794_MAC_ADDR2 0x6A
129 #define KSZ8794_MAC_ADDR3 0x6B
130 #define KSZ8794_MAC_ADDR4 0x6C
131 #define KSZ8794_MAC_ADDR5 0x6D
132 #define KSZ8794_IND_ACCESS_CTRL0 0x6E
133 #define KSZ8794_IND_ACCESS_CTRL1 0x6F
134 #define KSZ8794_IND_DATA8 0x70
135 #define KSZ8794_IND_DATA7 0x71
136 #define KSZ8794_IND_DATA6 0x72
137 #define KSZ8794_IND_DATA5 0x73
138 #define KSZ8794_IND_DATA4 0x74
139 #define KSZ8794_IND_DATA3 0x75
140 #define KSZ8794_IND_DATA2 0x76
141 #define KSZ8794_IND_DATA1 0x77
142 #define KSZ8794_IND_DATA0 0x78
143 #define KSZ8794_INT_STAT 0x7C
144 #define KSZ8794_INT_MASK 0x7D
145 #define KSZ8794_ACL_INT_STAT 0x7E
146 #define KSZ8794_ACL_CTRL 0x7F
147 #define KSZ8794_GLOBAL_CTRL12 0x80
148 #define KSZ8794_GLOBAL_CTRL13 0x81
149 #define KSZ8794_GLOBAL_CTRL14 0x82
150 #define KSZ8794_GLOBAL_CTRL15 0x83
151 #define KSZ8794_GLOBAL_CTRL16 0x84
152 #define KSZ8794_GLOBAL_CTRL17 0x85
153 #define KSZ8794_GLOBAL_CTRL18 0x86
154 #define KSZ8794_GLOBAL_CTRL19 0x87
155 #define KSZ8794_TOS_PRIO_CTRL0 0x90
156 #define KSZ8794_TOS_PRIO_CTRL1 0x91
157 #define KSZ8794_TOS_PRIO_CTRL2 0x92
158 #define KSZ8794_TOS_PRIO_CTRL3 0x93
159 #define KSZ8794_TOS_PRIO_CTRL4 0x94
160 #define KSZ8794_TOS_PRIO_CTRL5 0x95
161 #define KSZ8794_TOS_PRIO_CTRL6 0x96
162 #define KSZ8794_TOS_PRIO_CTRL7 0x97
163 #define KSZ8794_TOS_PRIO_CTRL8 0x98
164 #define KSZ8794_TOS_PRIO_CTRL9 0x99
165 #define KSZ8794_TOS_PRIO_CTRL10 0x9A
166 #define KSZ8794_TOS_PRIO_CTRL11 0x9B
167 #define KSZ8794_TOS_PRIO_CTRL12 0x9C
168 #define KSZ8794_TOS_PRIO_CTRL13 0x9D
169 #define KSZ8794_TOS_PRIO_CTRL14 0x9E
170 #define KSZ8794_TOS_PRIO_CTRL15 0x9F
171 #define KSZ8794_IND_BYTE 0xA0
172 #define KSZ8794_GLOBAL_CTRL20 0xA3
173 #define KSZ8794_GLOBAL_CTRL21 0xA4
174 #define KSZ8794_PORT1_CTRL12 0xB0
175 #define KSZ8794_PORT1_CTRL13 0xB1
176 #define KSZ8794_PORT1_CTRL14 0xB2
177 #define KSZ8794_PORT1_CTRL15 0xB3
178 #define KSZ8794_PORT1_CTRL16 0xB4
179 #define KSZ8794_PORT1_CTRL17 0xB5
180 #define KSZ8794_PORT1_RATE_LIMIT_CTRL 0xB6
181 #define KSZ8794_PORT1_PRIO0_IG_LIMIT_CTRL1 0xB7
182 #define KSZ8794_PORT1_PRIO1_IG_LIMIT_CTRL2 0xB8
183 #define KSZ8794_PORT1_PRIO2_IG_LIMIT_CTRL3 0xB9
184 #define KSZ8794_PORT1_PRIO3_IG_LIMIT_CTRL4 0xBA
185 #define KSZ8794_PORT1_QUEUE0_EG_LIMIT_CTRL1 0xBB
186 #define KSZ8794_PORT1_QUEUE1_EG_LIMIT_CTRL2 0xBC
187 #define KSZ8794_PORT1_QUEUE2_EG_LIMIT_CTRL3 0xBD
188 #define KSZ8794_PORT1_QUEUE3_EG_LIMIT_CTRL4 0xBE
189 #define KSZ8794_TEST 0xBF
190 #define KSZ8794_PORT2_CTRL12 0xC0
191 #define KSZ8794_PORT2_CTRL13 0xC1
192 #define KSZ8794_PORT2_CTRL14 0xC2
193 #define KSZ8794_PORT2_CTRL15 0xC3
194 #define KSZ8794_PORT2_CTRL16 0xC4
195 #define KSZ8794_PORT2_CTRL17 0xC5
196 #define KSZ8794_PORT2_RATE_LIMIT_CTRL 0xC6
197 #define KSZ8794_PORT2_PRIO0_IG_LIMIT_CTRL1 0xC7
198 #define KSZ8794_PORT2_PRIO1_IG_LIMIT_CTRL2 0xC8
199 #define KSZ8794_PORT2_PRIO2_IG_LIMIT_CTRL3 0xC9
200 #define KSZ8794_PORT2_PRIO3_IG_LIMIT_CTRL4 0xCA
201 #define KSZ8794_PORT2_QUEUE0_EG_LIMIT_CTRL1 0xCB
202 #define KSZ8794_PORT2_QUEUE1_EG_LIMIT_CTRL2 0xCC
203 #define KSZ8794_PORT2_QUEUE2_EG_LIMIT_CTRL3 0xCD
204 #define KSZ8794_PORT2_QUEUE3_EG_LIMIT_CTRL4 0xCE
205 #define KSZ8794_PORT3_CTRL12 0xD0
206 #define KSZ8794_PORT3_CTRL13 0xD1
207 #define KSZ8794_PORT3_CTRL14 0xD2
208 #define KSZ8794_PORT3_CTRL15 0xD3
209 #define KSZ8794_PORT3_CTRL16 0xD4
210 #define KSZ8794_PORT3_CTRL17 0xD5
211 #define KSZ8794_PORT3_RATE_LIMIT_CTRL 0xD6
212 #define KSZ8794_PORT3_PRIO0_IG_LIMIT_CTRL1 0xD7
213 #define KSZ8794_PORT3_PRIO1_IG_LIMIT_CTRL2 0xD8
214 #define KSZ8794_PORT3_PRIO2_IG_LIMIT_CTRL3 0xD9
215 #define KSZ8794_PORT3_PRIO3_IG_LIMIT_CTRL4 0xDA
216 #define KSZ8794_PORT3_QUEUE0_EG_LIMIT_CTRL1 0xDB
217 #define KSZ8794_PORT3_QUEUE1_EG_LIMIT_CTRL2 0xDC
218 #define KSZ8794_PORT3_QUEUE2_EG_LIMIT_CTRL3 0xDD
219 #define KSZ8794_PORT3_QUEUE3_EG_LIMIT_CTRL4 0xDE
220 #define KSZ8794_TEST2 0xDF
221 #define KSZ8794_TEST3 0xEF
222 #define KSZ8794_PORT4_CTRL12 0xF0
223 #define KSZ8794_PORT4_CTRL13 0xF1
224 #define KSZ8794_PORT4_CTRL14 0xF2
225 #define KSZ8794_PORT4_CTRL15 0xF3
226 #define KSZ8794_PORT4_CTRL16 0xF4
227 #define KSZ8794_PORT4_CTRL17 0xF5
228 #define KSZ8794_PORT4_RATE_LIMIT_CTRL 0xF6
229 #define KSZ8794_PORT4_PRIO0_IG_LIMIT_CTRL1 0xF7
230 #define KSZ8794_PORT4_PRIO1_IG_LIMIT_CTRL2 0xF8
231 #define KSZ8794_PORT4_PRIO2_IG_LIMIT_CTRL3 0xF9
232 #define KSZ8794_PORT4_PRIO3_IG_LIMIT_CTRL4 0xFA
233 #define KSZ8794_PORT4_QUEUE0_EG_LIMIT_CTRL1 0xFB
234 #define KSZ8794_PORT4_QUEUE1_EG_LIMIT_CTRL2 0xFC
235 #define KSZ8794_PORT4_QUEUE2_EG_LIMIT_CTRL3 0xFD
236 #define KSZ8794_PORT4_QUEUE3_EG_LIMIT_CTRL4 0xFE
237 #define KSZ8794_TEST4 0xFF
238 
239 //KSZ8794 Switch register access macros
240 #define KSZ8794_PORTn_CTRL0(port) (0x00 + ((port) * 0x10))
241 #define KSZ8794_PORTn_CTRL1(port) (0x01 + ((port) * 0x10))
242 #define KSZ8794_PORTn_CTRL2(port) (0x02 + ((port) * 0x10))
243 #define KSZ8794_PORTn_CTRL3(port) (0x03 + ((port) * 0x10))
244 #define KSZ8794_PORTn_CTRL4(port) (0x04 + ((port) * 0x10))
245 #define KSZ8794_PORTn_CTRL5(port) (0x05 + ((port) * 0x10))
246 #define KSZ8794_PORTn_CTRL7(port) (0x07 + ((port) * 0x10))
247 #define KSZ8794_PORTn_STAT0(port) (0x08 + ((port) * 0x10))
248 #define KSZ8794_PORTn_STAT1(port) (0x09 + ((port) * 0x10))
249 #define KSZ8794_PORTn_PHY_CTRL8(port) (0x0A + ((port) * 0x10))
250 #define KSZ8794_PORTn_LINKMD(port) (0x0B + ((port) * 0x10))
251 #define KSZ8794_PORTn_PHY_CTRL9(port) (0x0C + ((port) * 0x10))
252 #define KSZ8794_PORTn_PHY_CTRL10(port) (0x0D + ((port) * 0x10))
253 #define KSZ8794_PORTn_STAT2(port) (0x0E + ((port) * 0x10))
254 #define KSZ8794_PORTn_CTRL11_STAT3(port) (0x0F + ((port) * 0x10))
255 #define KSZ8794_PORTn_CTRL12(port) (0xA0 + ((port) * 0x10))
256 #define KSZ8794_PORTn_CTRL13(port) (0xA1 + ((port) * 0x10))
257 #define KSZ8794_PORTn_CTRL14(port) (0xA2 + ((port) * 0x10))
258 #define KSZ8794_PORTn_CTRL15(port) (0xA3 + ((port) * 0x10))
259 #define KSZ8794_PORTn_CTRL16(port) (0xA4 + ((port) * 0x10))
260 #define KSZ8794_PORTn_CTRL17(port) (0xA5 + ((port) * 0x10))
261 #define KSZ8794_PORTn_RATE_LIMIT_CTRL(port) (0xA6 + ((port) * 0x10))
262 #define KSZ8794_PORTn_PRIO0_IG_LIMIT_CTRL1(port) (0xA7 + ((port) * 0x10))
263 #define KSZ8794_PORTn_PRIO1_IG_LIMIT_CTRL2(port) (0xA8 + ((port) * 0x10))
264 #define KSZ8794_PORTn_PRIO2_IG_LIMIT_CTRL3(port) (0xA9 + ((port) * 0x10))
265 #define KSZ8794_PORTn_PRIO3_IG_LIMIT_CTRL4(port) (0xAA + ((port) * 0x10))
266 #define KSZ8794_PORTn_QUEUE0_EG_LIMIT_CTRL1(port) (0xAB + ((port) * 0x10))
267 #define KSZ8794_PORTn_QUEUE1_EG_LIMIT_CTRL2(port) (0xAC + ((port) * 0x10))
268 #define KSZ8794_PORTn_QUEUE2_EG_LIMIT_CTRL3(port) (0xAD + ((port) * 0x10))
269 #define KSZ8794_PORTn_QUEUE3_EG_LIMIT_CTRL4(port) (0xAE + ((port) * 0x10))
270 
271 //Basic Control register
272 #define KSZ8794_BMCR_RESET 0x8000
273 #define KSZ8794_BMCR_LOOPBACK 0x4000
274 #define KSZ8794_BMCR_FORCE_100 0x2000
275 #define KSZ8794_BMCR_AN_EN 0x1000
276 #define KSZ8794_BMCR_POWER_DOWN 0x0800
277 #define KSZ8794_BMCR_ISOLATE 0x0400
278 #define KSZ8794_BMCR_RESTART_AN 0x0200
279 #define KSZ8794_BMCR_FORCE_FULL_DUPLEX 0x0100
280 #define KSZ8794_BMCR_HP_MDIX 0x0020
281 #define KSZ8794_BMCR_FORCE_MDI 0x0010
282 #define KSZ8794_BMCR_AUTO_MDIX_DIS 0x0008
283 #define KSZ8794_BMCR_FAR_END_FAULT_DIS 0x0004
284 #define KSZ8794_BMCR_TRANSMIT_DIS 0x0002
285 #define KSZ8794_BMCR_LED_DIS 0x0001
286 
287 //Basic Status register
288 #define KSZ8794_BMSR_100BT4 0x8000
289 #define KSZ8794_BMSR_100BTX_FD 0x4000
290 #define KSZ8794_BMSR_100BTX_HD 0x2000
291 #define KSZ8794_BMSR_10BT_FD 0x1000
292 #define KSZ8794_BMSR_10BT_HD 0x0800
293 #define KSZ8794_BMSR_AN_COMPLETE 0x0020
294 #define KSZ8794_BMSR_FAR_END_FAULT 0x0010
295 #define KSZ8794_BMSR_AN_CAPABLE 0x0008
296 #define KSZ8794_BMSR_LINK_STATUS 0x0004
297 #define KSZ8794_BMSR_EXTENDED_CAPABLE 0x0001
298 
299 //PHYID High register
300 #define KSZ8794_PHYID1_DEFAULT 0x0022
301 
302 //PHYID Low register
303 #define KSZ8794_PHYID2_DEFAULT 0x1550
304 
305 //Advertisement Ability register
306 #define KSZ8794_ANAR_PAUSE 0x0400
307 #define KSZ8794_ANAR_100BTX_FD 0x0100
308 #define KSZ8794_ANAR_100BTX_HD 0x0080
309 #define KSZ8794_ANAR_10BT_FD 0x0040
310 #define KSZ8794_ANAR_10BT_HD 0x0020
311 #define KSZ8794_ANAR_SELECTOR 0x001F
312 #define KSZ8794_ANAR_SELECTOR_DEFAULT 0x0001
313 
314 //Link Partner Ability register
315 #define KSZ8794_ANLPAR_PAUSE 0x0400
316 #define KSZ8794_ANLPAR_100BTX_FD 0x0100
317 #define KSZ8794_ANLPAR_100BTX_HD 0x0080
318 #define KSZ8794_ANLPAR_10BT_FD 0x0040
319 #define KSZ8794_ANLPAR_10BT_HD 0x0020
320 
321 //LinkMD Control/Status register
322 #define KSZ8794_LINKMD_TEST_EN 0x8000
323 #define KSZ8794_LINKMD_RESULT 0x6000
324 #define KSZ8794_LINKMD_SHORT 0x1000
325 #define KSZ8794_LINKMD_FAULT_COUNT 0x01FF
326 
327 //PHY Special Control/Status register
328 #define KSZ8794_PHYSCS_OP_MODE 0x0700
329 #define KSZ8794_PHYSCS_OP_MODE_AN 0x0100
330 #define KSZ8794_PHYSCS_OP_MODE_10BT_HD 0x0200
331 #define KSZ8794_PHYSCS_OP_MODE_100BTX_HD 0x0300
332 #define KSZ8794_PHYSCS_OP_MODE_10BT_FD 0x0500
333 #define KSZ8794_PHYSCS_OP_MODE_100BTX_FD 0x0600
334 #define KSZ8794_PHYSCS_OP_MODE_ISOLATE 0x0700
335 #define KSZ8794_PHYSCS_POLRVS 0x0020
336 #define KSZ8794_PHYSCS_MDIX_STATUS 0x0010
337 #define KSZ8794_PHYSCS_FORCE_LINK 0x0008
338 #define KSZ8794_PHYSCS_PWRSAVE 0x0004
339 #define KSZ8794_PHYSCS_REMOTE_LOOPBACK 0x0002
340 
341 //Chip ID0 register
342 #define KSZ8794_CHIP_ID0_FAMILY_ID 0xFF
343 #define KSZ8794_CHIP_ID0_FAMILY_ID_DEFAULT 0x87
344 
345 //Chip ID1 / Start Switch register
346 #define KSZ8794_CHIP_ID1_CHIP_ID 0xF0
347 #define KSZ8794_CHIP_ID1_CHIP_ID_DEFAULT 0x60
348 #define KSZ8794_CHIP_ID1_REVISION_ID 0x0E
349 #define KSZ8794_CHIP_ID1_START_SWITCH 0x01
350 
351 //Global Control 1 register
352 #define KSZ8794_GLOBAL_CTRL1_2KB_PKT_SUPPORT 0x40
353 #define KSZ8794_GLOBAL_CTRL1_TX_FLOW_CTRL_EN 0x20
354 #define KSZ8794_GLOBAL_CTRL1_RX_FLOW_CTRL_EN 0x10
355 #define KSZ8794_GLOBAL_CTRL1_FRAME_LEN_CHECK_EN 0x08
356 #define KSZ8794_GLOBAL_CTRL1_AGING_EN 0x04
357 #define KSZ8794_GLOBAL_CTRL1_FAST_AGE_EN 0x02
358 #define KSZ8794_GLOBAL_CTRL1_AGGRESSIVE_BACK_OFF_EN 0x01
359 
360 //Global Control 10 register
361 #define KSZ8794_GLOBAL_CTRL10_TAIL_TAG_EN 0x02
362 #define KSZ8794_GLOBAL_CTRL10_PASS_FLOW_CTRL_PKT 0x01
363 
364 //Port N Control 0 register
365 #define KSZ8794_PORTn_CTRL0_BCAST_STORM_PROTECT_EN 0x80
366 #define KSZ8794_PORTn_CTRL0_DIFFSERV_PRIO_CLASS_EN 0x40
367 #define KSZ8794_PORTn_CTRL0_802_1P_PRIO_CLASS_EN 0x20
368 #define KSZ8794_PORTn_CTRL0_PORT_PRIO_CLASS_EN 0x18
369 #define KSZ8794_PORTn_CTRL0_TAG_INSERTION 0x04
370 #define KSZ8794_PORTn_CTRL0_TAG_REMOVAL 0x02
371 #define KSZ8794_PORTn_CTRL0_TWO_QUEUE_SPLIT_EN 0x01
372 
373 //Port N Control 1 register
374 #define KSZ8794_PORTn_CTRL1_SNIFFER_PORT 0x80
375 #define KSZ8794_PORTn_CTRL1_RECEIVE_SNIFF 0x40
376 #define KSZ8794_PORTn_CTRL1_TRANSMIT_SNIFF 0x20
377 #define KSZ8794_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x1F
378 
379 //Port N Control 2 register
380 #define KSZ8794_PORTn_CTRL2_USER_PRIO_CEILING 0x80
381 #define KSZ8794_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
382 #define KSZ8794_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
383 #define KSZ8794_PORTn_CTRL2_FORCE_FLOW_CTRL 0x10
384 #define KSZ8794_PORTn_CTRL2_BACK_PRESSURE_EN 0x08
385 #define KSZ8794_PORTn_CTRL2_TRANSMIT_EN 0x04
386 #define KSZ8794_PORTn_CTRL2_RECEIVE_EN 0x02
387 #define KSZ8794_PORTn_CTRL2_LEARNING_DIS 0x01
388 
389 //Port N Control 3 register
390 #define KSZ8794_PORTn_CTRL3_DEFAULT_USER_PRIO 0xE0
391 #define KSZ8794_PORTn_CTRL3_DEFAULT_CFI 0x10
392 #define KSZ8794_PORTn_CTRL3_DEFAULT_VID_MSB 0x0F
393 
394 //Port N Control 4 register
395 #define KSZ8794_PORTn_CTRL4_DEFAULT_VID_LSB 0xFF
396 
397 //Port N Status 0 register
398 #define KSZ8794_PORTn_STAT0_LP_FLOW_CTRL_CAPABLE 0x30
399 #define KSZ8794_PORTn_STAT0_LP_100BTX_FD_CAPABLE 0x08
400 #define KSZ8794_PORTn_STAT0_LP_100BTX_HF_CAPABLE 0x04
401 #define KSZ8794_PORTn_STAT0_LP_10BT_FD_CAPABLE 0x02
402 #define KSZ8794_PORTn_STAT0_LP_10BT_HD_CAPABLE 0x01
403 
404 //Port N Status 1 register
405 #define KSZ8794_PORTn_STAT1_HP_MDIX 0x80
406 #define KSZ8794_PORTn_STAT1_FACTORY_TESTING 0x40
407 #define KSZ8794_PORTn_STAT1_POLRVS 0x20
408 #define KSZ8794_PORTn_STAT1_TX_FLOW_CTRL_EN 0x10
409 #define KSZ8794_PORTn_STAT1_RX_FLOW_CTRL_EN 0x08
410 #define KSZ8794_PORTn_STAT1_OP_SPEED 0x04
411 #define KSZ8794_PORTn_STAT1_OP_DUPLEX 0x02
412 
413 //Port N Status 2 register
414 #define KSZ8794_PORTn_STAT2_MDIX_STATUS 0x80
415 #define KSZ8794_PORTn_STAT2_AN_DONE 0x40
416 #define KSZ8794_PORTn_STAT2_LINK_GOOD 0x20
417 
418 //Port N Control 11 / Status 3 register
419 #define KSZ8794_PORTn_CTRL11_STAT3_PHY_LOOPBACK 0x80
420 #define KSZ8794_PORTn_CTRL11_STAT3_PHY_ISOLATE 0x20
421 #define KSZ8794_PORTn_CTRL11_STAT3_SOFT_RESET 0x10
422 #define KSZ8794_PORTn_CTRL11_STAT3_FORCE_LINK 0x08
423 #define KSZ8794_PORTn_CTRL11_STAT3_OP_MODE 0x07
424 #define KSZ8794_PORTn_CTRL11_STAT3_OP_MODE_AN 0x01
425 #define KSZ8794_PORTn_CTRL11_STAT3_OP_MODE_10BT_HD 0x02
426 #define KSZ8794_PORTn_CTRL11_STAT3_OP_MODE_100BTX_HD 0x03
427 #define KSZ8794_PORTn_CTRL11_STAT3_OP_MODE_10BT_FD 0x05
428 #define KSZ8794_PORTn_CTRL11_STAT3_OP_MODE_100BTX_FD 0x06
429 
430 //Tail tag encoding
431 #define KSZ8794_TAIL_TAG_ENCODE(port) (0x40 | (1 << (((port) - 1) & 0x03)))
432 //Tail tag decoding
433 #define KSZ8794_TAIL_TAG_DECODE(tag) (((tag) & 0x03) + 1)
434 
435 //C++ guard
436 #ifdef __cplusplus
437 extern "C" {
438 #endif
439 
440 //KSZ8794 Ethernet switch driver
441 extern const PhyDriver ksz8794PhyDriver;
442 
443 //KSZ8794 related functions
444 error_t ksz8794Init(NetInterface *interface);
445 
446 bool_t ksz8794GetLinkState(NetInterface *interface, uint8_t port);
447 
448 void ksz8794Tick(NetInterface *interface);
449 
450 void ksz8794EnableIrq(NetInterface *interface);
451 void ksz8794DisableIrq(NetInterface *interface);
452 
453 void ksz8794EventHandler(NetInterface *interface);
454 
455 error_t ksz8794TagFrame(NetInterface *interface, NetBuffer *buffer,
456  size_t *offset, uint8_t port, uint16_t *type);
457 
458 error_t ksz8794UntagFrame(NetInterface *interface, uint8_t **frame,
459  size_t *length, uint8_t *port);
460 
461 void ksz8794WritePhyReg(NetInterface *interface, uint8_t port,
462  uint8_t address, uint16_t data);
463 
464 uint16_t ksz8794ReadPhyReg(NetInterface *interface, uint8_t port,
465  uint8_t address);
466 
467 void ksz8794DumpPhyReg(NetInterface *interface, uint8_t port);
468 
469 void ksz8794WriteSwitchReg(NetInterface *interface, uint16_t address,
470  uint8_t data);
471 
472 uint8_t ksz8794ReadSwitchReg(NetInterface *interface, uint16_t address);
473 
474 void ksz8794DumpSwitchReg(NetInterface *interface);
475 
476 //C++ guard
477 #ifdef __cplusplus
478 }
479 #endif
480 
481 #endif
uint8_t length
Definition: dtls_misc.h:149
const PhyDriver ksz8794PhyDriver
KSZ8794 Ethernet switch driver.
int bool_t
Definition: compiler_port.h:49
uint8_t ksz8794ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
void ksz8794Tick(NetInterface *interface)
KSZ8794 timer handler.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
PHY driver.
Definition: nic.h:214
void ksz8794DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
error_t ksz8794UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
error_t ksz8794TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
uint16_t ksz8794ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
void ksz8794WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
char_t type
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
bool_t ksz8794GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz8794DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
uint16_t port
Definition: dns_common.h:223
void ksz8794EventHandler(NetInterface *interface)
KSZ8794 event handler.
Network interface controller abstraction layer.
Ipv6Addr address
void ksz8794EnableIrq(NetInterface *interface)
Enable interrupts.
void ksz8794DisableIrq(NetInterface *interface)
Disable interrupts.
uint8_t data[]
Definition: dtls_misc.h:176
error_t ksz8794Init(NetInterface *interface)
KSZ8794 Ethernet switch initialization.
void ksz8794WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.