ksz8794_driver.h
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1 /**
2  * @file ksz8794_driver.h
3  * @brief KSZ8794 Ethernet switch
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _KSZ8794_DRIVER_H
30 #define _KSZ8794_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //KSZ8794 ports
36 #define KSZ8794_PORT1 1
37 #define KSZ8794_PORT2 2
38 #define KSZ8794_PORT3 3
39 
40 //SPI commands
41 #define KSZ8794_SPI_CMD_WRITE 0x4000
42 #define KSZ8794_SPI_CMD_READ 0x6000
43 #define KSZ8794_SPI_ADDR_MASK 0x1FFE
44 
45 //KSZ8794 PHY registers
46 #define KSZ8794_PHY_REG_BMCR 0x00
47 #define KSZ8794_PHY_REG_BMSR 0x01
48 #define KSZ8794_PHY_REG_PHYIDR1 0x02
49 #define KSZ8794_PHY_REG_PHYIDR2 0x03
50 #define KSZ8794_PHY_REG_ANAR 0x04
51 #define KSZ8794_PHY_REG_ANLPAR 0x05
52 #define KSZ8794_PHY_REG_LINKMDCS 0x1D
53 #define KSZ8794_PHY_REG_PHYSCS 0x1F
54 
55 //BMCR register
56 #define BMCR_SOFT_RESET (1 << 15)
57 #define BMCR_LOOPBACK (1 << 14)
58 #define BMCR_FORCE_100 (1 << 13)
59 #define BMCR_AN_EN (1 << 12)
60 #define BMCR_POWER_DOWN (1 << 11)
61 #define BMCR_ISOLATE (1 << 10)
62 #define BMCR_RESTART_AN (1 << 9)
63 #define BMCR_FORCE_FULL_DUPLEX (1 << 8)
64 #define BMCR_COL_TEST (1 << 7)
65 #define BMCR_HP_MDIX (1 << 5)
66 #define BMCR_FORCE_MDI (1 << 4)
67 #define BMCR_DIS_AUTO_MDIX (1 << 3)
68 #define BMCR_DIS_FAR_END_FAULT (1 << 2)
69 #define BMCR_DIS_TRANSMIT (1 << 1)
70 #define BMCR_DIS_LED (1 << 0)
71 
72 //BMSR register
73 #define BMSR_100BT4 (1 << 15)
74 #define BMSR_100BTX_FD (1 << 14)
75 #define BMSR_100BTX (1 << 13)
76 #define BMSR_10BT_FD (1 << 12)
77 #define BMSR_10BT (1 << 11)
78 #define BMSR_NO_PREAMBLE (1 << 6)
79 #define BMSR_AN_COMPLETE (1 << 5)
80 #define BMSR_FAR_END_FAULT (1 << 4)
81 #define BMSR_AN_ABLE (1 << 3)
82 #define BMSR_LINK_STATUS (1 << 2)
83 #define BMSR_JABBER_TEST (1 << 1)
84 #define BMSR_EXTENDED_CAP (1 << 0)
85 
86 //ANAR register
87 #define ANAR_NEXT_PAGE (1 << 15)
88 #define ANAR_REMOTE_FAULT (1 << 13)
89 #define ANAR_PAUSE (1 << 10)
90 #define ANAR_100BTX_FD (1 << 8)
91 #define ANAR_100BTX (1 << 7)
92 #define ANAR_10BT_FD (1 << 6)
93 #define ANAR_10BT (1 << 5)
94 #define ANAR_SELECTOR4 (1 << 4)
95 #define ANAR_SELECTOR3 (1 << 3)
96 #define ANAR_SELECTOR2 (1 << 2)
97 #define ANAR_SELECTOR1 (1 << 1)
98 #define ANAR_SELECTOR0 (1 << 0)
99 
100 //ANLPAR register
101 #define ANLPAR_NEXT_PAGE (1 << 15)
102 #define ANLPAR_LP_ACK (1 << 14)
103 #define ANLPAR_REMOTE_FAULT (1 << 13)
104 #define ANLPAR_PAUSE (1 << 10)
105 #define ANLPAR_100BTX_FD (1 << 8)
106 #define ANLPAR_100BTX (1 << 7)
107 #define ANLPAR_10BT_FD (1 << 6)
108 #define ANLPAR_10BT (1 << 5)
109 
110 //LINKMDCS register
111 #define LINKMDCS_VCT_EN (1 << 15)
112 #define LINKMDCS_VCT_RESULT1 (1 << 14)
113 #define LINKMDCS_VCT_RESULT0 (1 << 13)
114 #define LINKMDCS_VCT_10M_SHORT (1 << 12)
115 #define LINKMDCS_VCT_FAULT_COUNT8 (1 << 8)
116 #define LINKMDCS_VCT_FAULT_COUNT7 (1 << 7)
117 #define LINKMDCS_VCT_FAULT_COUNT6 (1 << 6)
118 #define LINKMDCS_VCT_FAULT_COUNT5 (1 << 5)
119 #define LINKMDCS_VCT_FAULT_COUNT4 (1 << 4)
120 #define LINKMDCS_VCT_FAULT_COUNT3 (1 << 3)
121 #define LINKMDCS_VCT_FAULT_COUNT2 (1 << 2)
122 #define LINKMDCS_VCT_FAULT_COUNT1 (1 << 1)
123 #define LINKMDCS_VCT_FAULT_COUNT0 (1 << 0)
124 
125 //PHYSCS register
126 #define PHYSCS_OP_MODE2 (1 << 10)
127 #define PHYSCS_OP_MODE1 (1 << 9)
128 #define PHYSCS_OP_MODE0 (1 << 8)
129 #define PHYSCS_POLRVS (1 << 5)
130 #define PHYSCS_MDIX_STATUS (1 << 4)
131 #define PHYSCS_FORCE_LINK (1 << 3)
132 #define PHYSCS_PWRSAVE (1 << 2)
133 #define PHYSCS_REMOTE_LOOPBACK (1 << 1)
134 
135 //Operation mode indication
136 #define PHYSCS_OP_MODE_MASK (7 << 8)
137 #define PHYSCS_OP_MODE_AN (0 << 8)
138 #define PHYSCS_OP_MODE_10BT (1 << 8)
139 #define PHYSCS_OP_MODE_100BTX (2 << 8)
140 #define PHYSCS_OP_MODE_10BT_FD (5 << 8)
141 #define PHYSCS_OP_MODE_100BTX_FD (6 << 8)
142 
143 //KSZ8794 switch registers
144 #define KSZ8794_SW_REG_GLOBAL_CTRL10 12
145 #define KSZ8794_SW_REG_PORT_CTRL0(n) (16 + (((n) - 1) * 16))
146 #define KSZ8794_SW_REG_PORT_CTRL1(n) (17 + (((n) - 1) * 16))
147 #define KSZ8794_SW_REG_PORT_CTRL2(n) (18 + (((n) - 1) * 16))
148 #define KSZ8794_SW_REG_PORT_STAT2(n) (30 + (((n) - 1) * 16))
149 #define KSZ8794_SW_REG_PORT_STAT3(n) (31 + (((n) - 1) * 16))
150 
151 //Global control 10 register
152 #define GLOBAL_CTRL10_TAIL_TAG_EN (1 << 1)
153 #define GLOBAL_CTRL10_PASS_FLOW_CTRL_PACKET (1 << 0)
154 
155 //Port control 2 register
156 #define PORT_CTRL2_USER_PRIO_CEILING (1 << 7)
157 #define PORT_CTRL2_INGRESS_VLAN_FILT (1 << 6)
158 #define PORT_CTRL2_DISCARD_NON_PVID_PACKET (1 << 5)
159 #define PORT_CTRL2_FORCE_FLOW_CTRL (1 << 4)
160 #define PORT_CTRL2_BACK_PRESSURE_EN (1 << 3)
161 #define PORT_CTRL2_TRANSMIT_EN (1 << 2)
162 #define PORT_CTRL2_RECEIVE_EN (1 << 1)
163 #define PORT_CTRL2_LEARNING_DIS (1 << 0)
164 
165 //Port status 2 register
166 #define PORT_STAT2_LINK_MDIX_STATUS (1 << 7)
167 #define PORT_STAT2_AUTO_NEGOTIATION_DONE (1 << 6)
168 #define PORT_STAT2_LINK_GOOD (1 << 5)
169 
170 //Port status 3 register
171 #define PORT_STAT3_PHY_LOOPBACK (1 << 7)
172 #define PORT_STAT3_PHY_PHY_ISOLATE (1 << 5)
173 #define PORT_STAT3_PHY_SOFT_RESET (1 << 4)
174 #define PORT_STAT3_PHY_FORCE_LINK (1 << 3)
175 #define PORT_STAT3_PHY_OP_MODE2 (1 << 2)
176 #define PORT_STAT3_PHY_OP_MODE1 (1 << 1)
177 #define PORT_STAT3_PHY_OP_MODE0 (1 << 0)
178 
179 //Operation mode indication
180 #define PORT_STAT3_PHY_OP_MODE_MASK (7 << 0)
181 #define PORT_STAT3_PHY_OP_MODE_AN (1 << 0)
182 #define PORT_STAT3_PHY_OP_MODE_10BT (2 << 0)
183 #define PORT_STAT3_PHY_OP_MODE_100BTX (3 << 0)
184 #define PORT_STAT3_PHY_OP_MODE_10BT_FD (5 << 0)
185 #define PORT_STAT3_PHY_OP_MODE_100BTX_FD (6 << 0)
186 
187 //Tail tag encoding
188 #define KSZ8794_TAIL_TAG_ENCODE(port) (0x40 | (1 << (((port) - 1) & 0x03)))
189 //Tail tag decoding
190 #define KSZ8794_TAIL_TAG_DECODE(tag) (((tag) & 0x03) + 1)
191 
192 //C++ guard
193 #ifdef __cplusplus
194  extern "C" {
195 #endif
196 
197 //KSZ8794 Ethernet switch driver
198 extern const PhyDriver ksz8794PhyDriver;
199 
200 //KSZ8794 related functions
201 error_t ksz8794Init(NetInterface *interface);
202 
203 bool_t ksz8794GetLinkState(NetInterface *interface, uint8_t port);
204 
205 void ksz8794Tick(NetInterface *interface);
206 
207 void ksz8794EnableIrq(NetInterface *interface);
208 void ksz8794DisableIrq(NetInterface *interface);
209 
210 void ksz8794EventHandler(NetInterface *interface);
211 
212 error_t ksz8794TagFrame(NetInterface **interface, NetBuffer *buffer,
213  size_t *offset, uint16_t *type);
214 
215 error_t ksz8794UntagFrame(NetInterface **interface, uint8_t **frame,
216  size_t *length);
217 
218 void ksz8794WritePhyReg(NetInterface *interface,
219  uint8_t port, uint8_t address, uint16_t data);
220 
221 uint16_t ksz8794ReadPhyReg(NetInterface *interface,
222  uint8_t port, uint8_t address);
223 
224 void ksz8794DumpPhyReg(NetInterface *interface, uint8_t port);
225 
226 void ksz8794WriteSwitchReg(NetInterface *interface,
227  uint16_t address, uint8_t data);
228 
229 uint8_t ksz8794ReadSwitchReg(NetInterface *interface,
230  uint16_t address);
231 
232 void ksz8794DumpSwitchReg(NetInterface *interface);
233 
234 //C++ guard
235 #ifdef __cplusplus
236  }
237 #endif
238 
239 #endif
void ksz8794WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
void ksz8794Tick(NetInterface *interface)
KSZ8794 timer handler.
error_t ksz8794TagFrame(NetInterface **interface, NetBuffer *buffer, size_t *offset, uint16_t *type)
Add tail tag to Ethernet frame.
void ksz8794DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
char_t type
void ksz8794DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
error_t ksz8794UntagFrame(NetInterface **interface, uint8_t **frame, size_t *length)
Decode tail tag from incoming Ethernet frame.
void ksz8794WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
uint8_t ksz8794ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
PHY driver.
Definition: nic.h:196
void ksz8794DisableIrq(NetInterface *interface)
Disable interrupts.
bool_t ksz8794GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
const PhyDriver ksz8794PhyDriver
KSZ8794 Ethernet switch driver.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void ksz8794EventHandler(NetInterface *interface)
KSZ8794 event handler.
uint16_t port
Definition: dns_common.h:221
uint16_t ksz8794ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
void ksz8794EnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t length
Definition: dtls_misc.h:140
error_t ksz8794Init(NetInterface *interface)
KSZ8794 Ethernet switch initialization.
int bool_t
Definition: compiler_port.h:47
Network interface controller abstraction layer.