ksz8851_driver.h
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1 /**
2  * @file ksz8851_driver.h
3  * @brief KSZ8851 Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 #ifndef _KSZ8851_DRIVER_H
32 #define _KSZ8851_DRIVER_H
33 
34 //SPI interface support
35 #ifndef KSZ8851_SPI_SUPPORT
36  #define KSZ8851_SPI_SUPPORT ENABLED
37 #elif (KSZ8851_SPI_SUPPORT != ENABLED && KSZ8851_SPI_SUPPORT != DISABLED)
38  #error KSZ8851_SPI_SUPPORT parameter is not valid
39 #endif
40 
41 //KSZ8851 data register
42 #ifndef KSZ8851_DATA_REG
43  #define KSZ8851_DATA_REG *((volatile uint16_t *) 0x60000000)
44 #endif
45 
46 //KSZ8851 command register
47 #ifndef KSZ8851_CMD_REG
48  #define KSZ8851_CMD_REG *((volatile uint16_t *) 0x60000004)
49 #endif
50 
51 //Device ID
52 #define KSZ8851_REV_A2_ID 0x8870
53 #define KSZ8851_REV_A3_ID 0x8872
54 
55 //SPI command set
56 #define KSZ8851_CMD_RD_REG 0x00
57 #define KSZ8851_CMD_WR_REG 0x40
58 #define KSZ8851_CMD_RD_FIFO 0x80
59 #define KSZ8851_CMD_WR_FIFO 0xC0
60 
61 //Byte enable bits
62 #if (KSZ8851_SPI_SUPPORT == ENABLED)
63  #define KSZ8851_CMD_B0 0x04
64  #define KSZ8851_CMD_B1 0x08
65  #define KSZ8851_CMD_B2 0x10
66  #define KSZ8851_CMD_B3 0x20
67 #else
68  #define KSZ8851_CMD_B0 0x1000
69  #define KSZ8851_CMD_B1 0x2000
70  #define KSZ8851_CMD_B2 0x4000
71  #define KSZ8851_CMD_B3 0x8000
72 #endif
73 
74 //KSZ8851 registers
75 #define KSZ8851_REG_CCR 0x08
76 #define KSZ8851_REG_MARL 0x10
77 #define KSZ8851_REG_MARM 0x12
78 #define KSZ8851_REG_MARH 0x14
79 #define KSZ8851_REG_OBCR 0x20
80 #define KSZ8851_REG_EEPCR 0x22
81 #define KSZ8851_REG_MBIR 0x24
82 #define KSZ8851_REG_GRR 0x26
83 #define KSZ8851_REG_WFCR 0x2A
84 #define KSZ8851_REG_WF0CRC0 0x30
85 #define KSZ8851_REG_WF0CRC1 0x32
86 #define KSZ8851_REG_WF0BM0 0x34
87 #define KSZ8851_REG_WF0BM1 0x36
88 #define KSZ8851_REG_WF0BM2 0x38
89 #define KSZ8851_REG_WF0BM3 0x3A
90 #define KSZ8851_REG_WF1CRC0 0x40
91 #define KSZ8851_REG_WF1CRC1 0x42
92 #define KSZ8851_REG_WF1BM0 0x44
93 #define KSZ8851_REG_WF1BM1 0x46
94 #define KSZ8851_REG_WF1BM2 0x48
95 #define KSZ8851_REG_WF1BM3 0x4A
96 #define KSZ8851_REG_WF2CRC0 0x50
97 #define KSZ8851_REG_WF2CRC1 0x52
98 #define KSZ8851_REG_WF2BM0 0x54
99 #define KSZ8851_REG_WF2BM1 0x56
100 #define KSZ8851_REG_WF2BM2 0x58
101 #define KSZ8851_REG_WF2BM3 0x5A
102 #define KSZ8851_REG_WF3CRC0 0x60
103 #define KSZ8851_REG_WF3CRC1 0x62
104 #define KSZ8851_REG_WF3BM0 0x64
105 #define KSZ8851_REG_WF3BM1 0x66
106 #define KSZ8851_REG_WF3BM2 0x68
107 #define KSZ8851_REG_WF3BM3 0x6A
108 #define KSZ8851_REG_TXCR 0x70
109 #define KSZ8851_REG_TXSR 0x72
110 #define KSZ8851_REG_RXCR1 0x74
111 #define KSZ8851_REG_RXCR2 0x76
112 #define KSZ8851_REG_TXMIR 0x78
113 #define KSZ8851_REG_RXFHSR 0x7C
114 #define KSZ8851_REG_RXFHBCR 0x7E
115 #define KSZ8851_REG_TXQCR 0x80
116 #define KSZ8851_REG_RXQCR 0x82
117 #define KSZ8851_REG_TXFDPR 0x84
118 #define KSZ8851_REG_RXFDPR 0x86
119 #define KSZ8851_REG_RXDTTR 0x8C
120 #define KSZ8851_REG_RXDBCTR 0x8E
121 #define KSZ8851_REG_IER 0x90
122 #define KSZ8851_REG_ISR 0x92
123 #define KSZ8851_REG_RXFCTR 0x9C
124 #define KSZ8851_REG_TXNTFSR 0x9E
125 #define KSZ8851_REG_MAHTR0 0xA0
126 #define KSZ8851_REG_MAHTR1 0xA2
127 #define KSZ8851_REG_MAHTR2 0xA4
128 #define KSZ8851_REG_MAHTR3 0xA6
129 #define KSZ8851_REG_FCLWR 0xB0
130 #define KSZ8851_REG_FCHWR 0xB2
131 #define KSZ8851_REG_FCOWR 0xB4
132 #define KSZ8851_REG_CIDER 0xC0
133 #define KSZ8851_REG_CGCR 0xC6
134 #define KSZ8851_REG_IACR 0xC8
135 #define KSZ8851_REG_IADLR 0xD0
136 #define KSZ8851_REG_IADHR 0xD2
137 #define KSZ8851_REG_PMECR 0xD4
138 #define KSZ8851_REG_GSWUTR 0xD6
139 #define KSZ8851_REG_PHYRR 0xD8
140 #define KSZ8851_REG_P1MBCR 0xE4
141 #define KSZ8851_REG_P1MBSR 0xE6
142 #define KSZ8851_REG_PHY1ILR 0xE8
143 #define KSZ8851_REG_PHY1IHR 0xEA
144 #define KSZ8851_REG_P1ANAR 0xEC
145 #define KSZ8851_REG_P1ANLPR 0xEE
146 #define KSZ8851_REG_P1SCLMD 0xF4
147 #define KSZ8851_REG_P1CR 0xF6
148 #define KSZ8851_REG_P1SR 0xF8
149 
150 //CCR register
151 #define CCR_BUS_ENDIAN_MODE 0x0400
152 #define CCR_EEPROM_PRESENCE 0x0200
153 #define CCR_SPI_MODE 0x0100
154 #define CCR_8_BIT_DATA_BUS 0x0080
155 #define CCR_16_BIT_DATA_BUS 0x0040
156 #define CCR_32_BIT_DATA_BUS 0x0020
157 #define CCR_BUS_SHARED_MODE 0x0010
158 #define CCR_128_PIN_PACKAGE 0x0008
159 #define CCR_48_PIN_PACKAGE 0x0002
160 #define CCR_32_PIN_PACKAGE 0x0001
161 
162 //OBCR register
163 #define OBCR_OUT_DRIVE_STRENGTH 0x0040
164 #define OBCR_SPI_SO_DELAY2 0x0020
165 #define OBCR_SPI_SO_DELAY1 0x0010
166 #define OBCR_SPI_SO_DELAY0 0x0008
167 #define OBCR_BUS_CLOCK_SEL 0x0004
168 #define OBCR_BUS_CLOCK_DIV1 0x0002
169 #define OBCR_BUS_CLOCK_DIV0 0x0001
170 
171 //EEPCR register
172 #define EEPCR_EESA 0x0010
173 #define EEPCR_EESB 0x0008
174 #define EEPCR_EECB2 0x0004
175 #define EEPCR_EECB1 0x0002
176 #define EEPCR_EECB0 0x0001
177 
178 //MBIR register
179 #define MBIR_TXMBF 0x1000
180 #define MBIR_TXMBFA 0x0800
181 #define MBIR_TXMBFC2 0x0400
182 #define MBIR_TXMBFC1 0x0200
183 #define MBIR_TXMBFC0 0x0100
184 #define MBIR_RXMBF 0x0010
185 #define MBIR_RXMBFA 0x0008
186 #define MBIR_RXMBFC2 0x0004
187 #define MBIR_RXMBFC1 0x0002
188 #define MBIR_RXMBFC0 0x0001
189 
190 //GRR register
191 #define GRR_QMU_MODULE_SOFT_RST 0x0002
192 #define GRR_GLOBAL_SOFT_RST 0x0001
193 
194 //WFCR register
195 #define WFCR_MPRXE 0x0080
196 #define WFCR_WF3E 0x0008
197 #define WFCR_WF2E 0x0004
198 #define WFCR_WF1E 0x0002
199 #define WFCR_WF0E 0x0001
200 
201 //TXCR register
202 #define TXCR_TCGICMP 0x0100
203 #define TXCR_TCGUDP 0x0080
204 #define TXCR_TCGTCP 0x0040
205 #define TXCR_TCGIP 0x0020
206 #define TXCR_FTXQ 0x0010
207 #define TXCR_TXFCE 0x0008
208 #define TXCR_TXPE 0x0004
209 #define TXCR_TXCE 0x0002
210 #define TXCR_TXE 0x0001
211 
212 //TXSR register
213 #define TXSR_TXLC 0x2000
214 #define TXSR_TXMC 0x1000
215 #define TXSR_TXFID5 0x0020
216 #define TXSR_TXFID4 0x0010
217 #define TXSR_TXFID3 0x0008
218 #define TXSR_TXFID2 0x0004
219 #define TXSR_TXFID1 0x0002
220 #define TXSR_TXFID0 0x0001
221 
222 //RXCR1 register
223 #define RXCR1_FRXQ 0x8000
224 #define RXCR1_RXUDPFCC 0x4000
225 #define RXCR1_RXTCPFCC 0x2000
226 #define RXCR1_RXIPFCC 0x1000
227 #define RXCR1_RXPAFMA 0x0800
228 #define RXCR1_RXFCE 0x0400
229 #define RXCR1_RXEFE 0x0200
230 #define RXCR1_RXMAFMA 0x0100
231 #define RXCR1_RXBE 0x0080
232 #define RXCR1_RXME 0x0040
233 #define RXCR1_RXUE 0x0020
234 #define RXCR1_RXAE 0x0010
235 #define RXCR1_RXINVF 0x0002
236 #define RXCR1_RXE 0x0001
237 
238 //RXCR2 register
239 #define RXCR2_SRDBL2 0x0080
240 #define RXCR2_SRDBL1 0x0040
241 #define RXCR2_SRDBL0 0x0020
242 #define RXCR2_IUFFP 0x0010
243 #define RXCR2_RXIUFCEZ 0x0008
244 #define RXCR2_UDPLFE 0x0004
245 #define RXCR2_RXICMPFCC 0x0002
246 #define RXCR2_RXSAF 0x0001
247 
248 //TXMIR register
249 #define TXMIR_TXMA_MASK 0x1FFF
250 
251 //RXFHSR register
252 #define RXFHSR_RXFV 0x8000
253 #define RXFHSR_RXICMPFCS 0x2000
254 #define RXFHSR_RXIPFCS 0x1000
255 #define RXFHSR_RXTCPFCS 0x0800
256 #define RXFHSR_RXUDPFCS 0x0400
257 #define RXFHSR_RXBF 0x0080
258 #define RXFHSR_RXMF 0x0040
259 #define RXFHSR_RXUF 0x0020
260 #define RXFHSR_RXMR 0x0010
261 #define RXFHSR_RXFT 0x0008
262 #define RXFHSR_RXFTL 0x0004
263 #define RXFHSR_RXRF 0x0002
264 #define RXFHSR_RXCE 0x0001
265 
266 //RXFHBCR register
267 #define RXFHBCR_RXBC_MASK 0x0FFF
268 
269 //TXQCR register
270 #define TXQCR_AETFE 0x0004
271 #define TXQCR_TXQMAM 0x0002
272 #define TXQCR_METFE 0x0001
273 
274 //RXQCR register
275 #define RXQCR_RXDTTS 0x1000
276 #define RXQCR_RXDBCTS 0x0800
277 #define RXQCR_RXFCTS 0x0400
278 #define RXQCR_RXIPHTOE 0x0200
279 #define RXQCR_RXDTTE 0x0080
280 #define RXQCR_RXDBCTE 0x0040
281 #define RXQCR_RXFCTE 0x0020
282 #define RXQCR_ADRFE 0x0010
283 #define RXQCR_SDA 0x0008
284 #define RXQCR_RRXEF 0x0001
285 
286 //TXFDPR register
287 #define TXFDPR_TXFPAI 0x4000
288 
289 //RXFDPR register
290 #define RXFDPR_RXFPAI 0x4000
291 
292 //IER register
293 #define IER_LCIE 0x8000
294 #define IER_TXIE 0x4000
295 #define IER_RXIE 0x2000
296 #define IER_RXOIE 0x0800
297 #define IER_TXPSIE 0x0200
298 #define IER_RXPSIE 0x0100
299 #define IER_TXSAIE 0x0040
300 #define IER_RXWFDIE 0x0020
301 #define IER_RXMPDIE 0x0010
302 #define IER_LDIE 0x0008
303 #define IER_EDIE 0x0004
304 #define IER_SPIBEIE 0x0002
305 #define IER_DEDIE 0x0001
306 
307 //ISR register
308 #define ISR_LCIS 0x8000
309 #define ISR_TXIS 0x4000
310 #define ISR_RXIS 0x2000
311 #define ISR_RXOIS 0x0800
312 #define ISR_TXPSIS 0x0200
313 #define ISR_RXPSIS 0x0100
314 #define ISR_TXSAIS 0x0040
315 #define ISR_RXWFDIS 0x0020
316 #define ISR_RXMPDIS 0x0010
317 #define ISR_LDIS 0x0008
318 #define ISR_EDIS 0x0004
319 #define ISR_SPIBEIS 0x0002
320 
321 //CGCR register
322 #define CGCR_LEDSEL0 0x0200
323 
324 //IACR register
325 #define IACR_READ_ENABLE 0x1000
326 #define IACR_TABLE_SELECT1 0x0800
327 #define IACR_TABLE_SELECT0 0x0400
328 
329 //PMECR register
330 #define PMECR_PME_DELAY_EN 0x4000
331 #define PMECR_PME_POLARITY 0x1000
332 #define PMECR_PME_WUP_FRAME_EN 0x0800
333 #define PMECR_PME_MAGIC_EN 0x0400
334 #define PMECR_PME_LINK_UP_EN 0x0200
335 #define PMECR_PME_ENERGY_EN 0x0100
336 #define PMECR_AUTO_WUP_EN 0x0080
337 #define PMECR_WUP_NORMAL_OP_MODE 0x0040
338 #define PMECR_WUP_FROM_WUP_FRAME 0x0020
339 #define PMECR_WUP_FROM_MAGIC 0x0010
340 #define PMECR_WUP_FROM_LINK_UP 0x0008
341 #define PMECR_WUP_FROM_ENERGY 0x0004
342 #define PMECR_PWR_MODE1 0x0002
343 #define PMECR_PWR_MODE0 0x0001
344 
345 //PHYRR register
346 #define PHYRR_PHY_RESET 0x0001
347 
348 //P1MBCR register
349 #define P1MBCR_LOCAL_LOOPBACK 0x4000
350 #define P1MBCR_FORCE_100 0x2000
351 #define P1MBCR_AN_ENABLE 0x1000
352 #define P1MBCR_RESTART_AN 0x0200
353 #define P1MBCR_FORCE_FULL_DUPLEX 0x0100
354 #define P1MBCR_HP_MDIX 0x0020
355 #define P1MBCR_FORCE_MDIX 0x0010
356 #define P1MBCR_DISABLE_MDIX 0x0008
357 #define P1MBCR_DISABLE_TRANSMIT 0x0002
358 #define P1MBCR_DISABLE_LED 0x0001
359 
360 //P1MBSR register
361 #define P1MBSR_T4_CAPABLE 0x8000
362 #define P1MBSR_100_FD_CAPABLE 0x4000
363 #define P1MBSR_100_CAPABLE 0x2000
364 #define P1MBSR_10_FD_CAPABLE 0x1000
365 #define P1MBSR_10_CAPABLE 0x0800
366 #define P1MBSR_PREAMBLE_SUPPR 0x0040
367 #define P1MBSR_AN_COMPLETE 0x0020
368 #define P1MBSR_AN_CAPABLE 0x0008
369 #define P1MBSR_LINK_STATUS 0x0004
370 #define P1MBSR_JABBER_TEST 0x0002
371 #define P1MBSR_EXTENDED_CAPABLE 0x0001
372 
373 //P1ANAR register
374 #define P1ANAR_NEXT_PAGE 0x8000
375 #define P1ANAR_REMOTE_FAULT 0x2000
376 #define P1ANAR_ADV_PAUSE 0x0400
377 #define P1ANAR_ADV_100_FD 0x0100
378 #define P1ANAR_ADV_100 0x0080
379 #define P1ANAR_ADV_10_FD 0x0040
380 #define P1ANAR_ADV_10 0x0020
381 #define P1ANAR_SELECTOR_FIELD4 0x0010
382 #define P1ANAR_SELECTOR_FIELD3 0x0008
383 #define P1ANAR_SELECTOR_FIELD2 0x0004
384 #define P1ANAR_SELECTOR_FIELD1 0x0002
385 #define P1ANAR_SELECTOR_FIELD0 0x0001
386 
387 //P1ANLPR register
388 #define P1ANLPR_NEXT_PAGE 0x8000
389 #define P1ANLPR_LP_ACK 0x4000
390 #define P1ANLPR_REMOTE_FAULT 0x2000
391 #define P1ANLPR_ADV_PAUSE 0x0400
392 #define P1ANLPR_ADV_100_FD 0x0100
393 #define P1ANLPR_ADV_100 0x0080
394 #define P1ANLPR_ADV_10_FD 0x0040
395 #define P1ANLPR_ADV_10 0x0020
396 
397 //P1SCLMD register
398 #define P1SCLMD_VCT_RESULT1 0x4000
399 #define P1SCLMD_VCT_RESULT0 0x2000
400 #define P1SCLMD_VCT_EN 0x1000
401 #define P1SCLMD_FORCE_LNK 0x0800
402 #define P1SCLMD_REMOTE_LOOPBACK 0x0200
403 
404 //P1CR register
405 #define P1CR_LED_OFF 0x8000
406 #define P1CR_TX_DISABLE 0x4000
407 #define P1CR_RESTART_AN 0x2000
408 #define P1CR_DISABLE_AUTO_MDIX 0x0400
409 #define P1CR_FORCE_MDIX 0x0200
410 #define P1CR_AN_ENABLE 0x0080
411 #define P1CR_FORCE_SPEED 0x0040
412 #define P1CR_FORCE_DUPLEX 0x0020
413 #define P1CR_ADV_PAUSE 0x0010
414 #define P1CR_ADV_100_FD 0x0008
415 #define P1CR_ADV_100 0x0004
416 #define P1CR_ADV_10_FD 0x0002
417 #define P1CR_ADV_10 0x0001
418 
419 //P1SR register
420 #define P1SR_HP_MDIX 0x8000
421 #define P1SR_REVERSED_POLARITY 0x2000
422 #define P1SR_OPERATION_SPEED 0x0400
423 #define P1SR_OPERATION_DUPLEX 0x0200
424 #define P1SR_MDIX_STATUS 0x0080
425 #define P1SR_AN_DONE 0x0040
426 #define P1SR_LINK_GOOD 0x0020
427 #define P1SR_PARTNER_ADV_PAUSE 0x0010
428 #define P1SR_PARTNER_ADV_100_FD 0x0008
429 #define P1SR_PARTNER_ADV_100 0x0004
430 #define P1SR_PARTNER_ADV_10_FD 0x0002
431 #define P1SR_PARTNER_ADV_10 0x0001
432 
433 //Transmit control word
434 #define TX_CTRL_TXIC 0x8000
435 #define TX_CTRL_TXFID 0x003F
436 
437 //C++ guard
438 #ifdef __cplusplus
439 extern "C" {
440 #endif
441 
442 
443 /**
444  * @brief TX packet header
445  **/
446 
447 typedef __start_packed struct
448 {
449  uint16_t controlWord;
450  uint16_t byteCount;
452 
453 
454 /**
455  * @brief RX packet header
456  **/
457 
458 typedef __start_packed struct
459 {
460  uint16_t statusWord;
461  uint16_t byteCount;
463 
464 
465 /**
466  * @brief KSZ8851 driver context
467  **/
468 
469 typedef struct
470 {
471  uint_t frameId; ///<Identify a frame and its associated status
472  uint8_t *txBuffer; ///<Transmit buffer
473  uint8_t *rxBuffer; ///<Receive buffer
475 
476 
477 //KSZ8851 driver
478 extern const NicDriver ksz8851Driver;
479 
480 //KSZ8851 related functions
481 error_t ksz8851Init(NetInterface *interface);
482 
483 void ksz8851Tick(NetInterface *interface);
484 
485 void ksz8851EnableIrq(NetInterface *interface);
486 void ksz8851DisableIrq(NetInterface *interface);
488 void ksz8851EventHandler(NetInterface *interface);
489 
491  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
492 
494 
496 
497 void ksz8851WriteReg(NetInterface *interface, uint8_t address, uint16_t data);
498 uint16_t ksz8851ReadReg(NetInterface *interface, uint8_t address);
499 
500 void ksz8851WriteFifo(NetInterface *interface, const uint8_t *data,
501  size_t length);
502 
503 void ksz8851ReadFifo(NetInterface *interface, uint8_t *data, size_t length);
504 
505 void ksz8851SetBit(NetInterface *interface, uint8_t address, uint16_t mask);
506 void ksz8851ClearBit(NetInterface *interface, uint8_t address, uint16_t mask);
507 
508 uint32_t ksz8851CalcCrc(const void *data, size_t length);
509 
510 void ksz8851DumpReg(NetInterface *interface);
511 
512 //C++ guard
513 #ifdef __cplusplus
514 }
515 #endif
516 
517 #endif
uint8_t length
Definition: coap_common.h:190
void ksz8851EnableIrq(NetInterface *interface)
Enable interrupts.
int bool_t
Definition: compiler_port.h:49
uint8_t data[]
Definition: ethernet.h:209
uint16_t byteCount
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
uint16_t controlWord
error_t ksz8851UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void ksz8851ReadFifo(NetInterface *interface, uint8_t *data, size_t length)
Read RX FIFO.
void ksz8851DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
__start_packed struct @49 Ksz8851RxHeader
RX packet header.
error_t
Error codes.
Definition: error.h:42
error_t ksz8851Init(NetInterface *interface)
KSZ8851 controller initialization.
bool_t ksz8851IrqHandler(NetInterface *interface)
KSZ8851 interrupt service routine.
void ksz8851EventHandler(NetInterface *interface)
KSZ8851 event handler.
uint_t frameId
Identify a frame and its associated status.
#define NetInterface
Definition: net.h:36
__start_packed struct _Ipv4Header __end_packed
#define NetTxAncillary
Definition: net_misc.h:36
uint8_t mask
Definition: web_socket.h:317
uint8_t * txBuffer
Transmit buffer.
uint32_t ksz8851CalcCrc(const void *data, size_t length)
CRC calculation.
uint16_t statusWord
KSZ8851 driver context.
error_t ksz8851ReceivePacket(NetInterface *interface)
Receive a packet.
uint16_t ksz8851ReadReg(NetInterface *interface, uint8_t address)
Read KSZ8851 register.
uint8_t * rxBuffer
Receive buffer.
Ipv6Addr address
void ksz8851DisableIrq(NetInterface *interface)
Disable interrupts.
error_t ksz8851SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void ksz8851ClearBit(NetInterface *interface, uint8_t address, uint16_t mask)
Clear bit field.
void ksz8851WriteReg(NetInterface *interface, uint8_t address, uint16_t data)
Write KSZ8851 register.
void ksz8851SetBit(NetInterface *interface, uint8_t address, uint16_t mask)
Set bit field.
unsigned int uint_t
Definition: compiler_port.h:45
NIC driver.
Definition: nic.h:257
void ksz8851WriteFifo(NetInterface *interface, const uint8_t *data, size_t length)
Write TX FIFO.
void ksz8851Tick(NetInterface *interface)
KSZ8851 timer handler.
__start_packed struct @48 Ksz8851TxHeader
TX packet header.
const NicDriver ksz8851Driver
KSZ8851 driver.