ksz8851_driver.h
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1 /**
2  * @file ksz8851_driver.h
3  * @brief KSZ8851 Ethernet controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _KSZ8851_DRIVER_H
30 #define _KSZ8851_DRIVER_H
31 
32 //SPI interface support
33 #ifndef KSZ8851_SPI_SUPPORT
34  #define KSZ8851_SPI_SUPPORT ENABLED
35 #elif (KSZ8851_SPI_SUPPORT != ENABLED && KSZ8851_SPI_SUPPORT != DISABLED)
36  #error KSZ8851_SPI_SUPPORT parameter is not valid
37 #endif
38 
39 //KSZ8851 data register
40 #ifndef KSZ8851_DATA_REG
41  #define KSZ8851_DATA_REG *((volatile uint16_t *) 0x60000000)
42 #endif
43 
44 //KSZ8851 command register
45 #ifndef KSZ8851_CMD_REG
46  #define KSZ8851_CMD_REG *((volatile uint16_t *) 0x60000004)
47 #endif
48 
49 //Device ID
50 #define KSZ8851_REV_A2_ID 0x8870
51 #define KSZ8851_REV_A3_ID 0x8872
52 
53 //SPI command set
54 #define KSZ8851_CMD_RD_REG 0x00
55 #define KSZ8851_CMD_WR_REG 0x40
56 #define KSZ8851_CMD_RD_FIFO 0x80
57 #define KSZ8851_CMD_WR_FIFO 0xC0
58 
59 //Byte enable bits
60 #if (KSZ8851_SPI_SUPPORT == ENABLED)
61  #define KSZ8851_CMD_B0 0x04
62  #define KSZ8851_CMD_B1 0x08
63  #define KSZ8851_CMD_B2 0x10
64  #define KSZ8851_CMD_B3 0x20
65 #else
66  #define KSZ8851_CMD_B0 0x1000
67  #define KSZ8851_CMD_B1 0x2000
68  #define KSZ8851_CMD_B2 0x4000
69  #define KSZ8851_CMD_B3 0x8000
70 #endif
71 
72 //KSZ8851 registers
73 #define KSZ8851_REG_CCR 0x08
74 #define KSZ8851_REG_MARL 0x10
75 #define KSZ8851_REG_MARM 0x12
76 #define KSZ8851_REG_MARH 0x14
77 #define KSZ8851_REG_OBCR 0x20
78 #define KSZ8851_REG_EEPCR 0x22
79 #define KSZ8851_REG_MBIR 0x24
80 #define KSZ8851_REG_GRR 0x26
81 #define KSZ8851_REG_WFCR 0x2A
82 #define KSZ8851_REG_WF0CRC0 0x30
83 #define KSZ8851_REG_WF0CRC1 0x32
84 #define KSZ8851_REG_WF0BM0 0x34
85 #define KSZ8851_REG_WF0BM1 0x36
86 #define KSZ8851_REG_WF0BM2 0x38
87 #define KSZ8851_REG_WF0BM3 0x3A
88 #define KSZ8851_REG_WF1CRC0 0x40
89 #define KSZ8851_REG_WF1CRC1 0x42
90 #define KSZ8851_REG_WF1BM0 0x44
91 #define KSZ8851_REG_WF1BM1 0x46
92 #define KSZ8851_REG_WF1BM2 0x48
93 #define KSZ8851_REG_WF1BM3 0x4A
94 #define KSZ8851_REG_WF2CRC0 0x50
95 #define KSZ8851_REG_WF2CRC1 0x52
96 #define KSZ8851_REG_WF2BM0 0x54
97 #define KSZ8851_REG_WF2BM1 0x56
98 #define KSZ8851_REG_WF2BM2 0x58
99 #define KSZ8851_REG_WF2BM3 0x5A
100 #define KSZ8851_REG_WF3CRC0 0x60
101 #define KSZ8851_REG_WF3CRC1 0x62
102 #define KSZ8851_REG_WF3BM0 0x64
103 #define KSZ8851_REG_WF3BM1 0x66
104 #define KSZ8851_REG_WF3BM2 0x68
105 #define KSZ8851_REG_WF3BM3 0x6A
106 #define KSZ8851_REG_TXCR 0x70
107 #define KSZ8851_REG_TXSR 0x72
108 #define KSZ8851_REG_RXCR1 0x74
109 #define KSZ8851_REG_RXCR2 0x76
110 #define KSZ8851_REG_TXMIR 0x78
111 #define KSZ8851_REG_RXFHSR 0x7C
112 #define KSZ8851_REG_RXFHBCR 0x7E
113 #define KSZ8851_REG_TXQCR 0x80
114 #define KSZ8851_REG_RXQCR 0x82
115 #define KSZ8851_REG_TXFDPR 0x84
116 #define KSZ8851_REG_RXFDPR 0x86
117 #define KSZ8851_REG_RXDTTR 0x8C
118 #define KSZ8851_REG_RXDBCTR 0x8E
119 #define KSZ8851_REG_IER 0x90
120 #define KSZ8851_REG_ISR 0x92
121 #define KSZ8851_REG_RXFCTR 0x9C
122 #define KSZ8851_REG_TXNTFSR 0x9E
123 #define KSZ8851_REG_MAHTR0 0xA0
124 #define KSZ8851_REG_MAHTR1 0xA2
125 #define KSZ8851_REG_MAHTR2 0xA4
126 #define KSZ8851_REG_MAHTR3 0xA6
127 #define KSZ8851_REG_FCLWR 0xB0
128 #define KSZ8851_REG_FCHWR 0xB2
129 #define KSZ8851_REG_FCOWR 0xB4
130 #define KSZ8851_REG_CIDER 0xC0
131 #define KSZ8851_REG_CGCR 0xC6
132 #define KSZ8851_REG_IACR 0xC8
133 #define KSZ8851_REG_IADLR 0xD0
134 #define KSZ8851_REG_IADHR 0xD2
135 #define KSZ8851_REG_PMECR 0xD4
136 #define KSZ8851_REG_GSWUTR 0xD6
137 #define KSZ8851_REG_PHYRR 0xD8
138 #define KSZ8851_REG_P1MBCR 0xE4
139 #define KSZ8851_REG_P1MBSR 0xE6
140 #define KSZ8851_REG_PHY1ILR 0xE8
141 #define KSZ8851_REG_PHY1IHR 0xEA
142 #define KSZ8851_REG_P1ANAR 0xEC
143 #define KSZ8851_REG_P1ANLPR 0xEE
144 #define KSZ8851_REG_P1SCLMD 0xF4
145 #define KSZ8851_REG_P1CR 0xF6
146 #define KSZ8851_REG_P1SR 0xF8
147 
148 //CCR register
149 #define CCR_BUS_ENDIAN_MODE 0x0400
150 #define CCR_EEPROM_PRESENCE 0x0200
151 #define CCR_SPI_MODE 0x0100
152 #define CCR_8_BIT_DATA_BUS 0x0080
153 #define CCR_16_BIT_DATA_BUS 0x0040
154 #define CCR_32_BIT_DATA_BUS 0x0020
155 #define CCR_BUS_SHARED_MODE 0x0010
156 #define CCR_128_PIN_PACKAGE 0x0008
157 #define CCR_48_PIN_PACKAGE 0x0002
158 #define CCR_32_PIN_PACKAGE 0x0001
159 
160 //OBCR register
161 #define OBCR_OUT_DRIVE_STRENGTH 0x0040
162 #define OBCR_SPI_SO_DELAY2 0x0020
163 #define OBCR_SPI_SO_DELAY1 0x0010
164 #define OBCR_SPI_SO_DELAY0 0x0008
165 #define OBCR_BUS_CLOCK_SEL 0x0004
166 #define OBCR_BUS_CLOCK_DIV1 0x0002
167 #define OBCR_BUS_CLOCK_DIV0 0x0001
168 
169 //EEPCR register
170 #define EEPCR_EESA 0x0010
171 #define EEPCR_EESB 0x0008
172 #define EEPCR_EECB2 0x0004
173 #define EEPCR_EECB1 0x0002
174 #define EEPCR_EECB0 0x0001
175 
176 //MBIR register
177 #define MBIR_TXMBF 0x1000
178 #define MBIR_TXMBFA 0x0800
179 #define MBIR_TXMBFC2 0x0400
180 #define MBIR_TXMBFC1 0x0200
181 #define MBIR_TXMBFC0 0x0100
182 #define MBIR_RXMBF 0x0010
183 #define MBIR_RXMBFA 0x0008
184 #define MBIR_RXMBFC2 0x0004
185 #define MBIR_RXMBFC1 0x0002
186 #define MBIR_RXMBFC0 0x0001
187 
188 //GRR register
189 #define GRR_QMU_MODULE_SOFT_RST 0x0002
190 #define GRR_GLOBAL_SOFT_RST 0x0001
191 
192 //WFCR register
193 #define WFCR_MPRXE 0x0080
194 #define WFCR_WF3E 0x0008
195 #define WFCR_WF2E 0x0004
196 #define WFCR_WF1E 0x0002
197 #define WFCR_WF0E 0x0001
198 
199 //TXCR register
200 #define TXCR_TCGICMP 0x0100
201 #define TXCR_TCGUDP 0x0080
202 #define TXCR_TCGTCP 0x0040
203 #define TXCR_TCGIP 0x0020
204 #define TXCR_FTXQ 0x0010
205 #define TXCR_TXFCE 0x0008
206 #define TXCR_TXPE 0x0004
207 #define TXCR_TXCE 0x0002
208 #define TXCR_TXE 0x0001
209 
210 //TXSR register
211 #define TXSR_TXLC 0x2000
212 #define TXSR_TXMC 0x1000
213 #define TXSR_TXFID5 0x0020
214 #define TXSR_TXFID4 0x0010
215 #define TXSR_TXFID3 0x0008
216 #define TXSR_TXFID2 0x0004
217 #define TXSR_TXFID1 0x0002
218 #define TXSR_TXFID0 0x0001
219 
220 //RXCR1 register
221 #define RXCR1_FRXQ 0x8000
222 #define RXCR1_RXUDPFCC 0x4000
223 #define RXCR1_RXTCPFCC 0x2000
224 #define RXCR1_RXIPFCC 0x1000
225 #define RXCR1_RXPAFMA 0x0800
226 #define RXCR1_RXFCE 0x0400
227 #define RXCR1_RXEFE 0x0200
228 #define RXCR1_RXMAFMA 0x0100
229 #define RXCR1_RXBE 0x0080
230 #define RXCR1_RXME 0x0040
231 #define RXCR1_RXUE 0x0020
232 #define RXCR1_RXAE 0x0010
233 #define RXCR1_RXINVF 0x0002
234 #define RXCR1_RXE 0x0001
235 
236 //RXCR2 register
237 #define RXCR2_SRDBL2 0x0080
238 #define RXCR2_SRDBL1 0x0040
239 #define RXCR2_SRDBL0 0x0020
240 #define RXCR2_IUFFP 0x0010
241 #define RXCR2_RXIUFCEZ 0x0008
242 #define RXCR2_UDPLFE 0x0004
243 #define RXCR2_RXICMPFCC 0x0002
244 #define RXCR2_RXSAF 0x0001
245 
246 //TXMIR register
247 #define TXMIR_TXMA_MASK 0x1FFF
248 
249 //RXFHSR register
250 #define RXFHSR_RXFV 0x8000
251 #define RXFHSR_RXICMPFCS 0x2000
252 #define RXFHSR_RXIPFCS 0x1000
253 #define RXFHSR_RXTCPFCS 0x0800
254 #define RXFHSR_RXUDPFCS 0x0400
255 #define RXFHSR_RXBF 0x0080
256 #define RXFHSR_RXMF 0x0040
257 #define RXFHSR_RXUF 0x0020
258 #define RXFHSR_RXMR 0x0010
259 #define RXFHSR_RXFT 0x0008
260 #define RXFHSR_RXFTL 0x0004
261 #define RXFHSR_RXRF 0x0002
262 #define RXFHSR_RXCE 0x0001
263 
264 //RXFHBCR register
265 #define RXFHBCR_RXBC_MASK 0x0FFF
266 
267 //TXQCR register
268 #define TXQCR_AETFE 0x0004
269 #define TXQCR_TXQMAM 0x0002
270 #define TXQCR_METFE 0x0001
271 
272 //RXQCR register
273 #define RXQCR_RXDTTS 0x1000
274 #define RXQCR_RXDBCTS 0x0800
275 #define RXQCR_RXFCTS 0x0400
276 #define RXQCR_RXIPHTOE 0x0200
277 #define RXQCR_RXDTTE 0x0080
278 #define RXQCR_RXDBCTE 0x0040
279 #define RXQCR_RXFCTE 0x0020
280 #define RXQCR_ADRFE 0x0010
281 #define RXQCR_SDA 0x0008
282 #define RXQCR_RRXEF 0x0001
283 
284 //TXFDPR register
285 #define TXFDPR_TXFPAI 0x4000
286 
287 //RXFDPR register
288 #define RXFDPR_RXFPAI 0x4000
289 
290 //IER register
291 #define IER_LCIE 0x8000
292 #define IER_TXIE 0x4000
293 #define IER_RXIE 0x2000
294 #define IER_RXOIE 0x0800
295 #define IER_TXPSIE 0x0200
296 #define IER_RXPSIE 0x0100
297 #define IER_TXSAIE 0x0040
298 #define IER_RXWFDIE 0x0020
299 #define IER_RXMPDIE 0x0010
300 #define IER_LDIE 0x0008
301 #define IER_EDIE 0x0004
302 #define IER_SPIBEIE 0x0002
303 #define IER_DEDIE 0x0001
304 
305 //ISR register
306 #define ISR_LCIS 0x8000
307 #define ISR_TXIS 0x4000
308 #define ISR_RXIS 0x2000
309 #define ISR_RXOIS 0x0800
310 #define ISR_TXPSIS 0x0200
311 #define ISR_RXPSIS 0x0100
312 #define ISR_TXSAIS 0x0040
313 #define ISR_RXWFDIS 0x0020
314 #define ISR_RXMPDIS 0x0010
315 #define ISR_LDIS 0x0008
316 #define ISR_EDIS 0x0004
317 #define ISR_SPIBEIS 0x0002
318 
319 //CGCR register
320 #define CGCR_LEDSEL0 0x0200
321 
322 //IACR register
323 #define IACR_READ_ENABLE 0x1000
324 #define IACR_TABLE_SELECT1 0x0800
325 #define IACR_TABLE_SELECT0 0x0400
326 
327 //PMECR register
328 #define PMECR_PME_DELAY_EN 0x4000
329 #define PMECR_PME_POLARITY 0x1000
330 #define PMECR_PME_WUP_FRAME_EN 0x0800
331 #define PMECR_PME_MAGIC_EN 0x0400
332 #define PMECR_PME_LINK_UP_EN 0x0200
333 #define PMECR_PME_ENERGY_EN 0x0100
334 #define PMECR_AUTO_WUP_EN 0x0080
335 #define PMECR_WUP_NORMAL_OP_MODE 0x0040
336 #define PMECR_WUP_FROM_WUP_FRAME 0x0020
337 #define PMECR_WUP_FROM_MAGIC 0x0010
338 #define PMECR_WUP_FROM_LINK_UP 0x0008
339 #define PMECR_WUP_FROM_ENERGY 0x0004
340 #define PMECR_PWR_MODE1 0x0002
341 #define PMECR_PWR_MODE0 0x0001
342 
343 //PHYRR register
344 #define PHYRR_PHY_RESET 0x0001
345 
346 //P1MBCR register
347 #define P1MBCR_LOCAL_LOOPBACK 0x4000
348 #define P1MBCR_FORCE_100 0x2000
349 #define P1MBCR_AN_ENABLE 0x1000
350 #define P1MBCR_RESTART_AN 0x0200
351 #define P1MBCR_FORCE_FULL_DUPLEX 0x0100
352 #define P1MBCR_HP_MDIX 0x0020
353 #define P1MBCR_FORCE_MDIX 0x0010
354 #define P1MBCR_DISABLE_MDIX 0x0008
355 #define P1MBCR_DISABLE_TRANSMIT 0x0002
356 #define P1MBCR_DISABLE_LED 0x0001
357 
358 //P1MBSR register
359 #define P1MBSR_T4_CAPABLE 0x8000
360 #define P1MBSR_100_FD_CAPABLE 0x4000
361 #define P1MBSR_100_CAPABLE 0x2000
362 #define P1MBSR_10_FD_CAPABLE 0x1000
363 #define P1MBSR_10_CAPABLE 0x0800
364 #define P1MBSR_PREAMBLE_SUPPR 0x0040
365 #define P1MBSR_AN_COMPLETE 0x0020
366 #define P1MBSR_AN_CAPABLE 0x0008
367 #define P1MBSR_LINK_STATUS 0x0004
368 #define P1MBSR_JABBER_TEST 0x0002
369 #define P1MBSR_EXTENDED_CAPABLE 0x0001
370 
371 //P1ANAR register
372 #define P1ANAR_NEXT_PAGE 0x8000
373 #define P1ANAR_REMOTE_FAULT 0x2000
374 #define P1ANAR_ADV_PAUSE 0x0400
375 #define P1ANAR_ADV_100_FD 0x0100
376 #define P1ANAR_ADV_100 0x0080
377 #define P1ANAR_ADV_10_FD 0x0040
378 #define P1ANAR_ADV_10 0x0020
379 #define P1ANAR_SELECTOR_FIELD4 0x0010
380 #define P1ANAR_SELECTOR_FIELD3 0x0008
381 #define P1ANAR_SELECTOR_FIELD2 0x0004
382 #define P1ANAR_SELECTOR_FIELD1 0x0002
383 #define P1ANAR_SELECTOR_FIELD0 0x0001
384 
385 //P1ANLPR register
386 #define P1ANLPR_NEXT_PAGE 0x8000
387 #define P1ANLPR_LP_ACK 0x4000
388 #define P1ANLPR_REMOTE_FAULT 0x2000
389 #define P1ANLPR_ADV_PAUSE 0x0400
390 #define P1ANLPR_ADV_100_FD 0x0100
391 #define P1ANLPR_ADV_100 0x0080
392 #define P1ANLPR_ADV_10_FD 0x0040
393 #define P1ANLPR_ADV_10 0x0020
394 
395 //P1SCLMD register
396 #define P1SCLMD_VCT_RESULT1 0x4000
397 #define P1SCLMD_VCT_RESULT0 0x2000
398 #define P1SCLMD_VCT_EN 0x1000
399 #define P1SCLMD_FORCE_LNK 0x0800
400 #define P1SCLMD_REMOTE_LOOPBACK 0x0200
401 
402 //P1CR register
403 #define P1CR_LED_OFF 0x8000
404 #define P1CR_TX_DISABLE 0x4000
405 #define P1CR_RESTART_AN 0x2000
406 #define P1CR_DISABLE_AUTO_MDIX 0x0400
407 #define P1CR_FORCE_MDIX 0x0200
408 #define P1CR_AN_ENABLE 0x0080
409 #define P1CR_FORCE_SPEED 0x0040
410 #define P1CR_FORCE_DUPLEX 0x0020
411 #define P1CR_ADV_PAUSE 0x0010
412 #define P1CR_ADV_100_FD 0x0008
413 #define P1CR_ADV_100 0x0004
414 #define P1CR_ADV_10_FD 0x0002
415 #define P1CR_ADV_10 0x0001
416 
417 //P1SR register
418 #define P1SR_HP_MDIX 0x8000
419 #define P1SR_REVERSED_POLARITY 0x2000
420 #define P1SR_OPERATION_SPEED 0x0400
421 #define P1SR_OPERATION_DUPLEX 0x0200
422 #define P1SR_MDIX_STATUS 0x0080
423 #define P1SR_AN_DONE 0x0040
424 #define P1SR_LINK_GOOD 0x0020
425 #define P1SR_PARTNER_ADV_PAUSE 0x0010
426 #define P1SR_PARTNER_ADV_100_FD 0x0008
427 #define P1SR_PARTNER_ADV_100 0x0004
428 #define P1SR_PARTNER_ADV_10_FD 0x0002
429 #define P1SR_PARTNER_ADV_10 0x0001
430 
431 //Transmit control word
432 #define TX_CTRL_TXIC 0x8000
433 #define TX_CTRL_TXFID 0x003F
434 
435 //C++ guard
436 #ifdef __cplusplus
437  extern "C" {
438 #endif
439 
440 
441 /**
442  * @brief TX packet header
443  **/
444 
445 typedef __start_packed struct
446 {
447  uint16_t controlWord;
448  uint16_t byteCount;
450 
451 
452 /**
453  * @brief RX packet header
454  **/
455 
456 typedef __start_packed struct
457 {
458  uint16_t statusWord;
459  uint16_t byteCount;
461 
462 
463 /**
464  * @brief KSZ8851 driver context
465  **/
466 
467 typedef struct
468 {
469  uint_t frameId; ///<Identify a frame and its associated status
470  uint8_t *txBuffer; ///<Transmit buffer
471  uint8_t *rxBuffer; ///<Receive buffer
473 
474 
475 //KSZ8851 driver
476 extern const NicDriver ksz8851Driver;
477 
478 //KSZ8851 related functions
479 error_t ksz8851Init(NetInterface *interface);
480 
481 void ksz8851Tick(NetInterface *interface);
482 
483 void ksz8851EnableIrq(NetInterface *interface);
484 void ksz8851DisableIrq(NetInterface *interface);
486 void ksz8851EventHandler(NetInterface *interface);
487 
489  const NetBuffer *buffer, size_t offset);
490 
492 
494 
495 void ksz8851WriteReg(NetInterface *interface, uint8_t address, uint16_t data);
496 uint16_t ksz8851ReadReg(NetInterface *interface, uint8_t address);
497 
498 void ksz8851WriteFifo(NetInterface *interface, const uint8_t *data, size_t length);
499 void ksz8851ReadFifo(NetInterface *interface, uint8_t *data, size_t length);
500 
501 void ksz8851SetBit(NetInterface *interface, uint8_t address, uint16_t mask);
502 void ksz8851ClearBit(NetInterface *interface, uint8_t address, uint16_t mask);
503 
504 uint32_t ksz8851CalcCrc(const void *data, size_t length);
505 
506 void ksz8851DumpReg(NetInterface *interface);
507 
508 //C++ guard
509 #ifdef __cplusplus
510  }
511 #endif
512 
513 #endif
void ksz8851DisableIrq(NetInterface *interface)
Disable interrupts.
error_t ksz8851Init(NetInterface *interface)
KSZ8851 controller initialization.
bool_t ksz8851IrqHandler(NetInterface *interface)
KSZ8851 interrupt service routine.
__start_packed struct @155 Ksz8851RxHeader
RX packet header.
error_t ksz8851ReceivePacket(NetInterface *interface)
Receive a packet.
void ksz8851Tick(NetInterface *interface)
KSZ8851 timer handler.
const NicDriver ksz8851Driver
KSZ8851 driver.
void ksz8851ClearBit(NetInterface *interface, uint8_t address, uint16_t mask)
Clear bit field.
uint8_t * txBuffer
Transmit buffer.
uint8_t mask
Definition: web_socket.h:315
void ksz8851WriteFifo(NetInterface *interface, const uint8_t *data, size_t length)
Write TX FIFO.
void ksz8851SetBit(NetInterface *interface, uint8_t address, uint16_t mask)
Set bit field.
uint16_t ksz8851ReadReg(NetInterface *interface, uint8_t address)
Read KSZ8851 register.
void ksz8851DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
uint_t frameId
Identify a frame and its associated status.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
KSZ8851 driver context.
void ksz8851EventHandler(NetInterface *interface)
KSZ8851 event handler.
__start_packed struct _Ipv4Header __end_packed
Ipv6Addr address
uint8_t * rxBuffer
Receive buffer.
error_t
Error codes.
Definition: error.h:40
void ksz8851EnableIrq(NetInterface *interface)
Enable interrupts.
unsigned int uint_t
Definition: compiler_port.h:43
error_t ksz8851SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void ksz8851WriteReg(NetInterface *interface, uint8_t address, uint16_t data)
Write KSZ8851 register.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint16_t statusWord
__start_packed struct @154 Ksz8851TxHeader
TX packet header.
uint16_t byteCount
uint8_t length
Definition: dtls_misc.h:140
error_t ksz8851UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
int bool_t
Definition: compiler_port.h:47
uint16_t controlWord
void ksz8851ReadFifo(NetInterface *interface, uint8_t *data, size_t length)
Read RX FIFO.
uint32_t ksz8851CalcCrc(const void *data, size_t length)
CRC calculation.