ksz8895_driver.h
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1 /**
2  * @file ksz8895_driver.h
3  * @brief KSZ8895 5-port Ethernet switch driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 #ifndef _KSZ8895_DRIVER_H
32 #define _KSZ8895_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Port identifiers
38 #define KSZ8895_PORT1 1
39 #define KSZ8895_PORT2 2
40 #define KSZ8895_PORT3 3
41 #define KSZ8895_PORT4 4
42 #define KSZ8895_PORT5 5
43 
44 //Port masks
45 #define KSZ8895_PORT_MASK 0x1F
46 #define KSZ8895_PORT1_MASK 0x01
47 #define KSZ8895_PORT2_MASK 0x02
48 #define KSZ8895_PORT3_MASK 0x04
49 #define KSZ8895_PORT4_MASK 0x08
50 #define KSZ8895_PORT5_MASK 0x10
51 
52 //SPI command byte
53 #define KSZ8895_SPI_CMD_WRITE 0x02
54 #define KSZ8895_SPI_CMD_READ 0x03
55 
56 //Size of static and dynamic MAC tables
57 #define KSZ8895_STATIC_MAC_TABLE_SIZE 32
58 #define KSZ8895_DYNAMIC_MAC_TABLE_SIZE 1024
59 
60 //Tail tag rules (host to KSZ8895)
61 #define KSZ8895_TAIL_TAG_NORMAL_ADDR_LOOKUP 0x80
62 #define KSZ8895_TAIL_TAG_PORT_SEL 0x40
63 #define KSZ8895_TAIL_TAG_DEST_QUEUE 0x30
64 #define KSZ8895_TAIL_TAG_DEST_PORT4 0x08
65 #define KSZ8895_TAIL_TAG_DEST_PORT3 0x04
66 #define KSZ8895_TAIL_TAG_DEST_PORT2 0x02
67 #define KSZ8895_TAIL_TAG_DEST_PORT1 0x01
68 
69 //Tail tag rules (KSZ8895 to host)
70 #define KSZ8895_TAIL_TAG_SRC_PORT 0x03
71 
72 //KSZ8895 PHY registers
73 #define KSZ8895_BMCR 0x00
74 #define KSZ8895_BMSR 0x01
75 #define KSZ8895_PHYID1 0x02
76 #define KSZ8895_PHYID2 0x03
77 #define KSZ8895_ANAR 0x04
78 #define KSZ8895_ANLPAR 0x05
79 #define KSZ8895_LINKMD 0x1D
80 #define KSZ8895_PHYSCS 0x1F
81 
82 //KSZ8895 Switch registers
83 #define KSZ8895_CHIP_ID0 0x00
84 #define KSZ8895_CHIP_ID1 0x01
85 #define KSZ8895_GLOBAL_CTRL0 0x02
86 #define KSZ8895_GLOBAL_CTRL1 0x03
87 #define KSZ8895_GLOBAL_CTRL2 0x04
88 #define KSZ8895_GLOBAL_CTRL3 0x05
89 #define KSZ8895_GLOBAL_CTRL4 0x06
90 #define KSZ8895_GLOBAL_CTRL5 0x07
91 #define KSZ8895_GLOBAL_CTRL6 0x08
92 #define KSZ8895_GLOBAL_CTRL7 0x09
93 #define KSZ8895_GLOBAL_CTRL8 0x0A
94 #define KSZ8895_GLOBAL_CTRL9 0x0B
95 #define KSZ8895_GLOBAL_CTRL10 0x0C
96 #define KSZ8895_GLOBAL_CTRL11 0x0D
97 #define KSZ8895_PD_MGMT_CTRL1 0x0E
98 #define KSZ8895_PD_MGMT_CTRL2 0x0F
99 #define KSZ8895_PORT1_CTRL0 0x10
100 #define KSZ8895_PORT1_CTRL1 0x11
101 #define KSZ8895_PORT1_CTRL2 0x12
102 #define KSZ8895_PORT1_CTRL3 0x13
103 #define KSZ8895_PORT1_CTRL4 0x14
104 #define KSZ8895_PORT1_STAT0 0x19
105 #define KSZ8895_PORT1_PSCS 0x1A
106 #define KSZ8895_PORT1_LINKMD 0x1B
107 #define KSZ8895_PORT1_CTRL5 0x1C
108 #define KSZ8895_PORT1_CTRL6 0x1D
109 #define KSZ8895_PORT1_STAT1 0x1E
110 #define KSZ8895_PORT1_CTRL7_STAT2 0x1F
111 #define KSZ8895_PORT2_CTRL0 0x20
112 #define KSZ8895_PORT2_CTRL1 0x21
113 #define KSZ8895_PORT2_CTRL2 0x22
114 #define KSZ8895_PORT2_CTRL3 0x23
115 #define KSZ8895_PORT2_CTRL4 0x24
116 #define KSZ8895_PORT2_STAT0 0x29
117 #define KSZ8895_PORT2_PSCS 0x2A
118 #define KSZ8895_PORT2_LINKMD 0x2B
119 #define KSZ8895_PORT2_CTRL5 0x2C
120 #define KSZ8895_PORT2_CTRL6 0x2D
121 #define KSZ8895_PORT2_STAT1 0x2E
122 #define KSZ8895_PORT2_CTRL7_STAT2 0x2F
123 #define KSZ8895_PORT3_CTRL0 0x30
124 #define KSZ8895_PORT3_CTRL1 0x31
125 #define KSZ8895_PORT3_CTRL2 0x32
126 #define KSZ8895_PORT3_CTRL3 0x33
127 #define KSZ8895_PORT3_CTRL4 0x34
128 #define KSZ8895_PORT3_STAT0 0x39
129 #define KSZ8895_PORT3_PSCS 0x3A
130 #define KSZ8895_PORT3_LINKMD 0x3B
131 #define KSZ8895_PORT3_CTRL5 0x3C
132 #define KSZ8895_PORT3_CTRL6 0x3D
133 #define KSZ8895_PORT3_STAT1 0x3E
134 #define KSZ8895_PORT3_CTRL7_STAT2 0x3F
135 #define KSZ8895_PORT4_CTRL0 0x40
136 #define KSZ8895_PORT4_CTRL1 0x41
137 #define KSZ8895_PORT4_CTRL2 0x42
138 #define KSZ8895_PORT4_CTRL3 0x43
139 #define KSZ8895_PORT4_CTRL4 0x44
140 #define KSZ8895_PORT4_STAT0 0x49
141 #define KSZ8895_PORT4_PSCS 0x4A
142 #define KSZ8895_PORT4_LINKMD 0x4B
143 #define KSZ8895_PORT4_CTRL5 0x4C
144 #define KSZ8895_PORT4_CTRL6 0x4D
145 #define KSZ8895_PORT4_STAT1 0x4E
146 #define KSZ8895_PORT4_CTRL7_STAT2 0x4F
147 #define KSZ8895_PORT5_CTRL0 0x50
148 #define KSZ8895_PORT5_CTRL1 0x51
149 #define KSZ8895_PORT5_CTRL2 0x52
150 #define KSZ8895_PORT5_CTRL3 0x53
151 #define KSZ8895_PORT5_CTRL4 0x54
152 #define KSZ8895_RMII_MGMT_CTRL 0x57
153 #define KSZ8895_PORT5_STAT0 0x59
154 #define KSZ8895_PORT5_PSCS 0x5A
155 #define KSZ8895_PORT5_LINKMD 0x5B
156 #define KSZ8895_PORT5_CTRL5 0x5C
157 #define KSZ8895_PORT5_CTRL6 0x5D
158 #define KSZ8895_PORT5_STAT1 0x5E
159 #define KSZ8895_PORT5_CTRL7_STAT2 0x5F
160 #define KSZ8895_MAC_ADDR0 0x68
161 #define KSZ8895_MAC_ADDR1 0x69
162 #define KSZ8895_MAC_ADDR2 0x6A
163 #define KSZ8895_MAC_ADDR3 0x6B
164 #define KSZ8895_MAC_ADDR4 0x6C
165 #define KSZ8895_MAC_ADDR5 0x6D
166 #define KSZ8895_INDIRECT_CTRL0 0x6E
167 #define KSZ8895_INDIRECT_CTRL1 0x6F
168 #define KSZ8895_INDIRECT_DATA8 0x70
169 #define KSZ8895_INDIRECT_DATA7 0x71
170 #define KSZ8895_INDIRECT_DATA6 0x72
171 #define KSZ8895_INDIRECT_DATA5 0x73
172 #define KSZ8895_INDIRECT_DATA4 0x74
173 #define KSZ8895_INDIRECT_DATA3 0x75
174 #define KSZ8895_INDIRECT_DATA2 0x76
175 #define KSZ8895_INDIRECT_DATA1 0x77
176 #define KSZ8895_INDIRECT_DATA0 0x78
177 #define KSZ8895_INT_STAT 0x7C
178 #define KSZ8895_INT_MASK 0x7D
179 #define KSZ8895_GLOBAL_CTRL12 0x80
180 #define KSZ8895_GLOBAL_CTRL13 0x81
181 #define KSZ8895_GLOBAL_CTRL14 0x82
182 #define KSZ8895_GLOBAL_CTRL15 0x83
183 #define KSZ8895_GLOBAL_CTRL16 0x84
184 #define KSZ8895_GLOBAL_CTRL17 0x85
185 #define KSZ8895_GLOBAL_CTRL18 0x86
186 #define KSZ8895_GLOBAL_CTRL19 0x87
187 #define KSZ8895_ID 0x89
188 #define KSZ8895_TOS_PRIO_CTRL0 0x90
189 #define KSZ8895_TOS_PRIO_CTRL1 0x91
190 #define KSZ8895_TOS_PRIO_CTRL2 0x92
191 #define KSZ8895_TOS_PRIO_CTRL3 0x93
192 #define KSZ8895_TOS_PRIO_CTRL4 0x94
193 #define KSZ8895_TOS_PRIO_CTRL5 0x95
194 #define KSZ8895_TOS_PRIO_CTRL6 0x96
195 #define KSZ8895_TOS_PRIO_CTRL7 0x97
196 #define KSZ8895_TOS_PRIO_CTRL8 0x98
197 #define KSZ8895_TOS_PRIO_CTRL9 0x99
198 #define KSZ8895_TOS_PRIO_CTRL10 0x9A
199 #define KSZ8895_TOS_PRIO_CTRL11 0x9B
200 #define KSZ8895_TOS_PRIO_CTRL12 0x9C
201 #define KSZ8895_TOS_PRIO_CTRL13 0x9D
202 #define KSZ8895_TOS_PRIO_CTRL14 0x9E
203 #define KSZ8895_TOS_PRIO_CTRL15 0x9F
204 #define KSZ8895_PORT1_CTRL8 0xB0
205 #define KSZ8895_PORT1_CTRL9 0xB1
206 #define KSZ8895_PORT1_CTRL10 0xB2
207 #define KSZ8895_PORT1_CTRL11 0xB3
208 #define KSZ8895_PORT1_CTRL12 0xB4
209 #define KSZ8895_PORT1_CTRL13 0xB5
210 #define KSZ8895_PORT1_RATE_LIMIT_CTRL 0xB6
211 #define KSZ8895_PORT1_PRIO0_IG_LIMIT_CTRL1 0xB7
212 #define KSZ8895_PORT1_PRIO1_IG_LIMIT_CTRL2 0xB8
213 #define KSZ8895_PORT1_PRIO2_IG_LIMIT_CTRL3 0xB9
214 #define KSZ8895_PORT1_PRIO3_IG_LIMIT_CTRL4 0xBA
215 #define KSZ8895_PORT1_QUEUE0_EG_LIMIT_CTRL1 0xBB
216 #define KSZ8895_PORT1_QUEUE1_EG_LIMIT_CTRL2 0xBC
217 #define KSZ8895_PORT1_QUEUE2_EG_LIMIT_CTRL3 0xBD
218 #define KSZ8895_PORT1_QUEUE3_EG_LIMIT_CTRL4 0xBE
219 #define KSZ8895_TEST1 0xBF
220 #define KSZ8895_PORT2_CTRL8 0xC0
221 #define KSZ8895_PORT2_CTRL9 0xC1
222 #define KSZ8895_PORT2_CTRL10 0xC2
223 #define KSZ8895_PORT2_CTRL11 0xC3
224 #define KSZ8895_PORT2_CTRL12 0xC4
225 #define KSZ8895_PORT2_CTRL13 0xC5
226 #define KSZ8895_PORT2_RATE_LIMIT_CTRL 0xC6
227 #define KSZ8895_PORT2_PRIO0_IG_LIMIT_CTRL1 0xC7
228 #define KSZ8895_PORT2_PRIO1_IG_LIMIT_CTRL2 0xC8
229 #define KSZ8895_PORT2_PRIO2_IG_LIMIT_CTRL3 0xC9
230 #define KSZ8895_PORT2_PRIO3_IG_LIMIT_CTRL4 0xCA
231 #define KSZ8895_PORT2_QUEUE0_EG_LIMIT_CTRL1 0xCB
232 #define KSZ8895_PORT2_QUEUE1_EG_LIMIT_CTRL2 0xCC
233 #define KSZ8895_PORT2_QUEUE2_EG_LIMIT_CTRL3 0xCD
234 #define KSZ8895_PORT2_QUEUE3_EG_LIMIT_CTRL4 0xCE
235 #define KSZ8895_PORT3_CTRL8 0xD0
236 #define KSZ8895_PORT3_CTRL9 0xD1
237 #define KSZ8895_PORT3_CTRL10 0xD2
238 #define KSZ8895_PORT3_CTRL11 0xD3
239 #define KSZ8895_PORT3_CTRL12 0xD4
240 #define KSZ8895_PORT3_CTRL13 0xD5
241 #define KSZ8895_PORT3_RATE_LIMIT_CTRL 0xD6
242 #define KSZ8895_PORT3_PRIO0_IG_LIMIT_CTRL1 0xD7
243 #define KSZ8895_PORT3_PRIO1_IG_LIMIT_CTRL2 0xD8
244 #define KSZ8895_PORT3_PRIO2_IG_LIMIT_CTRL3 0xD9
245 #define KSZ8895_PORT3_PRIO3_IG_LIMIT_CTRL4 0xDA
246 #define KSZ8895_PORT3_QUEUE0_EG_LIMIT_CTRL1 0xDB
247 #define KSZ8895_PORT3_QUEUE1_EG_LIMIT_CTRL2 0xDC
248 #define KSZ8895_PORT3_QUEUE2_EG_LIMIT_CTRL3 0xDD
249 #define KSZ8895_PORT3_QUEUE3_EG_LIMIT_CTRL4 0xDE
250 #define KSZ8895_TEST2 0xDF
251 #define KSZ8895_PORT4_CTRL8 0xE0
252 #define KSZ8895_PORT4_CTRL9 0xE1
253 #define KSZ8895_PORT4_CTRL10 0xE2
254 #define KSZ8895_PORT4_CTRL11 0xE3
255 #define KSZ8895_PORT4_CTRL12 0xE4
256 #define KSZ8895_PORT4_CTRL13 0xE5
257 #define KSZ8895_PORT4_RATE_LIMIT_CTRL 0xE6
258 #define KSZ8895_PORT4_PRIO0_IG_LIMIT_CTRL1 0xE7
259 #define KSZ8895_PORT4_PRIO1_IG_LIMIT_CTRL2 0xE8
260 #define KSZ8895_PORT4_PRIO2_IG_LIMIT_CTRL3 0xE9
261 #define KSZ8895_PORT4_PRIO3_IG_LIMIT_CTRL4 0xEA
262 #define KSZ8895_PORT4_QUEUE0_EG_LIMIT_CTRL1 0xEB
263 #define KSZ8895_PORT4_QUEUE1_EG_LIMIT_CTRL2 0xEC
264 #define KSZ8895_PORT4_QUEUE2_EG_LIMIT_CTRL3 0xED
265 #define KSZ8895_PORT4_QUEUE3_EG_LIMIT_CTRL4 0xEE
266 #define KSZ8895_PORT3_COPPER_FIBER_CTRL 0xEF
267 #define KSZ8895_PORT5_CTRL8 0xF0
268 #define KSZ8895_PORT5_CTRL9 0xF1
269 #define KSZ8895_PORT5_CTRL10 0xF2
270 #define KSZ8895_PORT5_CTRL11 0xF3
271 #define KSZ8895_PORT5_CTRL12 0xF4
272 #define KSZ8895_PORT5_CTRL13 0xF5
273 #define KSZ8895_PORT5_RATE_LIMIT_CTRL 0xF6
274 #define KSZ8895_PORT5_PRIO0_IG_LIMIT_CTRL1 0xF7
275 #define KSZ8895_PORT5_PRIO1_IG_LIMIT_CTRL2 0xF8
276 #define KSZ8895_PORT5_PRIO2_IG_LIMIT_CTRL3 0xF9
277 #define KSZ8895_PORT5_PRIO3_IG_LIMIT_CTRL4 0xFA
278 #define KSZ8895_PORT5_QUEUE0_EG_LIMIT_CTRL1 0xFB
279 #define KSZ8895_PORT5_QUEUE1_EG_LIMIT_CTRL2 0xFC
280 #define KSZ8895_PORT5_QUEUE2_EG_LIMIT_CTRL3 0xFD
281 #define KSZ8895_PORT5_QUEUE3_EG_LIMIT_CTRL4 0xFE
282 #define KSZ8895_TEST3 0xFF
283 
284 //KSZ8895 Switch register access macros
285 #define KSZ8895_PORTn_CTRL0(port) (0x00 + ((port) * 0x10))
286 #define KSZ8895_PORTn_CTRL1(port) (0x01 + ((port) * 0x10))
287 #define KSZ8895_PORTn_CTRL2(port) (0x02 + ((port) * 0x10))
288 #define KSZ8895_PORTn_CTRL3(port) (0x03 + ((port) * 0x10))
289 #define KSZ8895_PORTn_CTRL4(port) (0x04 + ((port) * 0x10))
290 #define KSZ8895_PORTn_STAT0(port) (0x09 + ((port) * 0x10))
291 #define KSZ8895_PORTn_PSCS(port) (0x0A + ((port) * 0x10))
292 #define KSZ8895_PORTn_LINKMD(port) (0x0B + ((port) * 0x10))
293 #define KSZ8895_PORTn_CTRL5(port) (0x0C + ((port) * 0x10))
294 #define KSZ8895_PORTn_CTRL6(port) (0x0D + ((port) * 0x10))
295 #define KSZ8895_PORTn_STAT1(port) (0x0E + ((port) * 0x10))
296 #define KSZ8895_PORTn_CTRL7_STAT2(port) (0x0F + ((port) * 0x10))
297 #define KSZ8895_PORTn_CTRL8(port) (0xA0 + ((port) * 0x10))
298 #define KSZ8895_PORTn_CTRL9(port) (0xA1 + ((port) * 0x10))
299 #define KSZ8895_PORTn_CTRL10(port) (0xA2 + ((port) * 0x10))
300 #define KSZ8895_PORTn_CTRL11(port) (0xA3 + ((port) * 0x10))
301 #define KSZ8895_PORTn_CTRL12(port) (0xA4 + ((port) * 0x10))
302 #define KSZ8895_PORTn_CTRL13(port) (0xA5 + ((port) * 0x10))
303 #define KSZ8895_PORTn_RATE_LIMIT_CTRL(port) (0xA6 + ((port) * 0x10))
304 #define KSZ8895_PORTn_PRIO0_IG_LIMIT_CTRL1(port) (0xA7 + ((port) * 0x10))
305 #define KSZ8895_PORTn_PRIO1_IG_LIMIT_CTRL2(port) (0xA8 + ((port) * 0x10))
306 #define KSZ8895_PORTn_PRIO2_IG_LIMIT_CTRL3(port) (0xA9 + ((port) * 0x10))
307 #define KSZ8895_PORTn_PRIO3_IG_LIMIT_CTRL4(port) (0xAA + ((port) * 0x10))
308 #define KSZ8895_PORTn_QUEUE0_EG_LIMIT_CTRL1(port) (0xAB + ((port) * 0x10))
309 #define KSZ8895_PORTn_QUEUE1_EG_LIMIT_CTRL2(port) (0xAC + ((port) * 0x10))
310 #define KSZ8895_PORTn_QUEUE2_EG_LIMIT_CTRL3(port) (0xAD + ((port) * 0x10))
311 #define KSZ8895_PORTn_QUEUE3_EG_LIMIT_CTRL4(port) (0xAE + ((port) * 0x10))
312 
313 //MII Control register
314 #define KSZ8895_BMCR_RESET 0x8000
315 #define KSZ8895_BMCR_LOOPBACK 0x4000
316 #define KSZ8895_BMCR_FORCE_100 0x2000
317 #define KSZ8895_BMCR_AN_EN 0x1000
318 #define KSZ8895_BMCR_POWER_DOWN 0x0800
319 #define KSZ8895_BMCR_ISOLATE 0x0400
320 #define KSZ8895_BMCR_RESTART_AN 0x0200
321 #define KSZ8895_BMCR_FORCE_FULL_DUPLEX 0x0100
322 #define KSZ8895_BMCR_COL_TEST 0x0080
323 #define KSZ8895_BMCR_HP_MDIX 0x0020
324 #define KSZ8895_BMCR_FORCE_MDI 0x0010
325 #define KSZ8895_BMCR_AUTO_MDIX_DIS 0x0008
326 #define KSZ8895_BMCR_FAR_END_FAULT_DIS 0x0004
327 #define KSZ8895_BMCR_TRANSMIT_DIS 0x0002
328 #define KSZ8895_BMCR_LED_DIS 0x0001
329 
330 //MII Status register
331 #define KSZ8895_BMSR_100BT4 0x8000
332 #define KSZ8895_BMSR_100BTX_FD 0x4000
333 #define KSZ8895_BMSR_100BTX_HD 0x2000
334 #define KSZ8895_BMSR_10BT_FD 0x1000
335 #define KSZ8895_BMSR_10BT_HD 0x0800
336 #define KSZ8895_BMSR_PREAMBLE_SUPPR 0x0040
337 #define KSZ8895_BMSR_AN_COMPLETE 0x0020
338 #define KSZ8895_BMSR_FAR_END_FAULT 0x0010
339 #define KSZ8895_BMSR_AN_CAPABLE 0x0008
340 #define KSZ8895_BMSR_LINK_STATUS 0x0004
341 #define KSZ8895_BMSR_JABBER_TEST 0x0002
342 #define KSZ8895_BMSR_EXTENDED_CAPABLE 0x0001
343 
344 //PHYID High register
345 #define KSZ8895_PHYID1_DEFAULT 0x0022
346 
347 //PHYID Low register
348 #define KSZ8895_PHYID2_DEFAULT 0x1450
349 
350 //Advertisement Ability register
351 #define KSZ8895_ANAR_NEXT_PAGE 0x8000
352 #define KSZ8895_ANAR_REMOTE_FAULT 0x2000
353 #define KSZ8895_ANAR_PAUSE 0x0400
354 #define KSZ8895_ANAR_100BTX_FD 0x0100
355 #define KSZ8895_ANAR_100BTX_HD 0x0080
356 #define KSZ8895_ANAR_10BT_FD 0x0040
357 #define KSZ8895_ANAR_10BT_HD 0x0020
358 #define KSZ8895_ANAR_SELECTOR 0x001F
359 #define KSZ8895_ANAR_SELECTOR_DEFAULT 0x0001
360 
361 //Link Partner Ability register
362 #define KSZ8895_ANLPAR_NEXT_PAGE 0x8000
363 #define KSZ8895_ANLPAR_LP_ACK 0x4000
364 #define KSZ8895_ANLPAR_REMOTE_FAULT 0x2000
365 #define KSZ8895_ANLPAR_PAUSE 0x0400
366 #define KSZ8895_ANLPAR_100BTX_FD 0x0100
367 #define KSZ8895_ANLPAR_100BTX_HD 0x0080
368 #define KSZ8895_ANLPAR_10BT_FD 0x0040
369 #define KSZ8895_ANLPAR_10BT_HD 0x0020
370 
371 //LinkMD Control/Status register
372 #define KSZ8895_LINKMD_TEST_EN 0x8000
373 #define KSZ8895_LINKMD_RESULT 0x6000
374 #define KSZ8895_LINKMD_SHORT 0x1000
375 #define KSZ8895_LINKMD_FAULT_COUNT 0x01FF
376 
377 //PHY Special Control/Status register
378 #define KSZ8895_PHYSCS_OP_MODE 0x0700
379 #define KSZ8895_PHYSCS_OP_MODE_AN 0x0100
380 #define KSZ8895_PHYSCS_OP_MODE_10BT_HD 0x0200
381 #define KSZ8895_PHYSCS_OP_MODE_100BTX_HD 0x0300
382 #define KSZ8895_PHYSCS_OP_MODE_10BT_FD 0x0500
383 #define KSZ8895_PHYSCS_OP_MODE_100BTX_FD 0x0600
384 #define KSZ8895_PHYSCS_OP_MODE_ISOLATE 0x0700
385 #define KSZ8895_PHYSCS_POLRVS 0x0020
386 #define KSZ8895_PHYSCS_MDIX_STATUS 0x0010
387 #define KSZ8895_PHYSCS_FORCE_LINK 0x0008
388 #define KSZ8895_PHYSCS_PWRSAVE 0x0004
389 #define KSZ8895_PHYSCS_REMOTE_LOOPBACK 0x0002
390 
391 //Chip ID0 register
392 #define KSZ8895_CHIP_ID0_FAMILY_ID 0xFF
393 #define KSZ8895_CHIP_ID0_FAMILY_ID_DEFAULT 0x95
394 
395 //Chip ID1 / Start Switch register
396 #define KSZ8895_CHIP_ID1_CHIP_ID 0xF0
397 #define KSZ8895_CHIP_ID1_CHIP_ID_MQX_FQX_MLX 0x40
398 #define KSZ8895_CHIP_ID1_CHIP_ID_RQX 0x60
399 #define KSZ8895_CHIP_ID1_REVISION_ID 0x0E
400 #define KSZ8895_CHIP_ID1_START_SWITCH 0x01
401 
402 //Global Control 0 register
403 #define KSZ8895_GLOBAL_CTRL0_NEW_BACK_OFF_EN 0x80
404 #define KSZ8895_GLOBAL_CTRL0_FLUSH_DYNAMIC_MAC_TABLE 0x20
405 #define KSZ8895_GLOBAL_CTRL0_FLUSH_STATIC_MAC_TABLE 0x10
406 #define KSZ8895_GLOBAL_CTRL0_PHY_MII_RMII_EN 0x08
407 #define KSZ8895_GLOBAL_CTRL0_UNH_MODE 0x02
408 #define KSZ8895_GLOBAL_CTRL0_LINK_CHANGE_AGE 0x01
409 
410 //Global Control 1 register
411 #define KSZ8895_GLOBAL_CTRL1_PASS_ALL_FRAMES 0x80
412 #define KSZ8895_GLOBAL_CTRL1_2KB_PKT_SUPPORT 0x40
413 #define KSZ8895_GLOBAL_CTRL1_TX_FLOW_CTRL_DIS 0x20
414 #define KSZ8895_GLOBAL_CTRL1_RX_FLOW_CTRL_DIS 0x10
415 #define KSZ8895_GLOBAL_CTRL1_FRAME_LEN_CHECK_EN 0x08
416 #define KSZ8895_GLOBAL_CTRL1_AGING_EN 0x04
417 #define KSZ8895_GLOBAL_CTRL1_FAST_AGE_EN 0x02
418 #define KSZ8895_GLOBAL_CTRL1_AGGRESSIVE_BACK_OFF_EN 0x01
419 
420 //Global Control 10 register
421 #define KSZ8895_GLOBAL_CTRL10_CLK_MODE 0x40
422 #define KSZ8895_GLOBAL_CTRL10_CPU_CLK_SEL 0x30
423 #define KSZ8895_GLOBAL_CTRL10_RESTORE_PREAMBLE_EN 0x04
424 #define KSZ8895_GLOBAL_CTRL10_TAIL_TAG_EN 0x02
425 #define KSZ8895_GLOBAL_CTRL10_PASS_FLOW_CTRL_PKT 0x01
426 
427 //Port N Control 0 register
428 #define KSZ8895_PORTn_CTRL0_BCAST_STORM_PROTECT_EN 0x80
429 #define KSZ8895_PORTn_CTRL0_DIFFSERV_PRIO_CLASS_EN 0x40
430 #define KSZ8895_PORTn_CTRL0_802_1P_PRIO_CLASS_EN 0x20
431 #define KSZ8895_PORTn_CTRL0_PORT_PRIO_CLASS_EN 0x18
432 #define KSZ8895_PORTn_CTRL0_TAG_INSERTION 0x04
433 #define KSZ8895_PORTn_CTRL0_TAG_REMOVAL 0x02
434 #define KSZ8895_PORTn_CTRL0_TWO_QUEUE_SPLIT_EN 0x01
435 
436 //Port N Control 1 register
437 #define KSZ8895_PORTn_CTRL1_SNIFFER_PORT 0x80
438 #define KSZ8895_PORTn_CTRL1_RECEIVE_SNIFF 0x40
439 #define KSZ8895_PORTn_CTRL1_TRANSMIT_SNIFF 0x20
440 #define KSZ8895_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x1F
441 
442 //Port N Control 2 register
443 #define KSZ8895_PORTn_CTRL2_USER_PRIO_CEILING 0x80
444 #define KSZ8895_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
445 #define KSZ8895_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
446 #define KSZ8895_PORTn_CTRL2_FORCE_FLOW_CTRL 0x10
447 #define KSZ8895_PORTn_CTRL2_BACK_PRESSURE_EN 0x08
448 #define KSZ8895_PORTn_CTRL2_TRANSMIT_EN 0x04
449 #define KSZ8895_PORTn_CTRL2_RECEIVE_EN 0x02
450 #define KSZ8895_PORTn_CTRL2_LEARNING_DIS 0x01
451 
452 //Port N Control 3 register
453 #define KSZ8895_PORTn_CTRL3_DEFAULT_USER_PRIO 0xE0
454 #define KSZ8895_PORTn_CTRL3_DEFAULT_CFI 0x10
455 #define KSZ8895_PORTn_CTRL3_DEFAULT_VID_MSB 0x0F
456 
457 //Port N Control 4 register
458 #define KSZ8895_PORTn_CTRL4_DEFAULT_VID_LSB 0xFF
459 
460 //RMII Management Control register
461 #define KSZ8895_RMII_MGMT_CTRL_SW5_CLK_OUT_DIS 0x08
462 #define KSZ8895_RMII_MGMT_CTRL_P5_CLK_OUT_DIS 0x04
463 
464 //Port N Status 0 register
465 #define KSZ8895_PORTn_STAT0_HP_MDIX 0x80
466 #define KSZ8895_PORTn_STAT0_POLRVS 0x20
467 #define KSZ8895_PORTn_STAT0_TX_FLOW_CTRL_EN 0x10
468 #define KSZ8895_PORTn_STAT0_RX_FLOW_CTRL_EN 0x08
469 #define KSZ8895_PORTn_STAT0_OP_SPEED 0x04
470 #define KSZ8895_PORTn_STAT0_OP_DUPLEX 0x02
471 
472 //Port N PHY Special Control/Status register
473 #define KSZ8895_PORTn_PSCS_VCT_10M_SHORT 0x80
474 #define KSZ8895_PORTn_PSCS_VCT_RESULT 0x60
475 #define KSZ8895_PORTn_PSCS_VCT_EN 0x10
476 #define KSZ8895_PORTn_PSCS_FORCE_LNK 0x08
477 #define KSZ8895_PORTn_PSCS_PWRSAVE 0x04
478 #define KSZ8895_PORTn_PSCS_REMOTE_LOOPBACK 0x02
479 #define KSZ8895_PORTn_PSCS_VCT_FAULT_COUNT_MSB 0x01
480 
481 //Port N LinkMD Result register
482 #define KSZ8895_PORTn_LINKMD_VCT_FAULT_COUNT_LSB 0xFF
483 
484 //Port N Status 1 register
485 #define KSZ8895_PORTn_STAT1_MDIX_STATUS 0x80
486 #define KSZ8895_PORTn_STAT1_AN_DONE 0x40
487 #define KSZ8895_PORTn_STAT1_LINK_GOOD 0x20
488 #define KSZ8895_PORTn_STAT1_LP_FLOW_CTRL_CAPABLE 0x10
489 #define KSZ8895_PORTn_STAT1_LP_100BTX_FD_CAPABLE 0x08
490 #define KSZ8895_PORTn_STAT1_LP_100BTX_HF_CAPABLE 0x04
491 #define KSZ8895_PORTn_STAT1_LP_10BT_FD_CAPABLE 0x02
492 #define KSZ8895_PORTn_STAT1_LP_10BT_HD_CAPABLE 0x01
493 
494 //Port N Control 7 / Status 2 register
495 #define KSZ8895_PORTn_CTRL7_STAT2_PHY_LOOPBACK 0x80
496 #define KSZ8895_PORTn_CTRL7_STAT2_PHY_ISOLATE 0x20
497 #define KSZ8895_PORTn_CTRL7_STAT2_SOFT_RESET 0x10
498 #define KSZ8895_PORTn_CTRL7_STAT2_FORCE_LINK 0x08
499 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE 0x07
500 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_AN 0x01
501 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_10BT_HD 0x02
502 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_100BTX_HD 0x03
503 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_10BT_FD 0x05
504 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_100BTX_FD 0x06
505 
506 //Indirect Access Control 0 register
507 #define KSZ8895_INDIRECT_CTRL0_WRITE 0x00
508 #define KSZ8895_INDIRECT_CTRL0_READ 0x10
509 #define KSZ8895_INDIRECT_CTRL0_TABLE_SEL 0x0C
510 #define KSZ8895_INDIRECT_CTRL0_TABLE_SEL_STATIC_MAC 0x00
511 #define KSZ8895_INDIRECT_CTRL0_TABLE_SEL_VLAN 0x04
512 #define KSZ8895_INDIRECT_CTRL0_TABLE_SEL_DYNAMIC_MAC 0x08
513 #define KSZ8895_INDIRECT_CTRL0_TABLE_SEL_MIB_COUNTER 0x0C
514 #define KSZ8895_INDIRECT_CTRL0_ADDR_H 0x03
515 
516 //Indirect Access Control 1 register
517 #define KSZ8895_INDIRECT_CTRL1_ADDR_L 0xFF
518 
519 //Identification register
520 #define KSZ8895_ID_REVISION_ID 0xF0
521 #define KSZ8895_ID_REVISION_ID_MQX_RQX_FQX_REV_A2 0x40
522 #define KSZ8895_ID_REVISION_ID_ML_REV_B2 0x40
523 #define KSZ8895_ID_REVISION_ID_MQX_RQX_FQX_REV_A3 0x50
524 #define KSZ8895_ID_REVISION_ID_ML_REV_B3 0x50
525 #define KSZ8895_ID_REVISION_ID_MQX_RQX_FQX_REV_A4 0x60
526 
527 //C++ guard
528 #ifdef __cplusplus
529 extern "C" {
530 #endif
531 
532 //CodeWarrior or Win32 compiler?
533 #if defined(__CWCC__) || defined(_WIN32)
534  #pragma pack(push, 1)
535 #endif
536 
537 
538 /**
539  * @brief Static MAC table entry (read operation)
540  **/
541 
542 typedef struct
543 {
544 #ifdef _CPU_BIG_ENDIAN
545  uint8_t fid : 7; //0
546  uint8_t useFid : 1;
547  uint8_t reserved : 1; //1
548  uint8_t override : 1;
549  uint8_t valid : 1;
550  uint8_t forwardPorts : 5;
551 #else
552  uint8_t useFid : 1; //0
553  uint8_t fid : 7;
554  uint8_t forwardPorts : 5; //1
555  uint8_t valid : 1;
556  uint8_t override : 1;
557  uint8_t reserved : 1;
558 #endif
561 
562 
563 /**
564  * @brief Static MAC table entry (write operation)
565  **/
566 
567 typedef struct
568 {
569  uint8_t fid; //0
570 #ifdef _CPU_BIG_ENDIAN
571  uint8_t useFid : 1; //1
572  uint8_t override : 1;
573  uint8_t valid : 1;
574  uint8_t forwardPorts : 5;
575 #else
576  uint8_t forwardPorts : 5; //1
577  uint8_t valid : 1;
578  uint8_t override : 1;
579  uint8_t useFid : 1;
580 #endif
583 
584 
585 /**
586  * @brief Dynamic MAC table entry
587  **/
588 
589 typedef struct
590 {
591 #ifdef _CPU_BIG_ENDIAN
592  uint8_t macEmpty : 1; //0
593  uint8_t numValidEntriesH : 7;
594  uint8_t numValidEntriesL : 3; //1
595  uint8_t timestamp : 2;
596  uint8_t sourcePort : 3;
597  uint8_t dataNotReady : 1; //2
598  uint8_t fid : 7;
599 #else
600  uint8_t numValidEntriesH : 7; //0
601  uint8_t macEmpty : 1;
602  uint8_t sourcePort : 3; //1
603  uint8_t timestamp : 2;
604  uint8_t numValidEntriesL : 3;
605  uint8_t fid : 7; //2
606  uint8_t dataNotReady : 1;
607 #endif
610 
611 
612 //CodeWarrior or Win32 compiler?
613 #if defined(__CWCC__) || defined(_WIN32)
614  #pragma pack(pop)
615 #endif
616 
617 //KSZ8895 Ethernet switch driver
618 extern const SwitchDriver ksz8895SwitchDriver;
619 
620 //KSZ8895 related functions
621 error_t ksz8895Init(NetInterface *interface);
622 
623 void ksz8895Tick(NetInterface *interface);
624 
625 void ksz8895EnableIrq(NetInterface *interface);
626 void ksz8895DisableIrq(NetInterface *interface);
627 
628 void ksz8895EventHandler(NetInterface *interface);
629 
630 error_t ksz8895TagFrame(NetInterface *interface, NetBuffer *buffer,
631  size_t *offset, NetTxAncillary *ancillary);
632 
633 error_t ksz8895UntagFrame(NetInterface *interface, uint8_t **frame,
634  size_t *length, NetRxAncillary *ancillary);
635 
636 bool_t ksz8895GetLinkState(NetInterface *interface, uint8_t port);
637 uint32_t ksz8895GetLinkSpeed(NetInterface *interface, uint8_t port);
639 
640 void ksz8895SetPortState(NetInterface *interface, uint8_t port,
641  SwitchPortState state);
642 
644 
645 void ksz8895SetAgingTime(NetInterface *interface, uint32_t agingTime);
646 void ksz8895EnableRsvdMcastTable(NetInterface *interface, bool_t enable);
647 
649  const SwitchFdbEntry *entry);
650 
652  const SwitchFdbEntry *entry);
653 
655  SwitchFdbEntry *entry);
656 
658 
660  SwitchFdbEntry *entry);
661 
662 void ksz8895FlushDynamicFdbTable(NetInterface *interface, uint8_t port);
663 
664 void ksz8895WritePhyReg(NetInterface *interface, uint8_t port,
665  uint8_t address, uint16_t data);
666 
667 uint16_t ksz8895ReadPhyReg(NetInterface *interface, uint8_t port,
668  uint8_t address);
669 
670 void ksz8895DumpPhyReg(NetInterface *interface, uint8_t port);
671 
672 void ksz8895WriteSwitchReg(NetInterface *interface, uint8_t address,
673  uint8_t data);
674 
675 uint8_t ksz8895ReadSwitchReg(NetInterface *interface, uint8_t address);
676 
677 void ksz8895DumpSwitchReg(NetInterface *interface);
678 
679 //C++ guard
680 #ifdef __cplusplus
681 }
682 #endif
683 
684 #endif
uint8_t length
Definition: coap_common.h:190
uint8_t fid
int bool_t
Definition: compiler_port.h:49
uint8_t data[]
Definition: ethernet.h:209
void ksz8895SetAgingTime(NetInterface *interface, uint32_t agingTime)
Set aging time for dynamic filtering entries.
uint32_t reserved
Definition: ipv6.h:318
void ksz8895WriteSwitchReg(NetInterface *interface, uint8_t address, uint8_t data)
Write switch register.
const SwitchDriver ksz8895SwitchDriver
KSZ8895 Ethernet switch driver.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void ksz8895EnableRsvdMcastTable(NetInterface *interface, bool_t enable)
Enable reserved multicast table.
__start_packed struct @5 MacAddr
MAC address.
uint8_t numValidEntriesL
NicDuplexMode ksz8895GetDuplexMode(NetInterface *interface, uint8_t port)
Get duplex mode.
void ksz8895EnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t forwardPorts
uint8_t override
error_t ksz8895Init(NetInterface *interface)
KSZ8895 Ethernet switch initialization.
MacAddr macAddr
uint8_t fid
void ksz8895DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
uint8_t numValidEntriesH
uint8_t ksz8895ReadSwitchReg(NetInterface *interface, uint8_t address)
Read switch register.
void ksz8895EventHandler(NetInterface *interface)
KSZ8895 event handler.
error_t
Error codes.
Definition: error.h:42
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
MacAddr macAddr
void ksz8895DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
#define NetTxAncillary
Definition: net_misc.h:36
SwitchPortState
Switch port state.
Definition: nic.h:130
uint8_t sourcePort
uint8_t forwardPorts
MacAddr macAddr
error_t ksz8895UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, NetRxAncillary *ancillary)
Decode tail tag from incoming Ethernet frame.
uint8_t reserved
void ksz8895WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
void ksz8895SetPortState(NetInterface *interface, uint8_t port, SwitchPortState state)
Set port state.
uint16_t port
Definition: dns_common.h:223
uint8_t fid
Static MAC table entry (read operation)
uint8_t dataNotReady
error_t ksz8895DeleteStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Remove an entry from the static MAC table.
uint8_t valid
Ethernet switch driver.
Definition: nic.h:306
void ksz8895DisableIrq(NetInterface *interface)
Disable interrupts.
Static MAC table entry (write operation)
NicDuplexMode
Duplex mode.
Definition: nic.h:118
Network interface controller abstraction layer.
bool_t ksz8895GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz8895FlushStaticFdbTable(NetInterface *interface)
Flush static MAC table.
uint8_t macEmpty
Ipv6Addr address
error_t ksz8895AddStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Add a new entry to the static MAC table.
uint8_t useFid
uint32_t ksz8895GetLinkSpeed(NetInterface *interface, uint8_t port)
Get link speed.
uint16_t ksz8895ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
unsigned int uint_t
Definition: compiler_port.h:45
uint8_t timestamp
error_t ksz8895GetDynamicFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the dynamic MAC table.
error_t ksz8895TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, NetTxAncillary *ancillary)
Add tail tag to Ethernet frame.
error_t ksz8895GetStaticFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the static MAC table.
void ksz8895Tick(NetInterface *interface)
KSZ8895 timer handler.
Dynamic MAC table entry.
SwitchPortState ksz8895GetPortState(NetInterface *interface, uint8_t port)
Get port state.
Forwarding database entry.
Definition: nic.h:145
uint8_t useFid
void ksz8895FlushDynamicFdbTable(NetInterface *interface, uint8_t port)
Flush dynamic MAC table.
uint8_t override
uint8_t valid