ksz8895_driver.h
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1 /**
2  * @file ksz8895_driver.h
3  * @brief KSZ8895 5-port Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _KSZ8895_DRIVER_H
32 #define _KSZ8895_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ8895 ports
38 #define KSZ8895_PORT1 1
39 #define KSZ8895_PORT2 2
40 #define KSZ8895_PORT3 3
41 #define KSZ8895_PORT4 4
42 
43 //SPI command byte
44 #define KSZ8895_SPI_CMD_WRITE 0x02
45 #define KSZ8895_SPI_CMD_READ 0x03
46 
47 //KSZ8895 PHY registers
48 #define KSZ8895_BMCR 0x00
49 #define KSZ8895_BMSR 0x01
50 #define KSZ8895_PHYID1 0x02
51 #define KSZ8895_PHYID2 0x03
52 #define KSZ8895_ANAR 0x04
53 #define KSZ8895_ANLPAR 0x05
54 #define KSZ8895_LINKMD 0x1D
55 #define KSZ8895_PHYSCS 0x1F
56 
57 //KSZ8895 Switch registers
58 #define KSZ8895_CHIP_ID0 0x00
59 #define KSZ8895_CHIP_ID1 0x01
60 #define KSZ8895_GLOBAL_CTRL0 0x02
61 #define KSZ8895_GLOBAL_CTRL1 0x03
62 #define KSZ8895_GLOBAL_CTRL2 0x04
63 #define KSZ8895_GLOBAL_CTRL3 0x05
64 #define KSZ8895_GLOBAL_CTRL4 0x06
65 #define KSZ8895_GLOBAL_CTRL5 0x07
66 #define KSZ8895_GLOBAL_CTRL6 0x08
67 #define KSZ8895_GLOBAL_CTRL7 0x09
68 #define KSZ8895_GLOBAL_CTRL8 0x0A
69 #define KSZ8895_GLOBAL_CTRL9 0x0B
70 #define KSZ8895_GLOBAL_CTRL10 0x0C
71 #define KSZ8895_GLOBAL_CTRL11 0x0D
72 #define KSZ8895_PD_MGMT_CTRL1 0x0E
73 #define KSZ8895_PD_MGMT_CTRL2 0x0F
74 #define KSZ8895_PORT1_CTRL0 0x10
75 #define KSZ8895_PORT1_CTRL1 0x11
76 #define KSZ8895_PORT1_CTRL2 0x12
77 #define KSZ8895_PORT1_CTRL3 0x13
78 #define KSZ8895_PORT1_CTRL4 0x14
79 #define KSZ8895_PORT1_STAT0 0x19
80 #define KSZ8895_PORT1_PSCS 0x1A
81 #define KSZ8895_PORT1_LINKMD 0x1B
82 #define KSZ8895_PORT1_CTRL5 0x1C
83 #define KSZ8895_PORT1_CTRL6 0x1D
84 #define KSZ8895_PORT1_STAT1 0x1E
85 #define KSZ8895_PORT1_CTRL7_STAT2 0x1F
86 #define KSZ8895_PORT2_CTRL0 0x20
87 #define KSZ8895_PORT2_CTRL1 0x21
88 #define KSZ8895_PORT2_CTRL2 0x22
89 #define KSZ8895_PORT2_CTRL3 0x23
90 #define KSZ8895_PORT2_CTRL4 0x24
91 #define KSZ8895_PORT2_STAT0 0x29
92 #define KSZ8895_PORT2_PSCS 0x2A
93 #define KSZ8895_PORT2_LINKMD 0x2B
94 #define KSZ8895_PORT2_CTRL5 0x2C
95 #define KSZ8895_PORT2_CTRL6 0x2D
96 #define KSZ8895_PORT2_STAT1 0x2E
97 #define KSZ8895_PORT2_CTRL7_STAT2 0x2F
98 #define KSZ8895_PORT3_CTRL0 0x30
99 #define KSZ8895_PORT3_CTRL1 0x31
100 #define KSZ8895_PORT3_CTRL2 0x32
101 #define KSZ8895_PORT3_CTRL3 0x33
102 #define KSZ8895_PORT3_CTRL4 0x34
103 #define KSZ8895_PORT3_STAT0 0x39
104 #define KSZ8895_PORT3_PSCS 0x3A
105 #define KSZ8895_PORT3_LINKMD 0x3B
106 #define KSZ8895_PORT3_CTRL5 0x3C
107 #define KSZ8895_PORT3_CTRL6 0x3D
108 #define KSZ8895_PORT3_STAT1 0x3E
109 #define KSZ8895_PORT3_CTRL7_STAT2 0x3F
110 #define KSZ8895_PORT4_CTRL0 0x40
111 #define KSZ8895_PORT4_CTRL1 0x41
112 #define KSZ8895_PORT4_CTRL2 0x42
113 #define KSZ8895_PORT4_CTRL3 0x43
114 #define KSZ8895_PORT4_CTRL4 0x44
115 #define KSZ8895_PORT4_STAT0 0x49
116 #define KSZ8895_PORT4_PSCS 0x4A
117 #define KSZ8895_PORT4_LINKMD 0x4B
118 #define KSZ8895_PORT4_CTRL5 0x4C
119 #define KSZ8895_PORT4_CTRL6 0x4D
120 #define KSZ8895_PORT4_STAT1 0x4E
121 #define KSZ8895_PORT4_CTRL7_STAT2 0x4F
122 #define KSZ8895_PORT5_CTRL0 0x50
123 #define KSZ8895_PORT5_CTRL1 0x51
124 #define KSZ8895_PORT5_CTRL2 0x52
125 #define KSZ8895_PORT5_CTRL3 0x53
126 #define KSZ8895_PORT5_CTRL4 0x54
127 #define KSZ8895_RMII_MGMT_CTRL 0x57
128 #define KSZ8895_PORT5_STAT0 0x59
129 #define KSZ8895_PORT5_PSCS 0x5A
130 #define KSZ8895_PORT5_LINKMD 0x5B
131 #define KSZ8895_PORT5_CTRL5 0x5C
132 #define KSZ8895_PORT5_CTRL6 0x5D
133 #define KSZ8895_PORT5_STAT1 0x5E
134 #define KSZ8895_PORT5_CTRL7_STAT2 0x5F
135 #define KSZ8895_MAC_ADDR0 0x68
136 #define KSZ8895_MAC_ADDR1 0x69
137 #define KSZ8895_MAC_ADDR2 0x6A
138 #define KSZ8895_MAC_ADDR3 0x6B
139 #define KSZ8895_MAC_ADDR4 0x6C
140 #define KSZ8895_MAC_ADDR5 0x6D
141 #define KSZ8895_IND_ACCESS_CTRL0 0x6E
142 #define KSZ8895_IND_ACCESS_CTRL1 0x6F
143 #define KSZ8895_IND_DATA8 0x70
144 #define KSZ8895_IND_DATA7 0x71
145 #define KSZ8895_IND_DATA6 0x72
146 #define KSZ8895_IND_DATA5 0x73
147 #define KSZ8895_IND_DATA4 0x74
148 #define KSZ8895_IND_DATA3 0x75
149 #define KSZ8895_IND_DATA2 0x76
150 #define KSZ8895_IND_DATA1 0x77
151 #define KSZ8895_IND_DATA0 0x78
152 #define KSZ8895_INT_STAT 0x7C
153 #define KSZ8895_INT_MASK 0x7D
154 #define KSZ8895_GLOBAL_CTRL12 0x80
155 #define KSZ8895_GLOBAL_CTRL13 0x81
156 #define KSZ8895_GLOBAL_CTRL14 0x82
157 #define KSZ8895_GLOBAL_CTRL15 0x83
158 #define KSZ8895_GLOBAL_CTRL16 0x84
159 #define KSZ8895_GLOBAL_CTRL17 0x85
160 #define KSZ8895_GLOBAL_CTRL18 0x86
161 #define KSZ8895_GLOBAL_CTRL19 0x87
162 #define KSZ8895_ID 0x89
163 #define KSZ8895_TOS_PRIO_CTRL0 0x90
164 #define KSZ8895_TOS_PRIO_CTRL1 0x91
165 #define KSZ8895_TOS_PRIO_CTRL2 0x92
166 #define KSZ8895_TOS_PRIO_CTRL3 0x93
167 #define KSZ8895_TOS_PRIO_CTRL4 0x94
168 #define KSZ8895_TOS_PRIO_CTRL5 0x95
169 #define KSZ8895_TOS_PRIO_CTRL6 0x96
170 #define KSZ8895_TOS_PRIO_CTRL7 0x97
171 #define KSZ8895_TOS_PRIO_CTRL8 0x98
172 #define KSZ8895_TOS_PRIO_CTRL9 0x99
173 #define KSZ8895_TOS_PRIO_CTRL10 0x9A
174 #define KSZ8895_TOS_PRIO_CTRL11 0x9B
175 #define KSZ8895_TOS_PRIO_CTRL12 0x9C
176 #define KSZ8895_TOS_PRIO_CTRL13 0x9D
177 #define KSZ8895_TOS_PRIO_CTRL14 0x9E
178 #define KSZ8895_TOS_PRIO_CTRL15 0x9F
179 #define KSZ8895_PORT1_CTRL8 0xB0
180 #define KSZ8895_PORT1_CTRL9 0xB1
181 #define KSZ8895_PORT1_CTRL10 0xB2
182 #define KSZ8895_PORT1_CTRL11 0xB3
183 #define KSZ8895_PORT1_CTRL12 0xB4
184 #define KSZ8895_PORT1_CTRL13 0xB5
185 #define KSZ8895_PORT1_RATE_LIMIT_CTRL 0xB6
186 #define KSZ8895_PORT1_PRIO0_IG_LIMIT_CTRL1 0xB7
187 #define KSZ8895_PORT1_PRIO1_IG_LIMIT_CTRL2 0xB8
188 #define KSZ8895_PORT1_PRIO2_IG_LIMIT_CTRL3 0xB9
189 #define KSZ8895_PORT1_PRIO3_IG_LIMIT_CTRL4 0xBA
190 #define KSZ8895_PORT1_QUEUE0_EG_LIMIT_CTRL1 0xBB
191 #define KSZ8895_PORT1_QUEUE1_EG_LIMIT_CTRL2 0xBC
192 #define KSZ8895_PORT1_QUEUE2_EG_LIMIT_CTRL3 0xBD
193 #define KSZ8895_PORT1_QUEUE3_EG_LIMIT_CTRL4 0xBE
194 #define KSZ8895_TEST1 0xBF
195 #define KSZ8895_PORT2_CTRL8 0xC0
196 #define KSZ8895_PORT2_CTRL9 0xC1
197 #define KSZ8895_PORT2_CTRL10 0xC2
198 #define KSZ8895_PORT2_CTRL11 0xC3
199 #define KSZ8895_PORT2_CTRL12 0xC4
200 #define KSZ8895_PORT2_CTRL13 0xC5
201 #define KSZ8895_PORT2_RATE_LIMIT_CTRL 0xC6
202 #define KSZ8895_PORT2_PRIO0_IG_LIMIT_CTRL1 0xC7
203 #define KSZ8895_PORT2_PRIO1_IG_LIMIT_CTRL2 0xC8
204 #define KSZ8895_PORT2_PRIO2_IG_LIMIT_CTRL3 0xC9
205 #define KSZ8895_PORT2_PRIO3_IG_LIMIT_CTRL4 0xCA
206 #define KSZ8895_PORT2_QUEUE0_EG_LIMIT_CTRL1 0xCB
207 #define KSZ8895_PORT2_QUEUE1_EG_LIMIT_CTRL2 0xCC
208 #define KSZ8895_PORT2_QUEUE2_EG_LIMIT_CTRL3 0xCD
209 #define KSZ8895_PORT2_QUEUE3_EG_LIMIT_CTRL4 0xCE
210 #define KSZ8895_PORT3_CTRL8 0xD0
211 #define KSZ8895_PORT3_CTRL9 0xD1
212 #define KSZ8895_PORT3_CTRL10 0xD2
213 #define KSZ8895_PORT3_CTRL11 0xD3
214 #define KSZ8895_PORT3_CTRL12 0xD4
215 #define KSZ8895_PORT3_CTRL13 0xD5
216 #define KSZ8895_PORT3_RATE_LIMIT_CTRL 0xD6
217 #define KSZ8895_PORT3_PRIO0_IG_LIMIT_CTRL1 0xD7
218 #define KSZ8895_PORT3_PRIO1_IG_LIMIT_CTRL2 0xD8
219 #define KSZ8895_PORT3_PRIO2_IG_LIMIT_CTRL3 0xD9
220 #define KSZ8895_PORT3_PRIO3_IG_LIMIT_CTRL4 0xDA
221 #define KSZ8895_PORT3_QUEUE0_EG_LIMIT_CTRL1 0xDB
222 #define KSZ8895_PORT3_QUEUE1_EG_LIMIT_CTRL2 0xDC
223 #define KSZ8895_PORT3_QUEUE2_EG_LIMIT_CTRL3 0xDD
224 #define KSZ8895_PORT3_QUEUE3_EG_LIMIT_CTRL4 0xDE
225 #define KSZ8895_TEST2 0xDF
226 #define KSZ8895_PORT4_CTRL8 0xE0
227 #define KSZ8895_PORT4_CTRL9 0xE1
228 #define KSZ8895_PORT4_CTRL10 0xE2
229 #define KSZ8895_PORT4_CTRL11 0xE3
230 #define KSZ8895_PORT4_CTRL12 0xE4
231 #define KSZ8895_PORT4_CTRL13 0xE5
232 #define KSZ8895_PORT4_RATE_LIMIT_CTRL 0xE6
233 #define KSZ8895_PORT4_PRIO0_IG_LIMIT_CTRL1 0xE7
234 #define KSZ8895_PORT4_PRIO1_IG_LIMIT_CTRL2 0xE8
235 #define KSZ8895_PORT4_PRIO2_IG_LIMIT_CTRL3 0xE9
236 #define KSZ8895_PORT4_PRIO3_IG_LIMIT_CTRL4 0xEA
237 #define KSZ8895_PORT4_QUEUE0_EG_LIMIT_CTRL1 0xEB
238 #define KSZ8895_PORT4_QUEUE1_EG_LIMIT_CTRL2 0xEC
239 #define KSZ8895_PORT4_QUEUE2_EG_LIMIT_CTRL3 0xED
240 #define KSZ8895_PORT4_QUEUE3_EG_LIMIT_CTRL4 0xEE
241 #define KSZ8895_PORT3_COPPER_FIBER_CTRL 0xEF
242 #define KSZ8895_PORT5_CTRL8 0xF0
243 #define KSZ8895_PORT5_CTRL9 0xF1
244 #define KSZ8895_PORT5_CTRL10 0xF2
245 #define KSZ8895_PORT5_CTRL11 0xF3
246 #define KSZ8895_PORT5_CTRL12 0xF4
247 #define KSZ8895_PORT5_CTRL13 0xF5
248 #define KSZ8895_PORT5_RATE_LIMIT_CTRL 0xF6
249 #define KSZ8895_PORT5_PRIO0_IG_LIMIT_CTRL1 0xF7
250 #define KSZ8895_PORT5_PRIO1_IG_LIMIT_CTRL2 0xF8
251 #define KSZ8895_PORT5_PRIO2_IG_LIMIT_CTRL3 0xF9
252 #define KSZ8895_PORT5_PRIO3_IG_LIMIT_CTRL4 0xFA
253 #define KSZ8895_PORT5_QUEUE0_EG_LIMIT_CTRL1 0xFB
254 #define KSZ8895_PORT5_QUEUE1_EG_LIMIT_CTRL2 0xFC
255 #define KSZ8895_PORT5_QUEUE2_EG_LIMIT_CTRL3 0xFD
256 #define KSZ8895_PORT5_QUEUE3_EG_LIMIT_CTRL4 0xFE
257 #define KSZ8895_TEST3 0xFF
258 
259 //KSZ8895 Switch register access macros
260 #define KSZ8895_PORTn_CTRL0(port) (0x00 + ((port) * 0x10))
261 #define KSZ8895_PORTn_CTRL1(port) (0x01 + ((port) * 0x10))
262 #define KSZ8895_PORTn_CTRL2(port) (0x02 + ((port) * 0x10))
263 #define KSZ8895_PORTn_CTRL3(port) (0x03 + ((port) * 0x10))
264 #define KSZ8895_PORTn_CTRL4(port) (0x04 + ((port) * 0x10))
265 #define KSZ8895_PORTn_STAT0(port) (0x09 + ((port) * 0x10))
266 #define KSZ8895_PORTn_PSCS(port) (0x0A + ((port) * 0x10))
267 #define KSZ8895_PORTn_LINKMD(port) (0x0B + ((port) * 0x10))
268 #define KSZ8895_PORTn_CTRL5(port) (0x0C + ((port) * 0x10))
269 #define KSZ8895_PORTn_CTRL6(port) (0x0D + ((port) * 0x10))
270 #define KSZ8895_PORTn_STAT1(port) (0x0E + ((port) * 0x10))
271 #define KSZ8895_PORTn_CTRL7_STAT2(port) (0x0F + ((port) * 0x10))
272 #define KSZ8895_PORTn_CTRL8(port) (0xA0 + ((port) * 0x10))
273 #define KSZ8895_PORTn_CTRL9(port) (0xA1 + ((port) * 0x10))
274 #define KSZ8895_PORTn_CTRL10(port) (0xA2 + ((port) * 0x10))
275 #define KSZ8895_PORTn_CTRL11(port) (0xA3 + ((port) * 0x10))
276 #define KSZ8895_PORTn_CTRL12(port) (0xA4 + ((port) * 0x10))
277 #define KSZ8895_PORTn_CTRL13(port) (0xA5 + ((port) * 0x10))
278 #define KSZ8895_PORTn_RATE_LIMIT_CTRL(port) (0xA6 + ((port) * 0x10))
279 #define KSZ8895_PORTn_PRIO0_IG_LIMIT_CTRL1(port) (0xA7 + ((port) * 0x10))
280 #define KSZ8895_PORTn_PRIO1_IG_LIMIT_CTRL2(port) (0xA8 + ((port) * 0x10))
281 #define KSZ8895_PORTn_PRIO2_IG_LIMIT_CTRL3(port) (0xA9 + ((port) * 0x10))
282 #define KSZ8895_PORTn_PRIO3_IG_LIMIT_CTRL4(port) (0xAA + ((port) * 0x10))
283 #define KSZ8895_PORTn_QUEUE0_EG_LIMIT_CTRL1(port) (0xAB + ((port) * 0x10))
284 #define KSZ8895_PORTn_QUEUE1_EG_LIMIT_CTRL2(port) (0xAC + ((port) * 0x10))
285 #define KSZ8895_PORTn_QUEUE2_EG_LIMIT_CTRL3(port) (0xAD + ((port) * 0x10))
286 #define KSZ8895_PORTn_QUEUE3_EG_LIMIT_CTRL4(port) (0xAE + ((port) * 0x10))
287 
288 //MII Control register
289 #define KSZ8895_BMCR_RESET 0x8000
290 #define KSZ8895_BMCR_LOOPBACK 0x4000
291 #define KSZ8895_BMCR_FORCE_100 0x2000
292 #define KSZ8895_BMCR_AN_EN 0x1000
293 #define KSZ8895_BMCR_POWER_DOWN 0x0800
294 #define KSZ8895_BMCR_ISOLATE 0x0400
295 #define KSZ8895_BMCR_RESTART_AN 0x0200
296 #define KSZ8895_BMCR_FORCE_FULL_DUPLEX 0x0100
297 #define KSZ8895_BMCR_COL_TEST 0x0080
298 #define KSZ8895_BMCR_HP_MDIX 0x0020
299 #define KSZ8895_BMCR_FORCE_MDI 0x0010
300 #define KSZ8895_BMCR_AUTO_MDIX_DIS 0x0008
301 #define KSZ8895_BMCR_FAR_END_FAULT_DIS 0x0004
302 #define KSZ8895_BMCR_TRANSMIT_DIS 0x0002
303 #define KSZ8895_BMCR_LED_DIS 0x0001
304 
305 //MII Status register
306 #define KSZ8895_BMSR_100BT4 0x8000
307 #define KSZ8895_BMSR_100BTX_FD 0x4000
308 #define KSZ8895_BMSR_100BTX_HD 0x2000
309 #define KSZ8895_BMSR_10BT_FD 0x1000
310 #define KSZ8895_BMSR_10BT_HD 0x0800
311 #define KSZ8895_BMSR_PREAMBLE_SUPPR 0x0040
312 #define KSZ8895_BMSR_AN_COMPLETE 0x0020
313 #define KSZ8895_BMSR_FAR_END_FAULT 0x0010
314 #define KSZ8895_BMSR_AN_CAPABLE 0x0008
315 #define KSZ8895_BMSR_LINK_STATUS 0x0004
316 #define KSZ8895_BMSR_JABBER_TEST 0x0002
317 #define KSZ8895_BMSR_EXTENDED_CAPABLE 0x0001
318 
319 //PHYID High register
320 #define KSZ8895_PHYID1_DEFAULT 0x0022
321 
322 //PHYID Low register
323 #define KSZ8895_PHYID2_DEFAULT 0x1450
324 
325 //Advertisement Ability register
326 #define KSZ8895_ANAR_NEXT_PAGE 0x8000
327 #define KSZ8895_ANAR_REMOTE_FAULT 0x2000
328 #define KSZ8895_ANAR_PAUSE 0x0400
329 #define KSZ8895_ANAR_100BTX_FD 0x0100
330 #define KSZ8895_ANAR_100BTX_HD 0x0080
331 #define KSZ8895_ANAR_10BT_FD 0x0040
332 #define KSZ8895_ANAR_10BT_HD 0x0020
333 #define KSZ8895_ANAR_SELECTOR 0x001F
334 #define KSZ8895_ANAR_SELECTOR_DEFAULT 0x0001
335 
336 //Link Partner Ability register
337 #define KSZ8895_ANLPAR_NEXT_PAGE 0x8000
338 #define KSZ8895_ANLPAR_LP_ACK 0x4000
339 #define KSZ8895_ANLPAR_REMOTE_FAULT 0x2000
340 #define KSZ8895_ANLPAR_PAUSE 0x0400
341 #define KSZ8895_ANLPAR_100BTX_FD 0x0100
342 #define KSZ8895_ANLPAR_100BTX_HD 0x0080
343 #define KSZ8895_ANLPAR_10BT_FD 0x0040
344 #define KSZ8895_ANLPAR_10BT_HD 0x0020
345 
346 //LinkMD Control/Status register
347 #define KSZ8895_LINKMD_TEST_EN 0x8000
348 #define KSZ8895_LINKMD_RESULT 0x6000
349 #define KSZ8895_LINKMD_SHORT 0x1000
350 #define KSZ8895_LINKMD_FAULT_COUNT 0x01FF
351 
352 //PHY Special Control/Status register
353 #define KSZ8895_PHYSCS_OP_MODE 0x0700
354 #define KSZ8895_PHYSCS_OP_MODE_AN 0x0100
355 #define KSZ8895_PHYSCS_OP_MODE_10BT_HD 0x0200
356 #define KSZ8895_PHYSCS_OP_MODE_100BTX_HD 0x0300
357 #define KSZ8895_PHYSCS_OP_MODE_10BT_FD 0x0500
358 #define KSZ8895_PHYSCS_OP_MODE_100BTX_FD 0x0600
359 #define KSZ8895_PHYSCS_OP_MODE_ISOLATE 0x0700
360 #define KSZ8895_PHYSCS_POLRVS 0x0020
361 #define KSZ8895_PHYSCS_MDIX_STATUS 0x0010
362 #define KSZ8895_PHYSCS_FORCE_LINK 0x0008
363 #define KSZ8895_PHYSCS_PWRSAVE 0x0004
364 #define KSZ8895_PHYSCS_REMOTE_LOOPBACK 0x0002
365 
366 //Chip ID0 register
367 #define KSZ8895_CHIP_ID0_FAMILY_ID 0xFF
368 #define KSZ8895_CHIP_ID0_FAMILY_ID_DEFAULT 0x95
369 
370 //Chip ID1 / Start Switch register
371 #define KSZ8895_CHIP_ID1_CHIP_ID 0xF0
372 #define KSZ8895_CHIP_ID1_CHIP_ID_MQX_FQX_MLX 0x40
373 #define KSZ8895_CHIP_ID1_CHIP_ID_RQX 0x60
374 #define KSZ8895_CHIP_ID1_REVISION_ID 0x0E
375 #define KSZ8895_CHIP_ID1_START_SWITCH 0x01
376 
377 //Global Control 10 register
378 #define KSZ8895_GLOBAL_CTRL10_CLK_MODE 0x40
379 #define KSZ8895_GLOBAL_CTRL10_CPU_CLK_SEL 0x30
380 #define KSZ8895_GLOBAL_CTRL10_RESTORE_PREAMBLE_EN 0x04
381 #define KSZ8895_GLOBAL_CTRL10_TAIL_TAG_EN 0x02
382 #define KSZ8895_GLOBAL_CTRL10_PASS_FLOW_CTRL_PKT 0x01
383 
384 //Port N Control 0 register
385 #define KSZ8895_PORTn_CTRL0_BCAST_STORM_PROTECT_EN 0x80
386 #define KSZ8895_PORTn_CTRL0_DIFFSERV_PRIO_CLASS_EN 0x40
387 #define KSZ8895_PORTn_CTRL0_802_1P_PRIO_CLASS_EN 0x20
388 #define KSZ8895_PORTn_CTRL0_PORT_PRIO_CLASS_EN 0x18
389 #define KSZ8895_PORTn_CTRL0_TAG_INSERTION 0x04
390 #define KSZ8895_PORTn_CTRL0_TAG_REMOVAL 0x02
391 #define KSZ8895_PORTn_CTRL0_TWO_QUEUE_SPLIT_EN 0x01
392 
393 //Port N Control 1 register
394 #define KSZ8895_PORTn_CTRL1_SNIFFER_PORT 0x80
395 #define KSZ8895_PORTn_CTRL1_RECEIVE_SNIFF 0x40
396 #define KSZ8895_PORTn_CTRL1_TRANSMIT_SNIFF 0x20
397 #define KSZ8895_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x1F
398 
399 //Port N Control 2 register
400 #define KSZ8895_PORTn_CTRL2_USER_PRIO_CEILING 0x80
401 #define KSZ8895_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
402 #define KSZ8895_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
403 #define KSZ8895_PORTn_CTRL2_FORCE_FLOW_CTRL 0x10
404 #define KSZ8895_PORTn_CTRL2_BACK_PRESSURE_EN 0x08
405 #define KSZ8895_PORTn_CTRL2_TRANSMIT_EN 0x04
406 #define KSZ8895_PORTn_CTRL2_RECEIVE_EN 0x02
407 #define KSZ8895_PORTn_CTRL2_LEARNING_DIS 0x01
408 
409 //Port N Control 3 register
410 #define KSZ8895_PORTn_CTRL3_DEFAULT_USER_PRIO 0xE0
411 #define KSZ8895_PORTn_CTRL3_DEFAULT_CFI 0x10
412 #define KSZ8895_PORTn_CTRL3_DEFAULT_VID_MSB 0x0F
413 
414 //Port N Control 4 register
415 #define KSZ8895_PORTn_CTRL4_DEFAULT_VID_LSB 0xFF
416 
417 //RMII Management Control register
418 #define KSZ8895_RMII_MGMT_CTRL_SW5_CLK_OUT_DIS 0x08
419 #define KSZ8895_RMII_MGMT_CTRL_P5_CLK_OUT_DIS 0x04
420 
421 //Port N Status 0 register
422 #define KSZ8895_PORTn_STAT0_HP_MDIX 0x80
423 #define KSZ8895_PORTn_STAT0_POLRVS 0x20
424 #define KSZ8895_PORTn_STAT0_TX_FLOW_CTRL_EN 0x10
425 #define KSZ8895_PORTn_STAT0_RX_FLOW_CTRL_EN 0x08
426 #define KSZ8895_PORTn_STAT0_OP_SPEED 0x04
427 #define KSZ8895_PORTn_STAT0_OP_DUPLEX 0x02
428 
429 //Port N PHY Special Control/Status register
430 #define KSZ8895_PORTn_PSCS_VCT_10M_SHORT 0x80
431 #define KSZ8895_PORTn_PSCS_VCT_RESULT 0x60
432 #define KSZ8895_PORTn_PSCS_VCT_EN 0x10
433 #define KSZ8895_PORTn_PSCS_FORCE_LNK 0x08
434 #define KSZ8895_PORTn_PSCS_PWRSAVE 0x04
435 #define KSZ8895_PORTn_PSCS_REMOTE_LOOPBACK 0x02
436 #define KSZ8895_PORTn_PSCS_VCT_FAULT_COUNT_MSB 0x01
437 
438 //Port N LinkMD Result register
439 #define KSZ8895_PORTn_LINKMD_VCT_FAULT_COUNT_LSB 0xFF
440 
441 //Port N Status 1 register
442 #define KSZ8895_PORTn_STAT1_MDIX_STATUS 0x80
443 #define KSZ8895_PORTn_STAT1_AN_DONE 0x40
444 #define KSZ8895_PORTn_STAT1_LINK_GOOD 0x20
445 #define KSZ8895_PORTn_STAT1_LP_FLOW_CTRL_CAPABLE 0x10
446 #define KSZ8895_PORTn_STAT1_LP_100BTX_FD_CAPABLE 0x08
447 #define KSZ8895_PORTn_STAT1_LP_100BTX_HF_CAPABLE 0x04
448 #define KSZ8895_PORTn_STAT1_LP_10BT_FD_CAPABLE 0x02
449 #define KSZ8895_PORTn_STAT1_LP_10BT_HD_CAPABLE 0x01
450 
451 //Port N Control 7 / Status 2 register
452 #define KSZ8895_PORTn_CTRL7_STAT2_PHY_LOOPBACK 0x80
453 #define KSZ8895_PORTn_CTRL7_STAT2_PHY_ISOLATE 0x20
454 #define KSZ8895_PORTn_CTRL7_STAT2_SOFT_RESET 0x10
455 #define KSZ8895_PORTn_CTRL7_STAT2_FORCE_LINK 0x08
456 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE 0x07
457 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_AN 0x01
458 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_10BT_HD 0x02
459 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_100BTX_HD 0x03
460 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_10BT_FD 0x05
461 #define KSZ8895_PORTn_CTRL7_STAT2_OP_MODE_100BTX_FD 0x06
462 
463 //Identification register
464 #define KSZ8895_ID_REVISION_ID 0xF0
465 #define KSZ8895_ID_REVISION_ID_MQX_RQX_FQX_REV_A2 0x40
466 #define KSZ8895_ID_REVISION_ID_ML_REV_B2 0x40
467 #define KSZ8895_ID_REVISION_ID_MQX_RQX_FQX_REV_A3 0x50
468 #define KSZ8895_ID_REVISION_ID_ML_REV_B3 0x50
469 #define KSZ8895_ID_REVISION_ID_MQX_RQX_FQX_REV_A4 0x60
470 
471 //Tail tag encoding
472 #define KSZ8895_TAIL_TAG_ENCODE(port) (0x40 | (1 << (((port) - 1) & 0x03)))
473 //Tail tag decoding
474 #define KSZ8895_TAIL_TAG_DECODE(tag) (((tag) & 0x03) + 1)
475 
476 //C++ guard
477 #ifdef __cplusplus
478 extern "C" {
479 #endif
480 
481 //KSZ8895 Ethernet switch driver
482 extern const PhyDriver ksz8895PhyDriver;
483 
484 //KSZ8895 related functions
485 error_t ksz8895Init(NetInterface *interface);
486 
487 bool_t ksz8895GetLinkState(NetInterface *interface, uint8_t port);
488 
489 void ksz8895Tick(NetInterface *interface);
490 
491 void ksz8895EnableIrq(NetInterface *interface);
492 void ksz8895DisableIrq(NetInterface *interface);
493 
494 void ksz8895EventHandler(NetInterface *interface);
495 
496 error_t ksz8895TagFrame(NetInterface *interface, NetBuffer *buffer,
497  size_t *offset, uint8_t port, uint16_t *type);
498 
499 error_t ksz8895UntagFrame(NetInterface *interface, uint8_t **frame,
500  size_t *length, uint8_t *port);
501 
502 void ksz8895WritePhyReg(NetInterface *interface, uint8_t port,
503  uint8_t address, uint16_t data);
504 
505 uint16_t ksz8895ReadPhyReg(NetInterface *interface, uint8_t port,
506  uint8_t address);
507 
508 void ksz8895DumpPhyReg(NetInterface *interface, uint8_t port);
509 
510 void ksz8895WriteSwitchReg(NetInterface *interface, uint8_t address,
511  uint8_t data);
512 
513 uint8_t ksz8895ReadSwitchReg(NetInterface *interface, uint8_t address);
514 
515 void ksz8895DumpSwitchReg(NetInterface *interface);
516 
517 //C++ guard
518 #ifdef __cplusplus
519 }
520 #endif
521 
522 #endif
error_t ksz8895TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
uint8_t length
Definition: dtls_misc.h:149
int bool_t
Definition: compiler_port.h:49
const PhyDriver ksz8895PhyDriver
KSZ8895 Ethernet switch driver.
void ksz8895WriteSwitchReg(NetInterface *interface, uint8_t address, uint8_t data)
Write switch register.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t ksz8895UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
PHY driver.
Definition: nic.h:214
void ksz8895EnableIrq(NetInterface *interface)
Enable interrupts.
error_t ksz8895Init(NetInterface *interface)
KSZ8895 Ethernet switch initialization.
void ksz8895DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
char_t type
uint8_t ksz8895ReadSwitchReg(NetInterface *interface, uint8_t address)
Read switch register.
void ksz8895EventHandler(NetInterface *interface)
KSZ8895 event handler.
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
void ksz8895DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
void ksz8895WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
uint16_t port
Definition: dns_common.h:223
void ksz8895DisableIrq(NetInterface *interface)
Disable interrupts.
Network interface controller abstraction layer.
bool_t ksz8895GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
Ipv6Addr address
uint16_t ksz8895ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
uint8_t data[]
Definition: dtls_misc.h:176
void ksz8895Tick(NetInterface *interface)
KSZ8895 timer handler.