lpc175x_eth_driver.h
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1 /**
2  * @file lpc175x_eth_driver.h
3  * @brief LPC1758 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _LPC175X_ETH_DRIVER_H
30 #define _LPC175X_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef LPC175X_ETH_TX_BUFFER_COUNT
37  #define LPC175X_ETH_TX_BUFFER_COUNT 2
38 #elif (LPC175X_ETH_TX_BUFFER_COUNT < 1)
39  #error LPC175X_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef LPC175X_ETH_TX_BUFFER_SIZE
44  #define LPC175X_ETH_TX_BUFFER_SIZE 1536
45 #elif (LPC175X_ETH_TX_BUFFER_SIZE != 1536)
46  #error LPC175X_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef LPC175X_ETH_RX_BUFFER_COUNT
51  #define LPC175X_ETH_RX_BUFFER_COUNT 4
52 #elif (LPC175X_ETH_RX_BUFFER_COUNT < 1)
53  #error LPC175X_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef LPC175X_ETH_RX_BUFFER_SIZE
58  #define LPC175X_ETH_RX_BUFFER_SIZE 1536
59 #elif (LPC175X_ETH_RX_BUFFER_SIZE != 1536)
60  #error LPC175X_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Interrupt priority grouping
64 #ifndef LPC175X_ETH_IRQ_PRIORITY_GROUPING
65  #define LPC175X_ETH_IRQ_PRIORITY_GROUPING 2
66 #elif (LPC175X_ETH_IRQ_PRIORITY_GROUPING < 0)
67  #error LPC175X_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
68 #endif
69 
70 //Ethernet interrupt group priority
71 #ifndef LPC175X_ETH_IRQ_GROUP_PRIORITY
72  #define LPC175X_ETH_IRQ_GROUP_PRIORITY 24
73 #elif (LPC175X_ETH_IRQ_GROUP_PRIORITY < 0)
74  #error LPC175X_ETH_IRQ_GROUP_PRIORITY parameter is not valid
75 #endif
76 
77 //Ethernet interrupt subpriority
78 #ifndef LPC175X_ETH_IRQ_SUB_PRIORITY
79  #define LPC175X_ETH_IRQ_SUB_PRIORITY 0
80 #elif (LPC175X_ETH_IRQ_SUB_PRIORITY < 0)
81  #error LPC175X_ETH_IRQ_SUB_PRIORITY parameter is not valid
82 #endif
83 
84 //MDC pin
85 #ifndef LPC175X_ETH_MDC_GPIO
86  #define LPC175X_ETH_MDC_GPIO LPC_GPIO2
87 #endif
88 
89 #ifndef LPC175X_ETH_MDC_MASK
90  #define LPC175X_ETH_MDC_MASK (1 << 8)
91 #endif
92 
93 //MDIO pin
94 #ifndef LPC175X_ETH_MDIO_GPIO
95  #define LPC175X_ETH_MDIO_GPIO LPC_GPIO2
96 #endif
97 
98 #ifndef LPC175X_ETH_MDIO_MASK
99  #define LPC175X_ETH_MDIO_MASK (1 << 9)
100 #endif
101 
102 //MAC1 register
103 #define MAC1_SOFT_RESET 0x00008000
104 #define MAC1_SIMULATION_RESET 0x00004000
105 #define MAC1_RESET_MCS_RX 0x00000800
106 #define MAC1_RESET_RX 0x00000400
107 #define MAC1_RESET_MCS_TX 0x00000200
108 #define MAC1_RESET_TX 0x00000100
109 #define MAC1_LOOPBACK 0x00000010
110 #define MAC1_TX_FLOW_CONTROL 0x00000008
111 #define MAC1_RX_FLOW_CONTROL 0x00000004
112 #define MAC1_PASS_ALL_FRAMES 0x00000002
113 #define MAC1_RECEIVE_ENABLE 0x00000001
114 
115 //MAC2 register
116 #define MAC2_EXCESS_DEFER 0x00004000
117 #define MAC2_BACK_PRESSURE_NO_BACKOFF 0x00002000
118 #define MAC2_NO_BACKOFF 0x00001000
119 #define MAC2_LONG_PREAMBLE_ENFORCEMENT 0x00000200
120 #define MAC2_PURE_PREAMBLE_ENFORCEMENT 0x00000100
121 #define MAC2_AUTO_DETECT_PAD_ENABLE 0x00000080
122 #define MAC2_VLAN_PAD_ENABLE 0x00000040
123 #define MAC2_PAD_CRC_ENABLE 0x00000020
124 #define MAC2_CRC_ENABLE 0x00000010
125 #define MAC2_DELAYED_CRC 0x00000008
126 #define MAC2_HUGE_FRAME_ENABLE 0x00000004
127 #define MAC2_FRAME_LENGTH_CHECKING 0x00000002
128 #define MAC2_FULL_DUPLEX 0x00000001
129 
130 //IPGT register
131 #define IPGT_BACK_TO_BACK_IPG 0x0000007F
132 #define IPGT_HALF_DUPLEX 0x00000012
133 #define IPGT_FULL_DUPLEX 0x00000015
134 
135 //IPGR register
136 #define IPGR_NON_BACK_TO_BACK_IPG1 0x00007F00
137 #define IPGR_NON_BACK_TO_BACK_IPG2 0x0000007F
138 #define IPGR_DEFAULT_VALUE 0x00000C12
139 
140 //CLRT register
141 #define CLRT_COLLISION_WINDOW 0x00003F00
142 #define CLRT_RETRANSMISSION_MAXIMUM 0x00003F00
143 #define CLRT_DEFAULT_VALUE 0x0000370F
144 
145 //MAXF register
146 #define MAXF_MAXIMUM_FRAME_LENGTH 0x0000FFFF
147 
148 //SUPP register
149 #define SUPP_SPEED 0x00000100
150 
151 //TEST register
152 #define TEST_BACKPRESSURE 0x00000004
153 #define TEST_PAUSE 0x00000002
154 #define TEST_SHORTCUT_PAUSE_QUANTA 0x00000001
155 
156 //MCFG register
157 #define MCFG_RESET_MII_MGMT 0x00008000
158 #define MCFG_CLOCK SELECT 0x0000003C
159 #define MCFG_SUPPRESS_PREAMBLE 0x00000002
160 #define MCFG_SCAN_INCREMENT 0x00000001
161 
162 #define MCFG_CLOCK_SELECT_DIV4 0x00000000
163 #define MCFG_CLOCK_SELECT_DIV6 0x00000008
164 #define MCFG_CLOCK_SELECT_DIV8 0x0000000C
165 #define MCFG_CLOCK_SELECT_DIV10 0x00000010
166 #define MCFG_CLOCK_SELECT_DIV14 0x00000014
167 #define MCFG_CLOCK_SELECT_DIV20 0x00000018
168 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
169 #define MCFG_CLOCK_SELECT_DIV36 0x00000020
170 #define MCFG_CLOCK_SELECT_DIV40 0x00000024
171 #define MCFG_CLOCK_SELECT_DIV44 0x00000028
172 #define MCFG_CLOCK_SELECT_DIV48 0x0000002C
173 #define MCFG_CLOCK_SELECT_DIV52 0x00000030
174 #define MCFG_CLOCK_SELECT_DIV56 0x00000034
175 #define MCFG_CLOCK_SELECT_DIV60 0x00000038
176 #define MCFG_CLOCK_SELECT_DIV64 0x0000003C
177 
178 //MCMD register
179 #define MCMD_SCAN 0x00000002
180 #define MCMD_READ 0x00000001
181 
182 //MADR register
183 #define MADR_PHY_ADDRESS 0x00001F00
184 #define MADR_REGISTER_ADDRESS 0x0000001F
185 
186 //MWTD register
187 #define MWTD_WRITE_DATA 0x0000FFFF
188 
189 //MRDD register
190 #define MRDD_READ_DATA 0x0000FFFF
191 
192 //MIND register
193 #define MIND_MII_LINK_FAIL 0x00000008
194 #define MIND_NOT_VALID 0x00000004
195 #define MIND_SCANNING 0x00000002
196 #define MIND_BUSY 0x00000001
197 
198 //Command register
199 #define COMMAND_FULL_DUPLEX 0x00000400
200 #define COMMAND_RMII 0x00000200
201 #define COMMAND_TX_FLOW_CONTROL 0x00000100
202 #define COMMAND_PASS_RX_FILTER 0x00000080
203 #define COMMAND_PASS_RUNT_FRAME 0x00000040
204 #define COMMAND_RX_RESET 0x00000020
205 #define COMMAND_TX_RESET 0x00000010
206 #define COMMAND_REG_RESET 0x00000008
207 #define COMMAND_TX_ENABLE 0x00000002
208 #define COMMAND_RX_ENABLE 0x00000001
209 
210 //Status register
211 #define STATUS_TX 0x00000002
212 #define STATUS_RX 0x00000001
213 
214 //TSV0 register
215 #define TSV0_VLAN 0x80000000
216 #define TSV0_BACKPRESSURE 0x40000000
217 #define TSV0_PAUSE 0x20000000
218 #define TSV0_CONTROL_FRAME 0x10000000
219 #define TSV0_TOTAL_BYTES 0x0FFFF000
220 #define TSV0_UNDERRUN 0x00000800
221 #define TSV0_GIANT 0x00000400
222 #define TSV0_LATE_COLLISION 0x00000200
223 #define TSV0_EXCESSIVE_COLLISION 0x00000100
224 #define TSV0_EXCESSIVE_DEFER 0x00000080
225 #define TSV0_PACKET_DEFER 0x00000040
226 #define TSV0_BROADCAST 0x00000020
227 #define TSV0_MULTICAST 0x00000010
228 #define TSV0_DONE 0x00000008
229 #define TSV0_LENGTH_OUT_OF_RANGE 0x00000004
230 #define TSV0_LENGTH_CHECK_ERROR 0x00000002
231 #define TSV0_CRC_ERROR 0x00000001
232 
233 //TSV1 register
234 #define TSV1_TRANSMIT_COLLISION_COUNT 0x000F0000
235 #define TSV1_TRANSMIT_BYTE_COUNT 0x0000FFFF
236 
237 //RSV register
238 #define RSV_VLAN 0x40000000
239 #define RSV_UNSUPPORTED_OPCODE 0x20000000
240 #define RSV_PAUSE 0x10000000
241 #define RSV_CONTROL_FRAME 0x08000000
242 #define RSV_DRIBBLE_NIBBLE 0x04000000
243 #define RSV_BROADCAST 0x02000000
244 #define RSV_MULTICAST 0x01000000
245 #define RSV_RECEIVE_OK 0x00800000
246 #define RSV_LENGTH_OUT_OF_RANGE 0x00400000
247 #define RSV_LENGTH_CHECK_ERROR 0x00200000
248 #define RSV_CRC_ERROR 0x00100000
249 #define RSV_RECEIVE_CODE_VIOLATION 0x00080000
250 #define RSV_CARRIER_EVENT_PREV_SEEN 0x00040000
251 #define RSV_RXDV_EVENT_PREV_SEEN 0x00020000
252 #define RSV_PACKET_PREVIOUSLY_IGNORED 0x00010000
253 #define RSV_RECEIVED_BYTE_COUNT 0x0000FFFF
254 
255 //FlowControlCounter register
256 #define FCC_PAUSE_TIMER 0xFFFF0000
257 #define FCC_MIRROR_COUNTER 0x0000FFFF
258 
259 //FlowControlStatus register
260 #define FCS_MIRROR_COUNTER_CURRENT 0x0000FFFF
261 
262 //RxFilterCtrl register
263 #define RFC_RX_FILTER_EN_WOL 0x00002000
264 #define RFC_MAGIC_PACKET_EN_WOL 0x00001000
265 #define RFC_ACCEPT_PERFECT_EN 0x00000020
266 #define RFC_ACCEPT_MULTICAST_HASH_EN 0x00000010
267 #define RFC_ACCEPT_UNICAST_HASH_EN 0x00000008
268 #define RFC_ACCEPT_MULTICAST_EN 0x00000004
269 #define RFC_ACCEPT_BROADCAST_EN 0x00000002
270 #define RFC_ACCEPT_UNICAST_EN 0x00000001
271 
272 //RxFilterWoLStatus and RxFilterWoLClear registers
273 #define RFWS_MAGIC_PACKET_WOL 0x00000100
274 #define RFWS_RX_FILTER_WOL 0x00000080
275 #define RFWS_ACCEPT_PERFECT_WOL 0x00000020
276 #define RFWS_ACCEPT_MULTICAST_HASH_WOL 0x00000010
277 #define RFWS_ACCEPT_UNICAST_HASH_WOL 0x00000008
278 #define RFWS_ACCEPT_MULTICAST_WOL 0x00000004
279 #define RFWS_ACCEPT_BROADCAST_WOL 0x00000002
280 #define RFWS_ACCEPT_UNICAST_WOL 0x00000001
281 
282 //IntStatus, IntEnable, IntClear and IntSet registers
283 #define INT_WAKEUP 0x00002000
284 #define INT_SOFT_INT 0x00001000
285 #define INT_TX_DONE 0x00000080
286 #define INT_TX_FINISHED 0x00000040
287 #define INT_TX_ERROR 0x00000020
288 #define INT_TX_UNDERRUN 0x00000010
289 #define INT_RX_DONE 0x00000008
290 #define INT_RX_FINISHED 0x00000004
291 #define INT_RX_ERROR 0x00000002
292 #define INT_RX_OVERRUN 0x00000001
293 
294 //Transmit descriptor control word
295 #define TX_CTRL_INTERRUPT 0x80000000
296 #define TX_CTRL_LAST 0x40000000
297 #define TX_CTRL_CRC 0x20000000
298 #define TX_CTRL_PAD 0x10000000
299 #define TX_CTRL_HUGE 0x08000000
300 #define TX_CTRL_OVERRIDE 0x04000000
301 #define TX_CTRL_SIZE 0x000007FF
302 
303 //Transmit status information word
304 #define TX_STATUS_ERROR 0x80000000
305 #define TX_STATUS_NO_DESCRIPTOR 0x40000000
306 #define TX_STATUS_UNDERRUN 0x20000000
307 #define TX_STATUS_LATE_COLLISION 0x10000000
308 #define TX_STATUS_EXCESSIVE_COLLISION 0x08000000
309 #define TX_STATUS_EXCESSIVE_DEFER 0x04000000
310 #define TX_STATUS_DEFER 0x02000000
311 #define TX_STATUS_COLLISION_COUNT 0x01E00000
312 
313 //Receive descriptor control word
314 #define RX_CTRL_INTERRUPT 0x80000000
315 #define RX_CTRL_SIZE 0x000007FF
316 
317 //Receive status information word
318 #define RX_STATUS_ERROR 0x80000000
319 #define RX_STATUS_LAST_FLAG 0x40000000
320 #define RX_STATUS_NO_DESCRIPTOR 0x20000000
321 #define RX_STATUS_OVERRUN 0x10000000
322 #define RX_STATUS_ALIGNMENT_ERROR 0x08000000
323 #define RX_STATUS_RANGE_ERROR 0x04000000
324 #define RX_STATUS_LENGTH_ERROR 0x02000000
325 #define RX_STATUS_SYMBOL_ERROR 0x01000000
326 #define RX_STATUS_CRC_ERROR 0x00800000
327 #define RX_STATUS_BROADCAST 0x00400000
328 #define RX_STATUS_MULTICAST 0x00200000
329 #define RX_STATUS_FAIL_FILTER 0x00100000
330 #define RX_STATUS_VLAN 0x00080000
331 #define RX_STATUS_CONTROL_FRAME 0x00040000
332 #define RX_STATUS_SIZE 0x000007FF
333 
334 //Receive status HashCRC word
335 #define RX_HASH_CRC_DA 0x001FF000
336 #define RX_HASH_CRC_SA 0x000001FF
337 
338 //Serial Management Interface
339 #define SMI_SYNC 0xFFFFFFFF
340 #define SMI_START 0x00000001
341 #define SMI_WRITE 0x00000001
342 #define SMI_READ 0x00000002
343 #define SMI_TA 0x00000002
344 
345 //C++ guard
346 #ifdef __cplusplus
347  extern "C" {
348 #endif
349 
350 
351 /**
352  * @brief Transmit descriptor
353  **/
354 
355 typedef struct
356 {
357  uint32_t packet;
358  uint32_t control;
359 } Lpc175xTxDesc;
360 
361 
362 /**
363  * @brief Transmit status
364  **/
365 
366 typedef struct
367 {
368  uint32_t info;
370 
371 
372 /**
373  * @brief Receive descriptor
374  **/
375 
376 typedef struct
377 {
378  uint32_t packet;
379  uint32_t control;
380 } Lpc175xRxDesc;
381 
382 
383 /**
384  * @brief Receive status
385  **/
386 
387 typedef struct
388 {
389  uint32_t info;
390  uint32_t hashCrc;
392 
393 
394 //LPC175x Ethernet MAC driver
395 extern const NicDriver lpc175xEthDriver;
396 
397 //LPC175x Ethernet MAC related functions
399 void lpc175xEthInitGpio(NetInterface *interface);
400 void lpc175xEthInitDesc(NetInterface *interface);
401 
402 void lpc175xEthTick(NetInterface *interface);
403 
404 void lpc175xEthEnableIrq(NetInterface *interface);
405 void lpc175xEthDisableIrq(NetInterface *interface);
406 void lpc175xEthEventHandler(NetInterface *interface);
407 
409  const NetBuffer *buffer, size_t offset);
410 
412 
415 
416 void lpc175xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
417 uint16_t lpc175xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
418 
419 void lpc175xEthWriteSmi(uint32_t data, uint_t length);
421 
422 uint32_t lpc175xEthCalcCrc(const void *data, size_t length);
423 
424 //C++ guard
425 #ifdef __cplusplus
426  }
427 #endif
428 
429 #endif
void lpc175xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t lpc175xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t lpc175xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void lpc175xEthEventHandler(NetInterface *interface)
LPC175x Ethernet MAC event handler.
uint32_t lpc175xEthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t lpc175xEthInit(NetInterface *interface)
LPC175x Ethernet MAC initialization.
void lpc175xEthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
const NicDriver lpc175xEthDriver
LPC175x Ethernet MAC driver.
uint32_t lpc175xEthReadSmi(uint_t length)
SMI read operation.
Receive status.
Transmit status.
error_t lpc175xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Transmit descriptor.
void lpc175xEthDisableIrq(NetInterface *interface)
Disable interrupts.
void lpc175xEthEnableIrq(NetInterface *interface)
Enable interrupts.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void lpc175xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
error_t lpc175xEthReceivePacket(NetInterface *interface)
Receive a packet.
error_t lpc175xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint16_t regAddr
void lpc175xEthInitGpio(NetInterface *interface)
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
Receive descriptor.
uint8_t length
Definition: dtls_misc.h:140
Network interface controller abstraction layer.
void lpc175xEthTick(NetInterface *interface)
LPC175x Ethernet MAC timer handler.