lpc175x_eth_driver.h
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1 /**
2  * @file lpc175x_eth_driver.h
3  * @brief LPC1758 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _LPC175X_ETH_DRIVER_H
32 #define _LPC175X_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef LPC175X_ETH_TX_BUFFER_COUNT
39  #define LPC175X_ETH_TX_BUFFER_COUNT 2
40 #elif (LPC175X_ETH_TX_BUFFER_COUNT < 1)
41  #error LPC175X_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef LPC175X_ETH_TX_BUFFER_SIZE
46  #define LPC175X_ETH_TX_BUFFER_SIZE 1536
47 #elif (LPC175X_ETH_TX_BUFFER_SIZE != 1536)
48  #error LPC175X_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef LPC175X_ETH_RX_BUFFER_COUNT
53  #define LPC175X_ETH_RX_BUFFER_COUNT 4
54 #elif (LPC175X_ETH_RX_BUFFER_COUNT < 1)
55  #error LPC175X_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef LPC175X_ETH_RX_BUFFER_SIZE
60  #define LPC175X_ETH_RX_BUFFER_SIZE 1536
61 #elif (LPC175X_ETH_RX_BUFFER_SIZE != 1536)
62  #error LPC175X_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef LPC175X_ETH_IRQ_PRIORITY_GROUPING
67  #define LPC175X_ETH_IRQ_PRIORITY_GROUPING 2
68 #elif (LPC175X_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error LPC175X_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef LPC175X_ETH_IRQ_GROUP_PRIORITY
74  #define LPC175X_ETH_IRQ_GROUP_PRIORITY 24
75 #elif (LPC175X_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error LPC175X_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef LPC175X_ETH_IRQ_SUB_PRIORITY
81  #define LPC175X_ETH_IRQ_SUB_PRIORITY 0
82 #elif (LPC175X_ETH_IRQ_SUB_PRIORITY < 0)
83  #error LPC175X_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //MDC pin
87 #ifndef LPC175X_ETH_MDC_GPIO
88  #define LPC175X_ETH_MDC_GPIO LPC_GPIO2
89 #endif
90 
91 #ifndef LPC175X_ETH_MDC_MASK
92  #define LPC175X_ETH_MDC_MASK (1 << 8)
93 #endif
94 
95 //MDIO pin
96 #ifndef LPC175X_ETH_MDIO_GPIO
97  #define LPC175X_ETH_MDIO_GPIO LPC_GPIO2
98 #endif
99 
100 #ifndef LPC175X_ETH_MDIO_MASK
101  #define LPC175X_ETH_MDIO_MASK (1 << 9)
102 #endif
103 
104 //MAC1 register
105 #define MAC1_SOFT_RESET 0x00008000
106 #define MAC1_SIMULATION_RESET 0x00004000
107 #define MAC1_RESET_MCS_RX 0x00000800
108 #define MAC1_RESET_RX 0x00000400
109 #define MAC1_RESET_MCS_TX 0x00000200
110 #define MAC1_RESET_TX 0x00000100
111 #define MAC1_LOOPBACK 0x00000010
112 #define MAC1_TX_FLOW_CONTROL 0x00000008
113 #define MAC1_RX_FLOW_CONTROL 0x00000004
114 #define MAC1_PASS_ALL_FRAMES 0x00000002
115 #define MAC1_RECEIVE_ENABLE 0x00000001
116 
117 //MAC2 register
118 #define MAC2_EXCESS_DEFER 0x00004000
119 #define MAC2_BACK_PRESSURE_NO_BACKOFF 0x00002000
120 #define MAC2_NO_BACKOFF 0x00001000
121 #define MAC2_LONG_PREAMBLE_ENFORCEMENT 0x00000200
122 #define MAC2_PURE_PREAMBLE_ENFORCEMENT 0x00000100
123 #define MAC2_AUTO_DETECT_PAD_ENABLE 0x00000080
124 #define MAC2_VLAN_PAD_ENABLE 0x00000040
125 #define MAC2_PAD_CRC_ENABLE 0x00000020
126 #define MAC2_CRC_ENABLE 0x00000010
127 #define MAC2_DELAYED_CRC 0x00000008
128 #define MAC2_HUGE_FRAME_ENABLE 0x00000004
129 #define MAC2_FRAME_LENGTH_CHECKING 0x00000002
130 #define MAC2_FULL_DUPLEX 0x00000001
131 
132 //IPGT register
133 #define IPGT_BACK_TO_BACK_IPG 0x0000007F
134 #define IPGT_HALF_DUPLEX 0x00000012
135 #define IPGT_FULL_DUPLEX 0x00000015
136 
137 //IPGR register
138 #define IPGR_NON_BACK_TO_BACK_IPG1 0x00007F00
139 #define IPGR_NON_BACK_TO_BACK_IPG2 0x0000007F
140 #define IPGR_DEFAULT_VALUE 0x00000C12
141 
142 //CLRT register
143 #define CLRT_COLLISION_WINDOW 0x00003F00
144 #define CLRT_RETRANSMISSION_MAXIMUM 0x00003F00
145 #define CLRT_DEFAULT_VALUE 0x0000370F
146 
147 //MAXF register
148 #define MAXF_MAXIMUM_FRAME_LENGTH 0x0000FFFF
149 
150 //SUPP register
151 #define SUPP_SPEED 0x00000100
152 
153 //TEST register
154 #define TEST_BACKPRESSURE 0x00000004
155 #define TEST_PAUSE 0x00000002
156 #define TEST_SHORTCUT_PAUSE_QUANTA 0x00000001
157 
158 //MCFG register
159 #define MCFG_RESET_MII_MGMT 0x00008000
160 #define MCFG_CLOCK SELECT 0x0000003C
161 #define MCFG_SUPPRESS_PREAMBLE 0x00000002
162 #define MCFG_SCAN_INCREMENT 0x00000001
163 
164 #define MCFG_CLOCK_SELECT_DIV4 0x00000000
165 #define MCFG_CLOCK_SELECT_DIV6 0x00000008
166 #define MCFG_CLOCK_SELECT_DIV8 0x0000000C
167 #define MCFG_CLOCK_SELECT_DIV10 0x00000010
168 #define MCFG_CLOCK_SELECT_DIV14 0x00000014
169 #define MCFG_CLOCK_SELECT_DIV20 0x00000018
170 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
171 #define MCFG_CLOCK_SELECT_DIV36 0x00000020
172 #define MCFG_CLOCK_SELECT_DIV40 0x00000024
173 #define MCFG_CLOCK_SELECT_DIV44 0x00000028
174 #define MCFG_CLOCK_SELECT_DIV48 0x0000002C
175 #define MCFG_CLOCK_SELECT_DIV52 0x00000030
176 #define MCFG_CLOCK_SELECT_DIV56 0x00000034
177 #define MCFG_CLOCK_SELECT_DIV60 0x00000038
178 #define MCFG_CLOCK_SELECT_DIV64 0x0000003C
179 
180 //MCMD register
181 #define MCMD_SCAN 0x00000002
182 #define MCMD_READ 0x00000001
183 
184 //MADR register
185 #define MADR_PHY_ADDRESS 0x00001F00
186 #define MADR_REGISTER_ADDRESS 0x0000001F
187 
188 //MWTD register
189 #define MWTD_WRITE_DATA 0x0000FFFF
190 
191 //MRDD register
192 #define MRDD_READ_DATA 0x0000FFFF
193 
194 //MIND register
195 #define MIND_MII_LINK_FAIL 0x00000008
196 #define MIND_NOT_VALID 0x00000004
197 #define MIND_SCANNING 0x00000002
198 #define MIND_BUSY 0x00000001
199 
200 //Command register
201 #define COMMAND_FULL_DUPLEX 0x00000400
202 #define COMMAND_RMII 0x00000200
203 #define COMMAND_TX_FLOW_CONTROL 0x00000100
204 #define COMMAND_PASS_RX_FILTER 0x00000080
205 #define COMMAND_PASS_RUNT_FRAME 0x00000040
206 #define COMMAND_RX_RESET 0x00000020
207 #define COMMAND_TX_RESET 0x00000010
208 #define COMMAND_REG_RESET 0x00000008
209 #define COMMAND_TX_ENABLE 0x00000002
210 #define COMMAND_RX_ENABLE 0x00000001
211 
212 //Status register
213 #define STATUS_TX 0x00000002
214 #define STATUS_RX 0x00000001
215 
216 //TSV0 register
217 #define TSV0_VLAN 0x80000000
218 #define TSV0_BACKPRESSURE 0x40000000
219 #define TSV0_PAUSE 0x20000000
220 #define TSV0_CONTROL_FRAME 0x10000000
221 #define TSV0_TOTAL_BYTES 0x0FFFF000
222 #define TSV0_UNDERRUN 0x00000800
223 #define TSV0_GIANT 0x00000400
224 #define TSV0_LATE_COLLISION 0x00000200
225 #define TSV0_EXCESSIVE_COLLISION 0x00000100
226 #define TSV0_EXCESSIVE_DEFER 0x00000080
227 #define TSV0_PACKET_DEFER 0x00000040
228 #define TSV0_BROADCAST 0x00000020
229 #define TSV0_MULTICAST 0x00000010
230 #define TSV0_DONE 0x00000008
231 #define TSV0_LENGTH_OUT_OF_RANGE 0x00000004
232 #define TSV0_LENGTH_CHECK_ERROR 0x00000002
233 #define TSV0_CRC_ERROR 0x00000001
234 
235 //TSV1 register
236 #define TSV1_TRANSMIT_COLLISION_COUNT 0x000F0000
237 #define TSV1_TRANSMIT_BYTE_COUNT 0x0000FFFF
238 
239 //RSV register
240 #define RSV_VLAN 0x40000000
241 #define RSV_UNSUPPORTED_OPCODE 0x20000000
242 #define RSV_PAUSE 0x10000000
243 #define RSV_CONTROL_FRAME 0x08000000
244 #define RSV_DRIBBLE_NIBBLE 0x04000000
245 #define RSV_BROADCAST 0x02000000
246 #define RSV_MULTICAST 0x01000000
247 #define RSV_RECEIVE_OK 0x00800000
248 #define RSV_LENGTH_OUT_OF_RANGE 0x00400000
249 #define RSV_LENGTH_CHECK_ERROR 0x00200000
250 #define RSV_CRC_ERROR 0x00100000
251 #define RSV_RECEIVE_CODE_VIOLATION 0x00080000
252 #define RSV_CARRIER_EVENT_PREV_SEEN 0x00040000
253 #define RSV_RXDV_EVENT_PREV_SEEN 0x00020000
254 #define RSV_PACKET_PREVIOUSLY_IGNORED 0x00010000
255 #define RSV_RECEIVED_BYTE_COUNT 0x0000FFFF
256 
257 //FlowControlCounter register
258 #define FCC_PAUSE_TIMER 0xFFFF0000
259 #define FCC_MIRROR_COUNTER 0x0000FFFF
260 
261 //FlowControlStatus register
262 #define FCS_MIRROR_COUNTER_CURRENT 0x0000FFFF
263 
264 //RxFilterCtrl register
265 #define RFC_RX_FILTER_EN_WOL 0x00002000
266 #define RFC_MAGIC_PACKET_EN_WOL 0x00001000
267 #define RFC_ACCEPT_PERFECT_EN 0x00000020
268 #define RFC_ACCEPT_MULTICAST_HASH_EN 0x00000010
269 #define RFC_ACCEPT_UNICAST_HASH_EN 0x00000008
270 #define RFC_ACCEPT_MULTICAST_EN 0x00000004
271 #define RFC_ACCEPT_BROADCAST_EN 0x00000002
272 #define RFC_ACCEPT_UNICAST_EN 0x00000001
273 
274 //RxFilterWoLStatus and RxFilterWoLClear registers
275 #define RFWS_MAGIC_PACKET_WOL 0x00000100
276 #define RFWS_RX_FILTER_WOL 0x00000080
277 #define RFWS_ACCEPT_PERFECT_WOL 0x00000020
278 #define RFWS_ACCEPT_MULTICAST_HASH_WOL 0x00000010
279 #define RFWS_ACCEPT_UNICAST_HASH_WOL 0x00000008
280 #define RFWS_ACCEPT_MULTICAST_WOL 0x00000004
281 #define RFWS_ACCEPT_BROADCAST_WOL 0x00000002
282 #define RFWS_ACCEPT_UNICAST_WOL 0x00000001
283 
284 //IntStatus, IntEnable, IntClear and IntSet registers
285 #define INT_WAKEUP 0x00002000
286 #define INT_SOFT_INT 0x00001000
287 #define INT_TX_DONE 0x00000080
288 #define INT_TX_FINISHED 0x00000040
289 #define INT_TX_ERROR 0x00000020
290 #define INT_TX_UNDERRUN 0x00000010
291 #define INT_RX_DONE 0x00000008
292 #define INT_RX_FINISHED 0x00000004
293 #define INT_RX_ERROR 0x00000002
294 #define INT_RX_OVERRUN 0x00000001
295 
296 //Transmit descriptor control word
297 #define TX_CTRL_INTERRUPT 0x80000000
298 #define TX_CTRL_LAST 0x40000000
299 #define TX_CTRL_CRC 0x20000000
300 #define TX_CTRL_PAD 0x10000000
301 #define TX_CTRL_HUGE 0x08000000
302 #define TX_CTRL_OVERRIDE 0x04000000
303 #define TX_CTRL_SIZE 0x000007FF
304 
305 //Transmit status information word
306 #define TX_STATUS_ERROR 0x80000000
307 #define TX_STATUS_NO_DESCRIPTOR 0x40000000
308 #define TX_STATUS_UNDERRUN 0x20000000
309 #define TX_STATUS_LATE_COLLISION 0x10000000
310 #define TX_STATUS_EXCESSIVE_COLLISION 0x08000000
311 #define TX_STATUS_EXCESSIVE_DEFER 0x04000000
312 #define TX_STATUS_DEFER 0x02000000
313 #define TX_STATUS_COLLISION_COUNT 0x01E00000
314 
315 //Receive descriptor control word
316 #define RX_CTRL_INTERRUPT 0x80000000
317 #define RX_CTRL_SIZE 0x000007FF
318 
319 //Receive status information word
320 #define RX_STATUS_ERROR 0x80000000
321 #define RX_STATUS_LAST_FLAG 0x40000000
322 #define RX_STATUS_NO_DESCRIPTOR 0x20000000
323 #define RX_STATUS_OVERRUN 0x10000000
324 #define RX_STATUS_ALIGNMENT_ERROR 0x08000000
325 #define RX_STATUS_RANGE_ERROR 0x04000000
326 #define RX_STATUS_LENGTH_ERROR 0x02000000
327 #define RX_STATUS_SYMBOL_ERROR 0x01000000
328 #define RX_STATUS_CRC_ERROR 0x00800000
329 #define RX_STATUS_BROADCAST 0x00400000
330 #define RX_STATUS_MULTICAST 0x00200000
331 #define RX_STATUS_FAIL_FILTER 0x00100000
332 #define RX_STATUS_VLAN 0x00080000
333 #define RX_STATUS_CONTROL_FRAME 0x00040000
334 #define RX_STATUS_SIZE 0x000007FF
335 
336 //Receive status HashCRC word
337 #define RX_HASH_CRC_DA 0x001FF000
338 #define RX_HASH_CRC_SA 0x000001FF
339 
340 //C++ guard
341 #ifdef __cplusplus
342 extern "C" {
343 #endif
344 
345 
346 /**
347  * @brief Transmit descriptor
348  **/
349 
350 typedef struct
351 {
352  uint32_t packet;
353  uint32_t control;
354 } Lpc175xTxDesc;
355 
356 
357 /**
358  * @brief Transmit status
359  **/
360 
361 typedef struct
362 {
363  uint32_t info;
365 
366 
367 /**
368  * @brief Receive descriptor
369  **/
370 
371 typedef struct
372 {
373  uint32_t packet;
374  uint32_t control;
375 } Lpc175xRxDesc;
376 
377 
378 /**
379  * @brief Receive status
380  **/
381 
382 typedef struct
383 {
384  uint32_t info;
385  uint32_t hashCrc;
387 
388 
389 //LPC175x Ethernet MAC driver
390 extern const NicDriver lpc175xEthDriver;
391 
392 //LPC175x Ethernet MAC related functions
394 void lpc175xEthInitGpio(NetInterface *interface);
395 void lpc175xEthInitDesc(NetInterface *interface);
396 
397 void lpc175xEthTick(NetInterface *interface);
398 
399 void lpc175xEthEnableIrq(NetInterface *interface);
400 void lpc175xEthDisableIrq(NetInterface *interface);
401 void lpc175xEthEventHandler(NetInterface *interface);
402 
404  const NetBuffer *buffer, size_t offset);
405 
407 
410 
411 void lpc175xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
412  uint8_t regAddr, uint16_t data);
413 
414 uint16_t lpc175xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
415  uint8_t regAddr);
416 
417 void lpc175xEthWriteSmi(uint32_t data, uint_t length);
419 
420 uint32_t lpc175xEthCalcCrc(const void *data, size_t length);
421 
422 //C++ guard
423 #ifdef __cplusplus
424 }
425 #endif
426 
427 #endif
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
error_t lpc175xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint32_t lpc175xEthCalcCrc(const void *data, size_t length)
CRC calculation.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void lpc175xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t lpc175xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t lpc175xEthInit(NetInterface *interface)
LPC175x Ethernet MAC initialization.
const NicDriver lpc175xEthDriver
LPC175x Ethernet MAC driver.
void lpc175xEthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t
Error codes.
Definition: error.h:42
uint32_t lpc175xEthReadSmi(uint_t length)
SMI read operation.
void lpc175xEthEventHandler(NetInterface *interface)
LPC175x Ethernet MAC event handler.
Receive descriptor.
void lpc175xEthTick(NetInterface *interface)
LPC175x Ethernet MAC timer handler.
#define NetInterface
Definition: net.h:36
uint16_t lpc175xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void lpc175xEthInitGpio(NetInterface *interface)
void lpc175xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
uint16_t regAddr
void lpc175xEthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
error_t lpc175xEthReceivePacket(NetInterface *interface)
Receive a packet.
error_t lpc175xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Network interface controller abstraction layer.
unsigned int uint_t
Definition: compiler_port.h:45
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
Receive status.
void lpc175xEthEnableIrq(NetInterface *interface)
Enable interrupts.
Transmit status.
Transmit descriptor.