lpc175x_eth_driver.c
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1 /**
2  * @file lpc175x_eth_driver.c
3  * @brief LPC1758 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "lpc17xx.h"
34 #include "core/net.h"
36 #include "debug.h"
37 
38 //Underlying network interface
39 static NetInterface *nicDriverInterface;
40 
41 //IAR EWARM compiler?
42 #if defined(__ICCARM__)
43 
44 //Transmit buffer
45 #pragma data_alignment = 4
47 //Receive buffer
48 #pragma data_alignment = 4
50 //Transmit descriptors
51 #pragma data_alignment = 4
53 //Transmit status array
54 #pragma data_alignment = 4
56 //Receive descriptors
57 #pragma data_alignment = 4
59 //Receive status array
60 #pragma data_alignment = 8
62 
63 //Keil MDK-ARM or GCC compiler?
64 #else
65 
66 //Transmit buffer
68  __attribute__((aligned(4)));
69 //Receive buffer
71  __attribute__((aligned(4)));
72 //Transmit descriptors
74  __attribute__((aligned(4)));
75 //Transmit status array
77  __attribute__((aligned(4)));
78 //Receive descriptors
80  __attribute__((aligned(4)));
81 //Receive status array
83  __attribute__((aligned(8)));
84 
85 #endif
86 
87 
88 /**
89  * @brief LPC175x Ethernet MAC driver
90  **/
91 
93 {
95  ETH_MTU,
106  TRUE,
107  TRUE,
108  TRUE,
109  FALSE
110 };
111 
112 
113 /**
114  * @brief LPC175x Ethernet MAC initialization
115  * @param[in] interface Underlying network interface
116  * @return Error code
117  **/
118 
120 {
121  error_t error;
122 
123  //Debug message
124  TRACE_INFO("Initializing LPC175x Ethernet MAC...\r\n");
125 
126  //Save underlying network interface
127  nicDriverInterface = interface;
128 
129  //Power up EMAC controller
130  LPC_SC->PCONP |= PCONP_PCENET;
131 
132  //GPIO configuration
133  lpc175xEthInitGpio(interface);
134 
135  //Reset host registers, transmit datapath and receive datapath
136  LPC_EMAC->Command = COMMAND_RX_RESET | COMMAND_TX_RESET | COMMAND_REG_RESET;
137 
138  //Reset EMAC controller
139  LPC_EMAC->MAC1 = MAC1_SOFT_RESET | MAC1_SIMULATION_RESET |
141 
142  //Initialize MAC related registers
143  LPC_EMAC->MAC1 = 0;
144  LPC_EMAC->MAC2 = MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE;
145  LPC_EMAC->IPGR = IPGR_DEFAULT_VALUE;
146  LPC_EMAC->CLRT = CLRT_DEFAULT_VALUE;
147 
148  //Select RMII mode
149  LPC_EMAC->Command = COMMAND_RMII;
150 
151  //PHY transceiver initialization
152  error = interface->phyDriver->init(interface);
153  //Failed to initialize PHY transceiver?
154  if(error)
155  return error;
156 
157  //Initialize TX and RX descriptor arrays
158  lpc175xEthInitDesc(interface);
159 
160  //Set the MAC address
161  LPC_EMAC->SA0 = interface->macAddr.w[2];
162  LPC_EMAC->SA1 = interface->macAddr.w[1];
163  LPC_EMAC->SA2 = interface->macAddr.w[0];
164 
165  //Initialize hash table
166  LPC_EMAC->HashFilterL = 0;
167  LPC_EMAC->HashFilterH = 0;
168 
169  //Configure the receive filter
170  LPC_EMAC->RxFilterCtrl = RFC_ACCEPT_PERFECT_EN |
172 
173  //Program the MAXF register with the maximum frame length to be accepted
174  LPC_EMAC->MAXF = 1518;
175 
176  //Reset EMAC interrupt flags
177  LPC_EMAC->IntClear = 0xFFFF;
178  //Enable desired EMAC interrupts
179  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
180 
181  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
182  NVIC_SetPriorityGrouping(LPC175X_ETH_IRQ_PRIORITY_GROUPING);
183 
184  //Configure Ethernet interrupt priority
185  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(LPC175X_ETH_IRQ_PRIORITY_GROUPING,
187 
188  //Enable transmission and reception
189  LPC_EMAC->Command |= COMMAND_TX_ENABLE | COMMAND_RX_ENABLE;
190  //Allow frames to be received
191  LPC_EMAC->MAC1 |= MAC1_RECEIVE_ENABLE;
192 
193  //Accept any packets from the upper layer
194  osSetEvent(&interface->nicTxEvent);
195 
196  //Successful initialization
197  return NO_ERROR;
198 }
199 
200 
201 //MCB1758 evaluation board?
202 #if defined(USE_MCB1758)
203 
204 /**
205  * @brief GPIO configuration
206  * @param[in] interface Underlying network interface
207  **/
208 
209 void lpc175xEthInitGpio(NetInterface *interface)
210 {
211  //Configure P1.0 (ENET_TXD0), P1.1 (ENET_TXD1), P1.4 (ENET_TX_EN), P1.8 (ENET_CRS),
212  //P1.9 (ENET_RXD0), P1.10 (ENET_RXD1), P1.14 (RX_ER) and P1.15 (ENET_REF_CLK)
213  LPC_PINCON->PINSEL2 &= ~(PINSEL2_P1_0_MASK | PINSEL2_P1_1_MASK |
214  PINSEL2_P1_4_MASK | PINSEL2_P1_8_MASK | PINSEL2_P1_9_MASK |
215  PINSEL2_P1_10_MASK | PINSEL2_P1_14_MASK | PINSEL2_P1_15_MASK);
216 
217  LPC_PINCON->PINSEL2 |= PINSEL2_P1_0_ENET_TXD0 | PINSEL2_P1_1_ENET_TXD1 |
218  PINSEL2_P1_4_ENET_TX_EN | PINSEL2_P1_8_ENET_CRS | PINSEL2_P1_9_ENET_RXD0 |
219  PINSEL2_P1_10_ENET_RXD1 | PINSEL2_P1_14_ENET_RX_ER | PINSEL2_P1_15_ENET_REF_CLK;
220 
221  //Configure P2.8 (ENET_MDC) and P2.9 (ENET_MDIO) as GPIOs
222  LPC_PINCON->PINSEL4 &= ~(PINSEL4_P2_8_MASK | PINSEL4_P2_9_MASK);
223  LPC_PINCON->PINSEL4 |= PINSEL4_P2_8_GPIO | PINSEL4_P2_9_GPIO;
224 
225  //SMI software implementation to drive MDC and MDIO
229 }
230 
231 #endif
232 
233 
234 /**
235  * @brief Initialize TX and RX descriptors
236  * @param[in] interface Underlying network interface
237  **/
238 
240 {
241  uint_t i;
242 
243  //Initialize TX descriptors
244  for(i = 0; i < LPC175X_ETH_TX_BUFFER_COUNT; i++)
245  {
246  //Base address of the buffer containing transmit data
247  txDesc[i].packet = (uint32_t) txBuffer[i];
248  //Transmit descriptor control word
249  txDesc[i].control = 0;
250  //Transmit status information word
251  txStatus[i].info = 0;
252  }
253 
254  //Initialize RX descriptors
255  for(i = 0; i < LPC175X_ETH_RX_BUFFER_COUNT; i++)
256  {
257  //Base address of the buffer for storing receive data
258  rxDesc[i].packet = (uint32_t) rxBuffer[i];
259  //Receive descriptor control word
261  //Receive status information word
262  rxStatus[i].info = 0;
263  //Receive status HashCRC word
264  rxStatus[i].hashCrc = 0;
265  }
266 
267  //Initialize EMAC transmit descriptor registers
268  LPC_EMAC->TxDescriptor = (uint32_t) txDesc;
269  LPC_EMAC->TxStatus = (uint32_t) txStatus;
270  LPC_EMAC->TxDescriptorNumber = LPC175X_ETH_TX_BUFFER_COUNT - 1;
271  LPC_EMAC->TxProduceIndex = 0;
272 
273  //Initialize EMAC receive descriptor registers
274  LPC_EMAC->RxDescriptor = (uint32_t) rxDesc;
275  LPC_EMAC->RxStatus = (uint32_t) rxStatus;
276  LPC_EMAC->RxDescriptorNumber = LPC175X_ETH_RX_BUFFER_COUNT - 1;
277  LPC_EMAC->RxConsumeIndex = 0;
278 }
279 
280 
281 /**
282  * @brief LPC175x Ethernet MAC timer handler
283  *
284  * This routine is periodically called by the TCP/IP stack to
285  * handle periodic operations such as polling the link state
286  *
287  * @param[in] interface Underlying network interface
288  **/
289 
290 void lpc175xEthTick(NetInterface *interface)
291 {
292  //Handle periodic operations
293  interface->phyDriver->tick(interface);
294 }
295 
296 
297 /**
298  * @brief Enable interrupts
299  * @param[in] interface Underlying network interface
300  **/
301 
303 {
304  //Enable Ethernet MAC interrupts
305  NVIC_EnableIRQ(ENET_IRQn);
306  //Enable Ethernet PHY interrupts
307  interface->phyDriver->enableIrq(interface);
308 }
309 
310 
311 /**
312  * @brief Disable interrupts
313  * @param[in] interface Underlying network interface
314  **/
315 
317 {
318  //Disable Ethernet MAC interrupts
319  NVIC_DisableIRQ(ENET_IRQn);
320  //Disable Ethernet PHY interrupts
321  interface->phyDriver->disableIrq(interface);
322 }
323 
324 
325 /**
326  * @brief LPC175x Ethernet MAC interrupt service routine
327  **/
328 
329 void ENET_IRQHandler(void)
330 {
331  uint_t i;
332  bool_t flag;
333  uint32_t status;
334 
335  //Enter interrupt service routine
336  osEnterIsr();
337 
338  //This flag will be set if a higher priority task must be woken
339  flag = FALSE;
340 
341  //Read interrupt status register
342  status = LPC_EMAC->IntStatus;
343 
344  //A packet has been transmitted?
345  if(status & INT_TX_DONE)
346  {
347  //Clear TxDone interrupt flag
348  LPC_EMAC->IntClear = INT_TX_DONE;
349 
350  //Get the index of the next descriptor
351  i = LPC_EMAC->TxProduceIndex + 1;
352 
353  //Wrap around if necessary
355  i = 0;
356 
357  //Check whether the TX buffer is available for writing
358  if(i != LPC_EMAC->TxConsumeIndex)
359  {
360  //Notify the TCP/IP stack that the transmitter is ready to send
361  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
362  }
363  }
364 
365  //A packet has been received?
366  if(status & INT_RX_DONE)
367  {
368  //Disable RxDone interrupts
369  LPC_EMAC->IntEnable &= ~INT_RX_DONE;
370 
371  //Set event flag
372  nicDriverInterface->nicEvent = TRUE;
373  //Notify the TCP/IP stack of the event
374  flag |= osSetEventFromIsr(&netEvent);
375  }
376 
377  //Leave interrupt service routine
378  osExitIsr(flag);
379 }
380 
381 
382 /**
383  * @brief LPC175x Ethernet MAC event handler
384  * @param[in] interface Underlying network interface
385  **/
386 
388 {
389  error_t error;
390 
391  //Packet received?
392  if(LPC_EMAC->IntStatus & INT_RX_DONE)
393  {
394  //Clear RxDone interrupt flag
395  LPC_EMAC->IntClear = INT_RX_DONE;
396 
397  //Process all pending packets
398  do
399  {
400  //Read incoming packet
401  error = lpc175xEthReceivePacket(interface);
402 
403  //No more data in the receive buffer?
404  } while(error != ERROR_BUFFER_EMPTY);
405  }
406 
407  //Re-enable TxDone and RxDone interrupts
408  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
409 }
410 
411 
412 /**
413  * @brief Send a packet
414  * @param[in] interface Underlying network interface
415  * @param[in] buffer Multi-part buffer containing the data to send
416  * @param[in] offset Offset to the first data byte
417  * @return Error code
418  **/
419 
421  const NetBuffer *buffer, size_t offset)
422 {
423  uint_t i;
424  uint_t j;
425  size_t length;
426 
427  //Retrieve the length of the packet
428  length = netBufferGetLength(buffer) - offset;
429 
430  //Check the frame length
431  if(!length)
432  {
433  //The transmitter can accept another packet
434  osSetEvent(&interface->nicTxEvent);
435  //We are done since the buffer is empty
436  return NO_ERROR;
437  }
439  {
440  //The transmitter can accept another packet
441  osSetEvent(&interface->nicTxEvent);
442  //Report an error
443  return ERROR_INVALID_LENGTH;
444  }
445 
446  //Get the index of the current descriptor
447  i = LPC_EMAC->TxProduceIndex;
448  //Get the index of the next descriptor
449  j = i + 1;
450 
451  //Wrap around if necessary
453  j = 0;
454 
455  //Check whether the transmit descriptor array is full
456  if(j == LPC_EMAC->TxConsumeIndex)
457  return ERROR_FAILURE;
458 
459  //Copy user data to the transmit buffer
460  netBufferRead((uint8_t *) txDesc[i].packet, buffer, offset, length);
461 
462  //Write the transmit control word
463  txDesc[i].control = TX_CTRL_INTERRUPT | TX_CTRL_LAST |
465 
466  //Increment index and wrap around if necessary
467  if(++i >= LPC175X_ETH_TX_BUFFER_COUNT)
468  i = 0;
469 
470  //Save the resulting value
471  LPC_EMAC->TxProduceIndex = i;
472 
473  //Get the index of the next descriptor
474  j = i + 1;
475 
476  //Wrap around if necessary
478  j = 0;
479 
480  //Check whether the next buffer is available for writing
481  if(j != LPC_EMAC->TxConsumeIndex)
482  {
483  //The transmitter can accept another packet
484  osSetEvent(&interface->nicTxEvent);
485  }
486 
487  //Successful write operation
488  return NO_ERROR;
489 }
490 
491 
492 /**
493  * @brief Receive a packet
494  * @param[in] interface Underlying network interface
495  * @return Error code
496  **/
497 
499 {
500  error_t error;
501  size_t n;
502  uint_t i;
503 
504  //Point to the current descriptor
505  i = LPC_EMAC->RxConsumeIndex;
506 
507  //Make sure the current buffer is available for reading
508  if(i != LPC_EMAC->RxProduceIndex)
509  {
510  //Retrieve the length of the frame
511  n = (rxStatus[i].info & RX_STATUS_SIZE) + 1;
512  //Limit the number of data to read
514 
515  //Pass the packet to the upper layer
516  nicProcessPacket(interface, (uint8_t *) rxDesc[i].packet, n);
517 
518  //Increment index and wrap around if necessary
519  if(++i >= LPC175X_ETH_RX_BUFFER_COUNT)
520  i = 0;
521 
522  //Save the resulting value
523  LPC_EMAC->RxConsumeIndex = i;
524 
525  //Valid packet received
526  error = NO_ERROR;
527  }
528  else
529  {
530  //No more data in the receive buffer
531  error = ERROR_BUFFER_EMPTY;
532  }
533 
534  //Return status code
535  return error;
536 }
537 
538 
539 /**
540  * @brief Configure MAC address filtering
541  * @param[in] interface Underlying network interface
542  * @return Error code
543  **/
544 
546 {
547  uint_t i;
548  uint_t k;
549  uint32_t crc;
550  uint32_t hashTable[2];
551  MacFilterEntry *entry;
552 
553  //Debug message
554  TRACE_DEBUG("Updating LPC175x hash table...\r\n");
555 
556  //Clear hash table
557  hashTable[0] = 0;
558  hashTable[1] = 0;
559 
560  //The MAC address filter contains the list of MAC addresses to accept
561  //when receiving an Ethernet frame
562  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
563  {
564  //Point to the current entry
565  entry = &interface->macAddrFilter[i];
566 
567  //Valid entry?
568  if(entry->refCount > 0)
569  {
570  //Compute CRC over the current MAC address
571  crc = lpc175xEthCalcCrc(&entry->addr, sizeof(MacAddr));
572  //Bits [28:23] are used to form the hash
573  k = (crc >> 23) & 0x3F;
574  //Update hash table contents
575  hashTable[k / 32] |= (1 << (k % 32));
576  }
577  }
578 
579  //Write the hash table
580  LPC_EMAC->HashFilterL = hashTable[0];
581  LPC_EMAC->HashFilterH = hashTable[1];
582 
583  //Debug message
584  TRACE_DEBUG(" HashFilterL = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterL);
585  TRACE_DEBUG(" HashFilterH = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterH);
586 
587  //Successful processing
588  return NO_ERROR;
589 }
590 
591 
592 /**
593  * @brief Adjust MAC configuration parameters for proper operation
594  * @param[in] interface Underlying network interface
595  * @return Error code
596  **/
597 
599 {
600  //10BASE-T or 100BASE-TX operation mode?
601  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
602  LPC_EMAC->SUPP = SUPP_SPEED;
603  else
604  LPC_EMAC->SUPP = 0;
605 
606  //Half-duplex or full-duplex mode?
607  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
608  {
609  //The MAC operates in full-duplex mode
610  LPC_EMAC->MAC2 |= MAC2_FULL_DUPLEX;
611  LPC_EMAC->Command |= COMMAND_FULL_DUPLEX;
612  //Configure Back-to-Back Inter-Packet Gap
613  LPC_EMAC->IPGT = IPGT_FULL_DUPLEX;
614  }
615  else
616  {
617  //The MAC operates in half-duplex mode
618  LPC_EMAC->MAC2 &= ~MAC2_FULL_DUPLEX;
619  LPC_EMAC->Command &= ~COMMAND_FULL_DUPLEX;
620  //Configure Back-to-Back Inter-Packet Gap
621  LPC_EMAC->IPGT = IPGT_HALF_DUPLEX;
622  }
623 
624  //Successful processing
625  return NO_ERROR;
626 }
627 
628 
629 /**
630  * @brief Write PHY register
631  * @param[in] phyAddr PHY address
632  * @param[in] regAddr Register address
633  * @param[in] data Register value
634  **/
635 
636 void lpc175xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
637 {
638  //Synchronization pattern
640  //Start of frame
642  //Set up a write operation
644  //Write PHY address
645  lpc175xEthWriteSmi(phyAddr, 5);
646  //Write register address
648  //Turnaround
650  //Write register value
652  //Release MDIO
654 }
655 
656 
657 /**
658  * @brief Read PHY register
659  * @param[in] phyAddr PHY address
660  * @param[in] regAddr Register address
661  * @return Register value
662  **/
663 
664 uint16_t lpc175xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
665 {
666  uint16_t data;
667 
668  //Synchronization pattern
670  //Start of frame
672  //Set up a read operation
674  //Write PHY address
675  lpc175xEthWriteSmi(phyAddr, 5);
676  //Write register address
678  //Turnaround to avoid contention
680  //Read register value
681  data = lpc175xEthReadSmi(16);
682  //Force the PHY to release the MDIO pin
684 
685  //Return PHY register contents
686  return data;
687 }
688 
689 
690 /**
691  * @brief SMI write operation
692  * @param[in] data Raw data to be written
693  * @param[in] length Number of bits to be written
694  **/
695 
697 {
698  //Skip the most significant bits since they are meaningless
699  data <<= 32 - length;
700 
701  //Configure MDIO as an output
703 
704  //Write the specified number of bits
705  while(length--)
706  {
707  //Write MDIO
708  if(data & 0x80000000)
710  else
712 
713  //Assert MDC
714  usleep(1);
716  //Deassert MDC
717  usleep(1);
719 
720  //Rotate data
721  data <<= 1;
722  }
723 }
724 
725 
726 /**
727  * @brief SMI read operation
728  * @param[in] length Number of bits to be read
729  * @return Data resulting from the MDIO read operation
730  **/
731 
733 {
734  uint32_t data = 0;
735 
736  //Configure MDIO as an input
738 
739  //Read the specified number of bits
740  while(length--)
741  {
742  //Rotate data
743  data <<= 1;
744 
745  //Assert MDC
747  usleep(1);
748  //Deassert MDC
750  usleep(1);
751 
752  //Check MDIO state
754  data |= 0x00000001;
755  }
756 
757  //Return the received data
758  return data;
759 }
760 
761 
762 /**
763  * @brief CRC calculation
764  * @param[in] data Pointer to the data over which to calculate the CRC
765  * @param[in] length Number of bytes to process
766  * @return Resulting CRC value
767  **/
768 
769 uint32_t lpc175xEthCalcCrc(const void *data, size_t length)
770 {
771  uint_t i;
772  uint_t j;
773 
774  //Point to the data over which to calculate the CRC
775  const uint8_t *p = (uint8_t *) data;
776  //CRC preset value
777  uint32_t crc = 0xFFFFFFFF;
778 
779  //Loop through data
780  for(i = 0; i < length; i++)
781  {
782  //The message is processed bit by bit
783  for(j = 0; j < 8; j++)
784  {
785  //Update CRC value
786  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
787  crc = (crc << 1) ^ 0x04C11DB7;
788  else
789  crc = crc << 1;
790  }
791  }
792 
793  //Return CRC value
794  return crc;
795 }
MacAddr addr
MAC address.
Definition: ethernet.h:210
uint16_t lpc175xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t lpc175xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define IPGT_HALF_DUPLEX
#define MAC1_RESET_MCS_TX
#define LPC175X_ETH_MDIO_GPIO
void lpc175xEthEventHandler(NetInterface *interface)
LPC175x Ethernet MAC event handler.
#define RFC_ACCEPT_PERFECT_EN
#define COMMAND_TX_ENABLE
#define LPC175X_ETH_TX_BUFFER_SIZE
TCP/IP stack core.
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define LPC175X_ETH_TX_BUFFER_COUNT
Generic error code.
Definition: error.h:43
#define RX_STATUS_SIZE
void lpc175xEthTick(NetInterface *interface)
LPC175x Ethernet MAC timer handler.
#define txBuffer
uint32_t lpc175xEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define MAC1_SIMULATION_RESET
#define MAC2_CRC_ENABLE
#define CLRT_DEFAULT_VALUE
#define MAC2_PAD_CRC_ENABLE
error_t lpc175xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define MAC1_RECEIVE_ENABLE
LPC1758 Ethernet MAC controller.
#define LPC175X_ETH_IRQ_SUB_PRIORITY
#define IPGR_DEFAULT_VALUE
const NicDriver lpc175xEthDriver
LPC175x Ethernet MAC driver.
#define LPC175X_ETH_MDC_GPIO
#define LPC175X_ETH_IRQ_GROUP_PRIORITY
Receive status.
void lpc175xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define INT_RX_DONE
Transmit status.
void lpc175xEthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define TX_CTRL_CRC
#define LPC175X_ETH_IRQ_PRIORITY_GROUPING
#define LPC175X_ETH_RX_BUFFER_COUNT
Transmit descriptor.
uint32_t lpc175xEthReadSmi(uint_t length)
SMI read operation.
#define COMMAND_REG_RESET
error_t lpc175xEthReceivePacket(NetInterface *interface)
Receive a packet.
void ENET_IRQHandler(void)
LPC175x Ethernet MAC interrupt service routine.
#define SMI_START
#define MAC2_FULL_DUPLEX
#define SMI_SYNC
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define TX_CTRL_LAST
#define TX_CTRL_PAD
#define usleep(delay)
Definition: os_port.h:122
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define COMMAND_RMII
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define RFC_ACCEPT_BROADCAST_EN
#define COMMAND_FULL_DUPLEX
#define LPC175X_ETH_RX_BUFFER_SIZE
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define rxBuffer
void lpc175xEthInitGpio(NetInterface *interface)
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define MAC1_RESET_MCS_RX
#define MAC1_RESET_RX
#define COMMAND_RX_RESET
#define RFC_ACCEPT_MULTICAST_HASH_EN
unsigned int uint_t
Definition: compiler_port.h:43
#define INT_TX_DONE
__start_packed struct @112 MacAddr
MAC address.
#define IPGT_FULL_DUPLEX
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
#define TX_CTRL_SIZE
#define MAC1_SOFT_RESET
#define RX_CTRL_INTERRUPT
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define SMI_TA
void lpc175xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
void lpc175xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define SMI_READ
#define TX_CTRL_INTERRUPT
#define SMI_WRITE
#define MAC1_RESET_TX
Receive descriptor.
#define SUPP_SPEED
#define osExitIsr(flag)
#define COMMAND_TX_RESET
#define LPC175X_ETH_MDC_MASK
#define LPC175X_ETH_MDIO_MASK
#define osEnterIsr()
error_t lpc175xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void lpc175xEthEnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define COMMAND_RX_ENABLE
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
error_t lpc175xEthInit(NetInterface *interface)
LPC175x Ethernet MAC initialization.
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98