lpc175x_eth_driver.c
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1 /**
2  * @file lpc175x_eth_driver.c
3  * @brief LPC1758 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "lpc17xx.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit descriptors
53 #pragma data_alignment = 4
55 //Transmit status array
56 #pragma data_alignment = 4
58 //Receive descriptors
59 #pragma data_alignment = 4
61 //Receive status array
62 #pragma data_alignment = 8
64 
65 //Keil MDK-ARM or GCC compiler?
66 #else
67 
68 //Transmit buffer
70  __attribute__((aligned(4)));
71 //Receive buffer
73  __attribute__((aligned(4)));
74 //Transmit descriptors
76  __attribute__((aligned(4)));
77 //Transmit status array
79  __attribute__((aligned(4)));
80 //Receive descriptors
82  __attribute__((aligned(4)));
83 //Receive status array
85  __attribute__((aligned(8)));
86 
87 #endif
88 
89 
90 /**
91  * @brief LPC175x Ethernet MAC driver
92  **/
93 
95 {
97  ETH_MTU,
108  TRUE,
109  TRUE,
110  TRUE,
111  FALSE
112 };
113 
114 
115 /**
116  * @brief LPC175x Ethernet MAC initialization
117  * @param[in] interface Underlying network interface
118  * @return Error code
119  **/
120 
122 {
123  error_t error;
124 
125  //Debug message
126  TRACE_INFO("Initializing LPC175x Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Power up EMAC controller
132  LPC_SC->PCONP |= PCONP_PCENET;
133 
134  //GPIO configuration
135  lpc175xEthInitGpio(interface);
136 
137  //Reset host registers, transmit datapath and receive datapath
138  LPC_EMAC->Command = COMMAND_RX_RESET | COMMAND_TX_RESET | COMMAND_REG_RESET;
139 
140  //Reset EMAC controller
141  LPC_EMAC->MAC1 = MAC1_SOFT_RESET | MAC1_SIMULATION_RESET |
143 
144  //Initialize MAC related registers
145  LPC_EMAC->MAC1 = 0;
146  LPC_EMAC->MAC2 = MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE;
147  LPC_EMAC->IPGR = IPGR_DEFAULT_VALUE;
148  LPC_EMAC->CLRT = CLRT_DEFAULT_VALUE;
149 
150  //Select RMII mode
151  LPC_EMAC->Command = COMMAND_RMII;
152 
153  //PHY transceiver initialization
154  error = interface->phyDriver->init(interface);
155  //Failed to initialize PHY transceiver?
156  if(error)
157  return error;
158 
159  //Initialize TX and RX descriptor arrays
160  lpc175xEthInitDesc(interface);
161 
162  //Set the MAC address of the station
163  LPC_EMAC->SA0 = interface->macAddr.w[2];
164  LPC_EMAC->SA1 = interface->macAddr.w[1];
165  LPC_EMAC->SA2 = interface->macAddr.w[0];
166 
167  //Initialize hash table
168  LPC_EMAC->HashFilterL = 0;
169  LPC_EMAC->HashFilterH = 0;
170 
171  //Configure the receive filter
172  LPC_EMAC->RxFilterCtrl = RFC_ACCEPT_PERFECT_EN |
174 
175  //Program the MAXF register with the maximum frame length to be accepted
176  LPC_EMAC->MAXF = LPC175X_ETH_RX_BUFFER_SIZE;
177 
178  //Reset EMAC interrupt flags
179  LPC_EMAC->IntClear = 0xFFFF;
180  //Enable desired EMAC interrupts
181  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
182 
183  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
184  NVIC_SetPriorityGrouping(LPC175X_ETH_IRQ_PRIORITY_GROUPING);
185 
186  //Configure Ethernet interrupt priority
187  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(LPC175X_ETH_IRQ_PRIORITY_GROUPING,
189 
190  //Enable transmission and reception
191  LPC_EMAC->Command |= COMMAND_TX_ENABLE | COMMAND_RX_ENABLE;
192  //Allow frames to be received
193  LPC_EMAC->MAC1 |= MAC1_RECEIVE_ENABLE;
194 
195  //Accept any packets from the upper layer
196  osSetEvent(&interface->nicTxEvent);
197 
198  //Successful initialization
199  return NO_ERROR;
200 }
201 
202 
203 //MCB1758 evaluation board?
204 #if defined(USE_MCB1758)
205 
206 /**
207  * @brief GPIO configuration
208  * @param[in] interface Underlying network interface
209  **/
210 
211 void lpc175xEthInitGpio(NetInterface *interface)
212 {
213  //Configure P1.0 (ENET_TXD0), P1.1 (ENET_TXD1), P1.4 (ENET_TX_EN), P1.8 (ENET_CRS),
214  //P1.9 (ENET_RXD0), P1.10 (ENET_RXD1), P1.14 (RX_ER) and P1.15 (ENET_REF_CLK)
215  LPC_PINCON->PINSEL2 &= ~(PINSEL2_P1_0_MASK | PINSEL2_P1_1_MASK |
216  PINSEL2_P1_4_MASK | PINSEL2_P1_8_MASK | PINSEL2_P1_9_MASK |
217  PINSEL2_P1_10_MASK | PINSEL2_P1_14_MASK | PINSEL2_P1_15_MASK);
218 
219  LPC_PINCON->PINSEL2 |= PINSEL2_P1_0_ENET_TXD0 | PINSEL2_P1_1_ENET_TXD1 |
220  PINSEL2_P1_4_ENET_TX_EN | PINSEL2_P1_8_ENET_CRS | PINSEL2_P1_9_ENET_RXD0 |
221  PINSEL2_P1_10_ENET_RXD1 | PINSEL2_P1_14_ENET_RX_ER | PINSEL2_P1_15_ENET_REF_CLK;
222 
223  //Configure P2.8 (ENET_MDC) and P2.9 (ENET_MDIO) as GPIOs
224  LPC_PINCON->PINSEL4 &= ~(PINSEL4_P2_8_MASK | PINSEL4_P2_9_MASK);
225  LPC_PINCON->PINSEL4 |= PINSEL4_P2_8_GPIO | PINSEL4_P2_9_GPIO;
226 
227  //SMI software implementation to drive MDC and MDIO
231 }
232 
233 #endif
234 
235 
236 /**
237  * @brief Initialize TX and RX descriptors
238  * @param[in] interface Underlying network interface
239  **/
240 
242 {
243  uint_t i;
244 
245  //Initialize TX descriptors
246  for(i = 0; i < LPC175X_ETH_TX_BUFFER_COUNT; i++)
247  {
248  //Base address of the buffer containing transmit data
249  txDesc[i].packet = (uint32_t) txBuffer[i];
250  //Transmit descriptor control word
251  txDesc[i].control = 0;
252  //Transmit status information word
253  txStatus[i].info = 0;
254  }
255 
256  //Initialize RX descriptors
257  for(i = 0; i < LPC175X_ETH_RX_BUFFER_COUNT; i++)
258  {
259  //Base address of the buffer for storing receive data
260  rxDesc[i].packet = (uint32_t) rxBuffer[i];
261  //Receive descriptor control word
263  //Receive status information word
264  rxStatus[i].info = 0;
265  //Receive status HashCRC word
266  rxStatus[i].hashCrc = 0;
267  }
268 
269  //Initialize EMAC transmit descriptor registers
270  LPC_EMAC->TxDescriptor = (uint32_t) txDesc;
271  LPC_EMAC->TxStatus = (uint32_t) txStatus;
272  LPC_EMAC->TxDescriptorNumber = LPC175X_ETH_TX_BUFFER_COUNT - 1;
273  LPC_EMAC->TxProduceIndex = 0;
274 
275  //Initialize EMAC receive descriptor registers
276  LPC_EMAC->RxDescriptor = (uint32_t) rxDesc;
277  LPC_EMAC->RxStatus = (uint32_t) rxStatus;
278  LPC_EMAC->RxDescriptorNumber = LPC175X_ETH_RX_BUFFER_COUNT - 1;
279  LPC_EMAC->RxConsumeIndex = 0;
280 }
281 
282 
283 /**
284  * @brief LPC175x Ethernet MAC timer handler
285  *
286  * This routine is periodically called by the TCP/IP stack to
287  * handle periodic operations such as polling the link state
288  *
289  * @param[in] interface Underlying network interface
290  **/
291 
292 void lpc175xEthTick(NetInterface *interface)
293 {
294  //Handle periodic operations
295  interface->phyDriver->tick(interface);
296 }
297 
298 
299 /**
300  * @brief Enable interrupts
301  * @param[in] interface Underlying network interface
302  **/
303 
305 {
306  //Enable Ethernet MAC interrupts
307  NVIC_EnableIRQ(ENET_IRQn);
308  //Enable Ethernet PHY interrupts
309  interface->phyDriver->enableIrq(interface);
310 }
311 
312 
313 /**
314  * @brief Disable interrupts
315  * @param[in] interface Underlying network interface
316  **/
317 
319 {
320  //Disable Ethernet MAC interrupts
321  NVIC_DisableIRQ(ENET_IRQn);
322  //Disable Ethernet PHY interrupts
323  interface->phyDriver->disableIrq(interface);
324 }
325 
326 
327 /**
328  * @brief LPC175x Ethernet MAC interrupt service routine
329  **/
330 
331 void ENET_IRQHandler(void)
332 {
333  uint_t i;
334  bool_t flag;
335  uint32_t status;
336 
337  //Interrupt service routine prologue
338  osEnterIsr();
339 
340  //This flag will be set if a higher priority task must be woken
341  flag = FALSE;
342 
343  //Read interrupt status register
344  status = LPC_EMAC->IntStatus;
345 
346  //A packet has been transmitted?
347  if(status & INT_TX_DONE)
348  {
349  //Clear TxDone interrupt flag
350  LPC_EMAC->IntClear = INT_TX_DONE;
351 
352  //Get the index of the next descriptor
353  i = LPC_EMAC->TxProduceIndex + 1;
354 
355  //Wrap around if necessary
357  i = 0;
358 
359  //Check whether the TX buffer is available for writing
360  if(i != LPC_EMAC->TxConsumeIndex)
361  {
362  //Notify the TCP/IP stack that the transmitter is ready to send
363  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
364  }
365  }
366 
367  //A packet has been received?
368  if(status & INT_RX_DONE)
369  {
370  //Disable RxDone interrupts
371  LPC_EMAC->IntEnable &= ~INT_RX_DONE;
372 
373  //Set event flag
374  nicDriverInterface->nicEvent = TRUE;
375  //Notify the TCP/IP stack of the event
376  flag |= osSetEventFromIsr(&netEvent);
377  }
378 
379  //Interrupt service routine epilogue
380  osExitIsr(flag);
381 }
382 
383 
384 /**
385  * @brief LPC175x Ethernet MAC event handler
386  * @param[in] interface Underlying network interface
387  **/
388 
390 {
391  error_t error;
392 
393  //Packet received?
394  if(LPC_EMAC->IntStatus & INT_RX_DONE)
395  {
396  //Clear RxDone interrupt flag
397  LPC_EMAC->IntClear = INT_RX_DONE;
398 
399  //Process all pending packets
400  do
401  {
402  //Read incoming packet
403  error = lpc175xEthReceivePacket(interface);
404 
405  //No more data in the receive buffer?
406  } while(error != ERROR_BUFFER_EMPTY);
407  }
408 
409  //Re-enable TxDone and RxDone interrupts
410  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
411 }
412 
413 
414 /**
415  * @brief Send a packet
416  * @param[in] interface Underlying network interface
417  * @param[in] buffer Multi-part buffer containing the data to send
418  * @param[in] offset Offset to the first data byte
419  * @return Error code
420  **/
421 
423  const NetBuffer *buffer, size_t offset)
424 {
425  uint_t i;
426  uint_t j;
427  size_t length;
428 
429  //Retrieve the length of the packet
430  length = netBufferGetLength(buffer) - offset;
431 
432  //Check the frame length
433  if(!length)
434  {
435  //The transmitter can accept another packet
436  osSetEvent(&interface->nicTxEvent);
437  //We are done since the buffer is empty
438  return NO_ERROR;
439  }
441  {
442  //The transmitter can accept another packet
443  osSetEvent(&interface->nicTxEvent);
444  //Report an error
445  return ERROR_INVALID_LENGTH;
446  }
447 
448  //Get the index of the current descriptor
449  i = LPC_EMAC->TxProduceIndex;
450  //Get the index of the next descriptor
451  j = i + 1;
452 
453  //Wrap around if necessary
455  j = 0;
456 
457  //Check whether the transmit descriptor array is full
458  if(j == LPC_EMAC->TxConsumeIndex)
459  return ERROR_FAILURE;
460 
461  //Copy user data to the transmit buffer
462  netBufferRead((uint8_t *) txDesc[i].packet, buffer, offset, length);
463 
464  //Write the transmit control word
465  txDesc[i].control = TX_CTRL_INTERRUPT | TX_CTRL_LAST |
467 
468  //Increment index and wrap around if necessary
469  if(++i >= LPC175X_ETH_TX_BUFFER_COUNT)
470  i = 0;
471 
472  //Save the resulting value
473  LPC_EMAC->TxProduceIndex = i;
474 
475  //Get the index of the next descriptor
476  j = i + 1;
477 
478  //Wrap around if necessary
480  j = 0;
481 
482  //Check whether the next buffer is available for writing
483  if(j != LPC_EMAC->TxConsumeIndex)
484  {
485  //The transmitter can accept another packet
486  osSetEvent(&interface->nicTxEvent);
487  }
488 
489  //Successful write operation
490  return NO_ERROR;
491 }
492 
493 
494 /**
495  * @brief Receive a packet
496  * @param[in] interface Underlying network interface
497  * @return Error code
498  **/
499 
501 {
502  error_t error;
503  size_t n;
504  uint_t i;
505 
506  //Point to the current descriptor
507  i = LPC_EMAC->RxConsumeIndex;
508 
509  //Make sure the current buffer is available for reading
510  if(i != LPC_EMAC->RxProduceIndex)
511  {
512  //Retrieve the length of the frame
513  n = (rxStatus[i].info & RX_STATUS_SIZE) + 1;
514  //Limit the number of data to read
516 
517  //Pass the packet to the upper layer
518  nicProcessPacket(interface, (uint8_t *) rxDesc[i].packet, n);
519 
520  //Increment index and wrap around if necessary
521  if(++i >= LPC175X_ETH_RX_BUFFER_COUNT)
522  i = 0;
523 
524  //Save the resulting value
525  LPC_EMAC->RxConsumeIndex = i;
526 
527  //Valid packet received
528  error = NO_ERROR;
529  }
530  else
531  {
532  //No more data in the receive buffer
533  error = ERROR_BUFFER_EMPTY;
534  }
535 
536  //Return status code
537  return error;
538 }
539 
540 
541 /**
542  * @brief Configure MAC address filtering
543  * @param[in] interface Underlying network interface
544  * @return Error code
545  **/
546 
548 {
549  uint_t i;
550  uint_t k;
551  uint32_t crc;
552  uint32_t hashTable[2];
553  MacFilterEntry *entry;
554 
555  //Debug message
556  TRACE_DEBUG("Updating MAC filter...\r\n");
557 
558  //Set the MAC address of the station
559  LPC_EMAC->SA0 = interface->macAddr.w[2];
560  LPC_EMAC->SA1 = interface->macAddr.w[1];
561  LPC_EMAC->SA2 = interface->macAddr.w[0];
562 
563  //Clear hash table
564  hashTable[0] = 0;
565  hashTable[1] = 0;
566 
567  //The MAC address filter contains the list of MAC addresses to accept
568  //when receiving an Ethernet frame
569  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
570  {
571  //Point to the current entry
572  entry = &interface->macAddrFilter[i];
573 
574  //Valid entry?
575  if(entry->refCount > 0)
576  {
577  //Compute CRC over the current MAC address
578  crc = lpc175xEthCalcCrc(&entry->addr, sizeof(MacAddr));
579  //Bits [28:23] are used to form the hash
580  k = (crc >> 23) & 0x3F;
581  //Update hash table contents
582  hashTable[k / 32] |= (1 << (k % 32));
583  }
584  }
585 
586  //Write the hash table
587  LPC_EMAC->HashFilterL = hashTable[0];
588  LPC_EMAC->HashFilterH = hashTable[1];
589 
590  //Debug message
591  TRACE_DEBUG(" HashFilterL = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterL);
592  TRACE_DEBUG(" HashFilterH = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterH);
593 
594  //Successful processing
595  return NO_ERROR;
596 }
597 
598 
599 /**
600  * @brief Adjust MAC configuration parameters for proper operation
601  * @param[in] interface Underlying network interface
602  * @return Error code
603  **/
604 
606 {
607  //10BASE-T or 100BASE-TX operation mode?
608  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
609  LPC_EMAC->SUPP = SUPP_SPEED;
610  else
611  LPC_EMAC->SUPP = 0;
612 
613  //Half-duplex or full-duplex mode?
614  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
615  {
616  //The MAC operates in full-duplex mode
617  LPC_EMAC->MAC2 |= MAC2_FULL_DUPLEX;
618  LPC_EMAC->Command |= COMMAND_FULL_DUPLEX;
619  //Configure Back-to-Back Inter-Packet Gap
620  LPC_EMAC->IPGT = IPGT_FULL_DUPLEX;
621  }
622  else
623  {
624  //The MAC operates in half-duplex mode
625  LPC_EMAC->MAC2 &= ~MAC2_FULL_DUPLEX;
626  LPC_EMAC->Command &= ~COMMAND_FULL_DUPLEX;
627  //Configure Back-to-Back Inter-Packet Gap
628  LPC_EMAC->IPGT = IPGT_HALF_DUPLEX;
629  }
630 
631  //Successful processing
632  return NO_ERROR;
633 }
634 
635 
636 /**
637  * @brief Write PHY register
638  * @param[in] opcode Access type (2 bits)
639  * @param[in] phyAddr PHY address (5 bits)
640  * @param[in] regAddr Register address (5 bits)
641  * @param[in] data Register value
642  **/
643 
644 void lpc175xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
645  uint8_t regAddr, uint16_t data)
646 {
647  //Synchronization pattern
649  //Start of frame
651  //Set up a write operation
653  //Write PHY address
654  lpc175xEthWriteSmi(phyAddr, 5);
655  //Write register address
657  //Turnaround
659  //Write register value
661  //Release MDIO
663 }
664 
665 
666 /**
667  * @brief Read PHY register
668  * @param[in] opcode Access type (2 bits)
669  * @param[in] phyAddr PHY address (5 bits)
670  * @param[in] regAddr Register address (5 bits)
671  * @return Register value
672  **/
673 
674 uint16_t lpc175xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
675  uint8_t regAddr)
676 {
677  uint16_t data;
678 
679  //Synchronization pattern
681  //Start of frame
683  //Set up a read operation
685  //Write PHY address
686  lpc175xEthWriteSmi(phyAddr, 5);
687  //Write register address
689  //Turnaround to avoid contention
691  //Read register value
692  data = lpc175xEthReadSmi(16);
693  //Force the PHY to release the MDIO pin
695 
696  //Return PHY register contents
697  return data;
698 }
699 
700 
701 /**
702  * @brief SMI write operation
703  * @param[in] data Raw data to be written
704  * @param[in] length Number of bits to be written
705  **/
706 
708 {
709  //Skip the most significant bits since they are meaningless
710  data <<= 32 - length;
711 
712  //Configure MDIO as an output
714 
715  //Write the specified number of bits
716  while(length--)
717  {
718  //Write MDIO
719  if(data & 0x80000000)
721  else
723 
724  //Assert MDC
725  usleep(1);
727  //Deassert MDC
728  usleep(1);
730 
731  //Rotate data
732  data <<= 1;
733  }
734 }
735 
736 
737 /**
738  * @brief SMI read operation
739  * @param[in] length Number of bits to be read
740  * @return Data resulting from the MDIO read operation
741  **/
742 
744 {
745  uint32_t data = 0;
746 
747  //Configure MDIO as an input
749 
750  //Read the specified number of bits
751  while(length--)
752  {
753  //Rotate data
754  data <<= 1;
755 
756  //Assert MDC
758  usleep(1);
759  //Deassert MDC
761  usleep(1);
762 
763  //Check MDIO state
765  data |= 0x00000001;
766  }
767 
768  //Return the received data
769  return data;
770 }
771 
772 
773 /**
774  * @brief CRC calculation
775  * @param[in] data Pointer to the data over which to calculate the CRC
776  * @param[in] length Number of bytes to process
777  * @return Resulting CRC value
778  **/
779 
780 uint32_t lpc175xEthCalcCrc(const void *data, size_t length)
781 {
782  uint_t i;
783  uint_t j;
784 
785  //Point to the data over which to calculate the CRC
786  const uint8_t *p = (uint8_t *) data;
787  //CRC preset value
788  uint32_t crc = 0xFFFFFFFF;
789 
790  //Loop through data
791  for(i = 0; i < length; i++)
792  {
793  //The message is processed bit by bit
794  for(j = 0; j < 8; j++)
795  {
796  //Update CRC value
797  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
798  crc = (crc << 1) ^ 0x04C11DB7;
799  else
800  crc = crc << 1;
801  }
802  }
803 
804  //Return CRC value
805  return crc;
806 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define usleep(delay)
Definition: os_port.h:127
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define TX_CTRL_SIZE
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
error_t lpc175xEthInit(NetInterface *interface)
LPC175x Ethernet MAC initialization.
const NicDriver lpc175xEthDriver
LPC175x Ethernet MAC driver.
uint8_t p
Definition: ndp.h:298
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define IPGR_DEFAULT_VALUE
void lpc175xEthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
error_t lpc175xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define COMMAND_TX_ENABLE
#define LPC175X_ETH_RX_BUFFER_SIZE
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define LPC175X_ETH_MDIO_GPIO
#define IPGT_FULL_DUPLEX
#define SMI_TA
Definition: nic.h:64
#define LPC175X_ETH_MDC_GPIO
#define SMI_START
Definition: nic.h:60
#define MAC1_SOFT_RESET
#define LPC175X_ETH_TX_BUFFER_COUNT
#define TX_CTRL_CRC
#define COMMAND_RMII
#define osExitIsr(flag)
uint16_t lpc175xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define TX_CTRL_INTERRUPT
#define RX_CTRL_INTERRUPT
#define MAC1_RESET_TX
#define MAC1_RECEIVE_ENABLE
#define SUPP_SPEED
error_t lpc175xEthReceivePacket(NetInterface *interface)
Receive a packet.
#define MAC2_FULL_DUPLEX
#define CLRT_DEFAULT_VALUE
#define FALSE
Definition: os_port.h:46
#define MAC1_SIMULATION_RESET
#define LPC175X_ETH_MDIO_MASK
void lpc175xEthEnableIrq(NetInterface *interface)
Enable interrupts.
#define LPC175X_ETH_MDC_MASK
error_t
Error codes.
Definition: error.h:42
#define COMMAND_RX_RESET
#define COMMAND_RX_ENABLE
Receive descriptor.
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define RFC_ACCEPT_BROADCAST_EN
#define txBuffer
#define LPC175X_ETH_RX_BUFFER_COUNT
#define NetInterface
Definition: net.h:36
#define INT_TX_DONE
MacAddr addr
MAC address.
Definition: ethernet.h:222
@ ERROR_INVALID_LENGTH
Definition: error.h:109
#define LPC175X_ETH_IRQ_GROUP_PRIORITY
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
OsEvent netEvent
Definition: net.c:77
#define COMMAND_TX_RESET
#define MAC1_RESET_MCS_TX
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MAC2_PAD_CRC_ENABLE
#define COMMAND_FULL_DUPLEX
#define MIN(a, b)
Definition: os_port.h:62
void lpc175xEthInitGpio(NetInterface *interface)
#define TX_CTRL_LAST
#define TX_CTRL_PAD
#define MAC1_RESET_MCS_RX
#define rxBuffer
void lpc175xEthEventHandler(NetInterface *interface)
LPC175x Ethernet MAC event handler.
#define TRACE_DEBUG(...)
Definition: debug.h:106
void lpc175xEthTick(NetInterface *interface)
LPC175x Ethernet MAC timer handler.
LPC1758 Ethernet MAC controller.
uint16_t regAddr
#define RX_STATUS_SIZE
#define ETH_MTU
Definition: ethernet.h:91
#define LPC175X_ETH_IRQ_PRIORITY_GROUPING
uint8_t n
MAC filter table entry.
Definition: ethernet.h:220
#define osEnterIsr()
#define MAC2_CRC_ENABLE
#define LPC175X_ETH_TX_BUFFER_SIZE
uint32_t lpc175xEthReadSmi(uint_t length)
SMI read operation.
#define IPGT_HALF_DUPLEX
#define LPC175X_ETH_IRQ_SUB_PRIORITY
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void lpc175xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t lpc175xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define RFC_ACCEPT_MULTICAST_HASH_EN
#define INT_RX_DONE
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
uint32_t lpc175xEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define SMI_SYNC
Definition: nic.h:59
unsigned int uint_t
Definition: compiler_port.h:45
void lpc175xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
#define COMMAND_REG_RESET
NIC driver.
Definition: nic.h:179
error_t lpc175xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void ENET_IRQHandler(void)
LPC175x Ethernet MAC interrupt service routine.
#define RFC_ACCEPT_PERFECT_EN
#define MAC1_RESET_RX
Receive status.
Transmit status.
@ NO_ERROR
Success.
Definition: error.h:44
void lpc175xEthDisableIrq(NetInterface *interface)
Disable interrupts.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
__start_packed struct @108 MacAddr
MAC address.
Transmit descriptor.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79