lpc178x_eth_driver.h
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1 /**
2  * @file lpc178x_eth_driver.h
3  * @brief LPC1786/88 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 #ifndef _LPC178X_ETH_DRIVER_H
32 #define _LPC178X_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef LPC178X_ETH_TX_BUFFER_COUNT
39  #define LPC178X_ETH_TX_BUFFER_COUNT 3
40 #elif (LPC178X_ETH_TX_BUFFER_COUNT < 1)
41  #error LPC178X_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef LPC178X_ETH_TX_BUFFER_SIZE
46  #define LPC178X_ETH_TX_BUFFER_SIZE 1536
47 #elif (LPC178X_ETH_TX_BUFFER_SIZE != 1536)
48  #error LPC178X_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef LPC178X_ETH_RX_BUFFER_COUNT
53  #define LPC178X_ETH_RX_BUFFER_COUNT 6
54 #elif (LPC178X_ETH_RX_BUFFER_COUNT < 1)
55  #error LPC178X_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef LPC178X_ETH_RX_BUFFER_SIZE
60  #define LPC178X_ETH_RX_BUFFER_SIZE 1536
61 #elif (LPC178X_ETH_RX_BUFFER_SIZE != 1536)
62  #error LPC178X_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef LPC178X_ETH_IRQ_PRIORITY_GROUPING
67  #define LPC178X_ETH_IRQ_PRIORITY_GROUPING 2
68 #elif (LPC178X_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error LPC178X_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef LPC178X_ETH_IRQ_GROUP_PRIORITY
74  #define LPC178X_ETH_IRQ_GROUP_PRIORITY 24
75 #elif (LPC178X_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error LPC178X_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef LPC178X_ETH_IRQ_SUB_PRIORITY
81  #define LPC178X_ETH_IRQ_SUB_PRIORITY 0
82 #elif (LPC178X_ETH_IRQ_SUB_PRIORITY < 0)
83  #error LPC178X_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //MAC1 register
87 #define MAC1_SOFT_RESET 0x00008000
88 #define MAC1_SIMULATION_RESET 0x00004000
89 #define MAC1_RESET_MCS_RX 0x00000800
90 #define MAC1_RESET_RX 0x00000400
91 #define MAC1_RESET_MCS_TX 0x00000200
92 #define MAC1_RESET_TX 0x00000100
93 #define MAC1_LOOPBACK 0x00000010
94 #define MAC1_TX_FLOW_CONTROL 0x00000008
95 #define MAC1_RX_FLOW_CONTROL 0x00000004
96 #define MAC1_PASS_ALL_FRAMES 0x00000002
97 #define MAC1_RECEIVE_ENABLE 0x00000001
98 
99 //MAC2 register
100 #define MAC2_EXCESS_DEFER 0x00004000
101 #define MAC2_BACK_PRESSURE_NO_BACKOFF 0x00002000
102 #define MAC2_NO_BACKOFF 0x00001000
103 #define MAC2_LONG_PREAMBLE_ENFORCEMENT 0x00000200
104 #define MAC2_PURE_PREAMBLE_ENFORCEMENT 0x00000100
105 #define MAC2_AUTO_DETECT_PAD_ENABLE 0x00000080
106 #define MAC2_VLAN_PAD_ENABLE 0x00000040
107 #define MAC2_PAD_CRC_ENABLE 0x00000020
108 #define MAC2_CRC_ENABLE 0x00000010
109 #define MAC2_DELAYED_CRC 0x00000008
110 #define MAC2_HUGE_FRAME_ENABLE 0x00000004
111 #define MAC2_FRAME_LENGTH_CHECKING 0x00000002
112 #define MAC2_FULL_DUPLEX 0x00000001
113 
114 //IPGT register
115 #define IPGT_BACK_TO_BACK_IPG 0x0000007F
116 #define IPGT_HALF_DUPLEX 0x00000012
117 #define IPGT_FULL_DUPLEX 0x00000015
118 
119 //IPGR register
120 #define IPGR_NON_BACK_TO_BACK_IPG1 0x00007F00
121 #define IPGR_NON_BACK_TO_BACK_IPG2 0x0000007F
122 #define IPGR_DEFAULT_VALUE 0x00000C12
123 
124 //CLRT register
125 #define CLRT_COLLISION_WINDOW 0x00003F00
126 #define CLRT_RETRANSMISSION_MAXIMUM 0x00003F00
127 #define CLRT_DEFAULT_VALUE 0x0000370F
128 
129 //MAXF register
130 #define MAXF_MAXIMUM_FRAME_LENGTH 0x0000FFFF
131 
132 //SUPP register
133 #define SUPP_SPEED 0x00000100
134 
135 //TEST register
136 #define TEST_BACKPRESSURE 0x00000004
137 #define TEST_PAUSE 0x00000002
138 #define TEST_SHORTCUT_PAUSE_QUANTA 0x00000001
139 
140 //MCFG register
141 #define MCFG_RESET_MII_MGMT 0x00008000
142 #define MCFG_CLOCK SELECT 0x0000003C
143 #define MCFG_SUPPRESS_PREAMBLE 0x00000002
144 #define MCFG_SCAN_INCREMENT 0x00000001
145 
146 #define MCFG_CLOCK_SELECT_DIV4 0x00000000
147 #define MCFG_CLOCK_SELECT_DIV6 0x00000008
148 #define MCFG_CLOCK_SELECT_DIV8 0x0000000C
149 #define MCFG_CLOCK_SELECT_DIV10 0x00000010
150 #define MCFG_CLOCK_SELECT_DIV14 0x00000014
151 #define MCFG_CLOCK_SELECT_DIV20 0x00000018
152 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
153 #define MCFG_CLOCK_SELECT_DIV36 0x00000020
154 #define MCFG_CLOCK_SELECT_DIV40 0x00000024
155 #define MCFG_CLOCK_SELECT_DIV44 0x00000028
156 #define MCFG_CLOCK_SELECT_DIV48 0x0000002C
157 #define MCFG_CLOCK_SELECT_DIV52 0x00000030
158 #define MCFG_CLOCK_SELECT_DIV56 0x00000034
159 #define MCFG_CLOCK_SELECT_DIV60 0x00000038
160 #define MCFG_CLOCK_SELECT_DIV64 0x0000003C
161 
162 //MCMD register
163 #define MCMD_SCAN 0x00000002
164 #define MCMD_READ 0x00000001
165 
166 //MADR register
167 #define MADR_PHY_ADDRESS 0x00001F00
168 #define MADR_REGISTER_ADDRESS 0x0000001F
169 
170 //MWTD register
171 #define MWTD_WRITE_DATA 0x0000FFFF
172 
173 //MRDD register
174 #define MRDD_READ_DATA 0x0000FFFF
175 
176 //MIND register
177 #define MIND_MII_LINK_FAIL 0x00000008
178 #define MIND_NOT_VALID 0x00000004
179 #define MIND_SCANNING 0x00000002
180 #define MIND_BUSY 0x00000001
181 
182 //Command register
183 #define COMMAND_FULL_DUPLEX 0x00000400
184 #define COMMAND_RMII 0x00000200
185 #define COMMAND_TX_FLOW_CONTROL 0x00000100
186 #define COMMAND_PASS_RX_FILTER 0x00000080
187 #define COMMAND_PASS_RUNT_FRAME 0x00000040
188 #define COMMAND_RX_RESET 0x00000020
189 #define COMMAND_TX_RESET 0x00000010
190 #define COMMAND_REG_RESET 0x00000008
191 #define COMMAND_TX_ENABLE 0x00000002
192 #define COMMAND_RX_ENABLE 0x00000001
193 
194 //Status register
195 #define STATUS_TX 0x00000002
196 #define STATUS_RX 0x00000001
197 
198 //TSV0 register
199 #define TSV0_VLAN 0x80000000
200 #define TSV0_BACKPRESSURE 0x40000000
201 #define TSV0_PAUSE 0x20000000
202 #define TSV0_CONTROL_FRAME 0x10000000
203 #define TSV0_TOTAL_BYTES 0x0FFFF000
204 #define TSV0_UNDERRUN 0x00000800
205 #define TSV0_GIANT 0x00000400
206 #define TSV0_LATE_COLLISION 0x00000200
207 #define TSV0_EXCESSIVE_COLLISION 0x00000100
208 #define TSV0_EXCESSIVE_DEFER 0x00000080
209 #define TSV0_PACKET_DEFER 0x00000040
210 #define TSV0_BROADCAST 0x00000020
211 #define TSV0_MULTICAST 0x00000010
212 #define TSV0_DONE 0x00000008
213 #define TSV0_LENGTH_OUT_OF_RANGE 0x00000004
214 #define TSV0_LENGTH_CHECK_ERROR 0x00000002
215 #define TSV0_CRC_ERROR 0x00000001
216 
217 //TSV1 register
218 #define TSV1_TRANSMIT_COLLISION_COUNT 0x000F0000
219 #define TSV1_TRANSMIT_BYTE_COUNT 0x0000FFFF
220 
221 //RSV register
222 #define RSV_VLAN 0x40000000
223 #define RSV_UNSUPPORTED_OPCODE 0x20000000
224 #define RSV_PAUSE 0x10000000
225 #define RSV_CONTROL_FRAME 0x08000000
226 #define RSV_DRIBBLE_NIBBLE 0x04000000
227 #define RSV_BROADCAST 0x02000000
228 #define RSV_MULTICAST 0x01000000
229 #define RSV_RECEIVE_OK 0x00800000
230 #define RSV_LENGTH_OUT_OF_RANGE 0x00400000
231 #define RSV_LENGTH_CHECK_ERROR 0x00200000
232 #define RSV_CRC_ERROR 0x00100000
233 #define RSV_RECEIVE_CODE_VIOLATION 0x00080000
234 #define RSV_CARRIER_EVENT_PREV_SEEN 0x00040000
235 #define RSV_RXDV_EVENT_PREV_SEEN 0x00020000
236 #define RSV_PACKET_PREVIOUSLY_IGNORED 0x00010000
237 #define RSV_RECEIVED_BYTE_COUNT 0x0000FFFF
238 
239 //FlowControlCounter register
240 #define FCC_PAUSE_TIMER 0xFFFF0000
241 #define FCC_MIRROR_COUNTER 0x0000FFFF
242 
243 //FlowControlStatus register
244 #define FCS_MIRROR_COUNTER_CURRENT 0x0000FFFF
245 
246 //RxFilterCtrl register
247 #define RFC_RX_FILTER_EN_WOL 0x00002000
248 #define RFC_MAGIC_PACKET_EN_WOL 0x00001000
249 #define RFC_ACCEPT_PERFECT_EN 0x00000020
250 #define RFC_ACCEPT_MULTICAST_HASH_EN 0x00000010
251 #define RFC_ACCEPT_UNICAST_HASH_EN 0x00000008
252 #define RFC_ACCEPT_MULTICAST_EN 0x00000004
253 #define RFC_ACCEPT_BROADCAST_EN 0x00000002
254 #define RFC_ACCEPT_UNICAST_EN 0x00000001
255 
256 //RxFilterWoLStatus and RxFilterWoLClear registers
257 #define RFWS_MAGIC_PACKET_WOL 0x00000100
258 #define RFWS_RX_FILTER_WOL 0x00000080
259 #define RFWS_ACCEPT_PERFECT_WOL 0x00000020
260 #define RFWS_ACCEPT_MULTICAST_HASH_WOL 0x00000010
261 #define RFWS_ACCEPT_UNICAST_HASH_WOL 0x00000008
262 #define RFWS_ACCEPT_MULTICAST_WOL 0x00000004
263 #define RFWS_ACCEPT_BROADCAST_WOL 0x00000002
264 #define RFWS_ACCEPT_UNICAST_WOL 0x00000001
265 
266 //IntStatus, IntEnable, IntClear and IntSet registers
267 #define INT_WAKEUP 0x00002000
268 #define INT_SOFT_INT 0x00001000
269 #define INT_TX_DONE 0x00000080
270 #define INT_TX_FINISHED 0x00000040
271 #define INT_TX_ERROR 0x00000020
272 #define INT_TX_UNDERRUN 0x00000010
273 #define INT_RX_DONE 0x00000008
274 #define INT_RX_FINISHED 0x00000004
275 #define INT_RX_ERROR 0x00000002
276 #define INT_RX_OVERRUN 0x00000001
277 
278 //Transmit descriptor control word
279 #define TX_CTRL_INTERRUPT 0x80000000
280 #define TX_CTRL_LAST 0x40000000
281 #define TX_CTRL_CRC 0x20000000
282 #define TX_CTRL_PAD 0x10000000
283 #define TX_CTRL_HUGE 0x08000000
284 #define TX_CTRL_OVERRIDE 0x04000000
285 #define TX_CTRL_SIZE 0x000007FF
286 
287 //Transmit status information word
288 #define TX_STATUS_ERROR 0x80000000
289 #define TX_STATUS_NO_DESCRIPTOR 0x40000000
290 #define TX_STATUS_UNDERRUN 0x20000000
291 #define TX_STATUS_LATE_COLLISION 0x10000000
292 #define TX_STATUS_EXCESSIVE_COLLISION 0x08000000
293 #define TX_STATUS_EXCESSIVE_DEFER 0x04000000
294 #define TX_STATUS_DEFER 0x02000000
295 #define TX_STATUS_COLLISION_COUNT 0x01E00000
296 
297 //Receive descriptor control word
298 #define RX_CTRL_INTERRUPT 0x80000000
299 #define RX_CTRL_SIZE 0x000007FF
300 
301 //Receive status information word
302 #define RX_STATUS_ERROR 0x80000000
303 #define RX_STATUS_LAST_FLAG 0x40000000
304 #define RX_STATUS_NO_DESCRIPTOR 0x20000000
305 #define RX_STATUS_OVERRUN 0x10000000
306 #define RX_STATUS_ALIGNMENT_ERROR 0x08000000
307 #define RX_STATUS_RANGE_ERROR 0x04000000
308 #define RX_STATUS_LENGTH_ERROR 0x02000000
309 #define RX_STATUS_SYMBOL_ERROR 0x01000000
310 #define RX_STATUS_CRC_ERROR 0x00800000
311 #define RX_STATUS_BROADCAST 0x00400000
312 #define RX_STATUS_MULTICAST 0x00200000
313 #define RX_STATUS_FAIL_FILTER 0x00100000
314 #define RX_STATUS_VLAN 0x00080000
315 #define RX_STATUS_CONTROL_FRAME 0x00040000
316 #define RX_STATUS_SIZE 0x000007FF
317 
318 //Receive status HashCRC word
319 #define RX_HASH_CRC_DA 0x001FF000
320 #define RX_HASH_CRC_SA 0x000001FF
321 
322 //C++ guard
323 #ifdef __cplusplus
324 extern "C" {
325 #endif
326 
327 
328 /**
329  * @brief Transmit descriptor
330  **/
331 
332 typedef struct
333 {
334  uint32_t packet;
335  uint32_t control;
336 } Lpc178xTxDesc;
337 
338 
339 /**
340  * @brief Transmit status
341  **/
342 
343 typedef struct
344 {
345  uint32_t info;
347 
348 
349 /**
350  * @brief Receive descriptor
351  **/
352 
353 typedef struct
354 {
355  uint32_t packet;
356  uint32_t control;
357 } Lpc178xRxDesc;
358 
359 
360 /**
361  * @brief Receive status
362  **/
363 
364 typedef struct
365 {
366  uint32_t info;
367  uint32_t hashCrc;
369 
370 
371 //LPC178x Ethernet MAC driver
372 extern const NicDriver lpc178xEthDriver;
373 
374 //LPC178x Ethernet MAC related functions
376 void lpc178xEthInitGpio(NetInterface *interface);
377 void lpc178xEthInitDesc(NetInterface *interface);
378 
379 void lpc178xEthTick(NetInterface *interface);
380 
381 void lpc178xEthEnableIrq(NetInterface *interface);
382 void lpc178xEthDisableIrq(NetInterface *interface);
383 void lpc178xEthEventHandler(NetInterface *interface);
384 
386  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
387 
389 
392 
393 void lpc178xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
394  uint8_t regAddr, uint16_t data);
395 
396 uint16_t lpc178xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
397  uint8_t regAddr);
398 
399 uint32_t lpc178xEthCalcCrc(const void *data, size_t length);
400 
401 //C++ guard
402 #ifdef __cplusplus
403 }
404 #endif
405 
406 #endif
uint8_t length
Definition: coap_common.h:190
void lpc178xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint8_t opcode
Definition: dns_common.h:172
void lpc178xEthEventHandler(NetInterface *interface)
LPC178x Ethernet MAC event handler.
Transmit descriptor.
uint8_t data[]
Definition: ethernet.h:209
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void lpc178xEthEnableIrq(NetInterface *interface)
Enable interrupts.
void lpc178xEthInitGpio(NetInterface *interface)
uint32_t lpc178xEthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t lpc178xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Receive status.
Transmit status.
error_t
Error codes.
Definition: error.h:42
error_t lpc178xEthReceivePacket(NetInterface *interface)
Receive a packet.
error_t lpc178xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
#define NetInterface
Definition: net.h:36
void lpc178xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
Receive descriptor.
#define NetTxAncillary
Definition: net_misc.h:36
uint16_t lpc178xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t lpc178xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void lpc178xEthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t regAddr
void lpc178xEthTick(NetInterface *interface)
LPC178x Ethernet MAC timer handler.
Network interface controller abstraction layer.
const NicDriver lpc178xEthDriver
LPC178x Ethernet MAC driver.
NIC driver.
Definition: nic.h:257
error_t lpc178xEthInit(NetInterface *interface)
LPC178x Ethernet MAC initialization.