lpc178x_eth_driver.h
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1 /**
2  * @file lpc178x_eth_driver.h
3  * @brief LPC1786/88 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _LPC178X_ETH_DRIVER_H
30 #define _LPC178X_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef LPC178X_ETH_TX_BUFFER_COUNT
37  #define LPC178X_ETH_TX_BUFFER_COUNT 3
38 #elif (LPC178X_ETH_TX_BUFFER_COUNT < 1)
39  #error LPC178X_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef LPC178X_ETH_TX_BUFFER_SIZE
44  #define LPC178X_ETH_TX_BUFFER_SIZE 1536
45 #elif (LPC178X_ETH_TX_BUFFER_SIZE != 1536)
46  #error LPC178X_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef LPC178X_ETH_RX_BUFFER_COUNT
51  #define LPC178X_ETH_RX_BUFFER_COUNT 6
52 #elif (LPC178X_ETH_RX_BUFFER_COUNT < 1)
53  #error LPC178X_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef LPC178X_ETH_RX_BUFFER_SIZE
58  #define LPC178X_ETH_RX_BUFFER_SIZE 1536
59 #elif (LPC178X_ETH_RX_BUFFER_SIZE != 1536)
60  #error LPC178X_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Interrupt priority grouping
64 #ifndef LPC178X_ETH_IRQ_PRIORITY_GROUPING
65  #define LPC178X_ETH_IRQ_PRIORITY_GROUPING 2
66 #elif (LPC178X_ETH_IRQ_PRIORITY_GROUPING < 0)
67  #error LPC178X_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
68 #endif
69 
70 //Ethernet interrupt group priority
71 #ifndef LPC178X_ETH_IRQ_GROUP_PRIORITY
72  #define LPC178X_ETH_IRQ_GROUP_PRIORITY 24
73 #elif (LPC178X_ETH_IRQ_GROUP_PRIORITY < 0)
74  #error LPC178X_ETH_IRQ_GROUP_PRIORITY parameter is not valid
75 #endif
76 
77 //Ethernet interrupt subpriority
78 #ifndef LPC178X_ETH_IRQ_SUB_PRIORITY
79  #define LPC178X_ETH_IRQ_SUB_PRIORITY 0
80 #elif (LPC178X_ETH_IRQ_SUB_PRIORITY < 0)
81  #error LPC178X_ETH_IRQ_SUB_PRIORITY parameter is not valid
82 #endif
83 
84 //MAC1 register
85 #define MAC1_SOFT_RESET 0x00008000
86 #define MAC1_SIMULATION_RESET 0x00004000
87 #define MAC1_RESET_MCS_RX 0x00000800
88 #define MAC1_RESET_RX 0x00000400
89 #define MAC1_RESET_MCS_TX 0x00000200
90 #define MAC1_RESET_TX 0x00000100
91 #define MAC1_LOOPBACK 0x00000010
92 #define MAC1_TX_FLOW_CONTROL 0x00000008
93 #define MAC1_RX_FLOW_CONTROL 0x00000004
94 #define MAC1_PASS_ALL_FRAMES 0x00000002
95 #define MAC1_RECEIVE_ENABLE 0x00000001
96 
97 //MAC2 register
98 #define MAC2_EXCESS_DEFER 0x00004000
99 #define MAC2_BACK_PRESSURE_NO_BACKOFF 0x00002000
100 #define MAC2_NO_BACKOFF 0x00001000
101 #define MAC2_LONG_PREAMBLE_ENFORCEMENT 0x00000200
102 #define MAC2_PURE_PREAMBLE_ENFORCEMENT 0x00000100
103 #define MAC2_AUTO_DETECT_PAD_ENABLE 0x00000080
104 #define MAC2_VLAN_PAD_ENABLE 0x00000040
105 #define MAC2_PAD_CRC_ENABLE 0x00000020
106 #define MAC2_CRC_ENABLE 0x00000010
107 #define MAC2_DELAYED_CRC 0x00000008
108 #define MAC2_HUGE_FRAME_ENABLE 0x00000004
109 #define MAC2_FRAME_LENGTH_CHECKING 0x00000002
110 #define MAC2_FULL_DUPLEX 0x00000001
111 
112 //IPGT register
113 #define IPGT_BACK_TO_BACK_IPG 0x0000007F
114 #define IPGT_HALF_DUPLEX 0x00000012
115 #define IPGT_FULL_DUPLEX 0x00000015
116 
117 //IPGR register
118 #define IPGR_NON_BACK_TO_BACK_IPG1 0x00007F00
119 #define IPGR_NON_BACK_TO_BACK_IPG2 0x0000007F
120 #define IPGR_DEFAULT_VALUE 0x00000C12
121 
122 //CLRT register
123 #define CLRT_COLLISION_WINDOW 0x00003F00
124 #define CLRT_RETRANSMISSION_MAXIMUM 0x00003F00
125 #define CLRT_DEFAULT_VALUE 0x0000370F
126 
127 //MAXF register
128 #define MAXF_MAXIMUM_FRAME_LENGTH 0x0000FFFF
129 
130 //SUPP register
131 #define SUPP_SPEED 0x00000100
132 
133 //TEST register
134 #define TEST_BACKPRESSURE 0x00000004
135 #define TEST_PAUSE 0x00000002
136 #define TEST_SHORTCUT_PAUSE_QUANTA 0x00000001
137 
138 //MCFG register
139 #define MCFG_RESET_MII_MGMT 0x00008000
140 #define MCFG_CLOCK SELECT 0x0000003C
141 #define MCFG_SUPPRESS_PREAMBLE 0x00000002
142 #define MCFG_SCAN_INCREMENT 0x00000001
143 
144 #define MCFG_CLOCK_SELECT_DIV4 0x00000000
145 #define MCFG_CLOCK_SELECT_DIV6 0x00000008
146 #define MCFG_CLOCK_SELECT_DIV8 0x0000000C
147 #define MCFG_CLOCK_SELECT_DIV10 0x00000010
148 #define MCFG_CLOCK_SELECT_DIV14 0x00000014
149 #define MCFG_CLOCK_SELECT_DIV20 0x00000018
150 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
151 #define MCFG_CLOCK_SELECT_DIV36 0x00000020
152 #define MCFG_CLOCK_SELECT_DIV40 0x00000024
153 #define MCFG_CLOCK_SELECT_DIV44 0x00000028
154 #define MCFG_CLOCK_SELECT_DIV48 0x0000002C
155 #define MCFG_CLOCK_SELECT_DIV52 0x00000030
156 #define MCFG_CLOCK_SELECT_DIV56 0x00000034
157 #define MCFG_CLOCK_SELECT_DIV60 0x00000038
158 #define MCFG_CLOCK_SELECT_DIV64 0x0000003C
159 
160 //MCMD register
161 #define MCMD_SCAN 0x00000002
162 #define MCMD_READ 0x00000001
163 
164 //MADR register
165 #define MADR_PHY_ADDRESS 0x00001F00
166 #define MADR_REGISTER_ADDRESS 0x0000001F
167 
168 //MWTD register
169 #define MWTD_WRITE_DATA 0x0000FFFF
170 
171 //MRDD register
172 #define MRDD_READ_DATA 0x0000FFFF
173 
174 //MIND register
175 #define MIND_MII_LINK_FAIL 0x00000008
176 #define MIND_NOT_VALID 0x00000004
177 #define MIND_SCANNING 0x00000002
178 #define MIND_BUSY 0x00000001
179 
180 //Command register
181 #define COMMAND_FULL_DUPLEX 0x00000400
182 #define COMMAND_RMII 0x00000200
183 #define COMMAND_TX_FLOW_CONTROL 0x00000100
184 #define COMMAND_PASS_RX_FILTER 0x00000080
185 #define COMMAND_PASS_RUNT_FRAME 0x00000040
186 #define COMMAND_RX_RESET 0x00000020
187 #define COMMAND_TX_RESET 0x00000010
188 #define COMMAND_REG_RESET 0x00000008
189 #define COMMAND_TX_ENABLE 0x00000002
190 #define COMMAND_RX_ENABLE 0x00000001
191 
192 //Status register
193 #define STATUS_TX 0x00000002
194 #define STATUS_RX 0x00000001
195 
196 //TSV0 register
197 #define TSV0_VLAN 0x80000000
198 #define TSV0_BACKPRESSURE 0x40000000
199 #define TSV0_PAUSE 0x20000000
200 #define TSV0_CONTROL_FRAME 0x10000000
201 #define TSV0_TOTAL_BYTES 0x0FFFF000
202 #define TSV0_UNDERRUN 0x00000800
203 #define TSV0_GIANT 0x00000400
204 #define TSV0_LATE_COLLISION 0x00000200
205 #define TSV0_EXCESSIVE_COLLISION 0x00000100
206 #define TSV0_EXCESSIVE_DEFER 0x00000080
207 #define TSV0_PACKET_DEFER 0x00000040
208 #define TSV0_BROADCAST 0x00000020
209 #define TSV0_MULTICAST 0x00000010
210 #define TSV0_DONE 0x00000008
211 #define TSV0_LENGTH_OUT_OF_RANGE 0x00000004
212 #define TSV0_LENGTH_CHECK_ERROR 0x00000002
213 #define TSV0_CRC_ERROR 0x00000001
214 
215 //TSV1 register
216 #define TSV1_TRANSMIT_COLLISION_COUNT 0x000F0000
217 #define TSV1_TRANSMIT_BYTE_COUNT 0x0000FFFF
218 
219 //RSV register
220 #define RSV_VLAN 0x40000000
221 #define RSV_UNSUPPORTED_OPCODE 0x20000000
222 #define RSV_PAUSE 0x10000000
223 #define RSV_CONTROL_FRAME 0x08000000
224 #define RSV_DRIBBLE_NIBBLE 0x04000000
225 #define RSV_BROADCAST 0x02000000
226 #define RSV_MULTICAST 0x01000000
227 #define RSV_RECEIVE_OK 0x00800000
228 #define RSV_LENGTH_OUT_OF_RANGE 0x00400000
229 #define RSV_LENGTH_CHECK_ERROR 0x00200000
230 #define RSV_CRC_ERROR 0x00100000
231 #define RSV_RECEIVE_CODE_VIOLATION 0x00080000
232 #define RSV_CARRIER_EVENT_PREV_SEEN 0x00040000
233 #define RSV_RXDV_EVENT_PREV_SEEN 0x00020000
234 #define RSV_PACKET_PREVIOUSLY_IGNORED 0x00010000
235 #define RSV_RECEIVED_BYTE_COUNT 0x0000FFFF
236 
237 //FlowControlCounter register
238 #define FCC_PAUSE_TIMER 0xFFFF0000
239 #define FCC_MIRROR_COUNTER 0x0000FFFF
240 
241 //FlowControlStatus register
242 #define FCS_MIRROR_COUNTER_CURRENT 0x0000FFFF
243 
244 //RxFilterCtrl register
245 #define RFC_RX_FILTER_EN_WOL 0x00002000
246 #define RFC_MAGIC_PACKET_EN_WOL 0x00001000
247 #define RFC_ACCEPT_PERFECT_EN 0x00000020
248 #define RFC_ACCEPT_MULTICAST_HASH_EN 0x00000010
249 #define RFC_ACCEPT_UNICAST_HASH_EN 0x00000008
250 #define RFC_ACCEPT_MULTICAST_EN 0x00000004
251 #define RFC_ACCEPT_BROADCAST_EN 0x00000002
252 #define RFC_ACCEPT_UNICAST_EN 0x00000001
253 
254 //RxFilterWoLStatus and RxFilterWoLClear registers
255 #define RFWS_MAGIC_PACKET_WOL 0x00000100
256 #define RFWS_RX_FILTER_WOL 0x00000080
257 #define RFWS_ACCEPT_PERFECT_WOL 0x00000020
258 #define RFWS_ACCEPT_MULTICAST_HASH_WOL 0x00000010
259 #define RFWS_ACCEPT_UNICAST_HASH_WOL 0x00000008
260 #define RFWS_ACCEPT_MULTICAST_WOL 0x00000004
261 #define RFWS_ACCEPT_BROADCAST_WOL 0x00000002
262 #define RFWS_ACCEPT_UNICAST_WOL 0x00000001
263 
264 //IntStatus, IntEnable, IntClear and IntSet registers
265 #define INT_WAKEUP 0x00002000
266 #define INT_SOFT_INT 0x00001000
267 #define INT_TX_DONE 0x00000080
268 #define INT_TX_FINISHED 0x00000040
269 #define INT_TX_ERROR 0x00000020
270 #define INT_TX_UNDERRUN 0x00000010
271 #define INT_RX_DONE 0x00000008
272 #define INT_RX_FINISHED 0x00000004
273 #define INT_RX_ERROR 0x00000002
274 #define INT_RX_OVERRUN 0x00000001
275 
276 //Transmit descriptor control word
277 #define TX_CTRL_INTERRUPT 0x80000000
278 #define TX_CTRL_LAST 0x40000000
279 #define TX_CTRL_CRC 0x20000000
280 #define TX_CTRL_PAD 0x10000000
281 #define TX_CTRL_HUGE 0x08000000
282 #define TX_CTRL_OVERRIDE 0x04000000
283 #define TX_CTRL_SIZE 0x000007FF
284 
285 //Transmit status information word
286 #define TX_STATUS_ERROR 0x80000000
287 #define TX_STATUS_NO_DESCRIPTOR 0x40000000
288 #define TX_STATUS_UNDERRUN 0x20000000
289 #define TX_STATUS_LATE_COLLISION 0x10000000
290 #define TX_STATUS_EXCESSIVE_COLLISION 0x08000000
291 #define TX_STATUS_EXCESSIVE_DEFER 0x04000000
292 #define TX_STATUS_DEFER 0x02000000
293 #define TX_STATUS_COLLISION_COUNT 0x01E00000
294 
295 //Receive descriptor control word
296 #define RX_CTRL_INTERRUPT 0x80000000
297 #define RX_CTRL_SIZE 0x000007FF
298 
299 //Receive status information word
300 #define RX_STATUS_ERROR 0x80000000
301 #define RX_STATUS_LAST_FLAG 0x40000000
302 #define RX_STATUS_NO_DESCRIPTOR 0x20000000
303 #define RX_STATUS_OVERRUN 0x10000000
304 #define RX_STATUS_ALIGNMENT_ERROR 0x08000000
305 #define RX_STATUS_RANGE_ERROR 0x04000000
306 #define RX_STATUS_LENGTH_ERROR 0x02000000
307 #define RX_STATUS_SYMBOL_ERROR 0x01000000
308 #define RX_STATUS_CRC_ERROR 0x00800000
309 #define RX_STATUS_BROADCAST 0x00400000
310 #define RX_STATUS_MULTICAST 0x00200000
311 #define RX_STATUS_FAIL_FILTER 0x00100000
312 #define RX_STATUS_VLAN 0x00080000
313 #define RX_STATUS_CONTROL_FRAME 0x00040000
314 #define RX_STATUS_SIZE 0x000007FF
315 
316 //Receive status HashCRC word
317 #define RX_HASH_CRC_DA 0x001FF000
318 #define RX_HASH_CRC_SA 0x000001FF
319 
320 //C++ guard
321 #ifdef __cplusplus
322  extern "C" {
323 #endif
324 
325 
326 /**
327  * @brief Transmit descriptor
328  **/
329 
330 typedef struct
331 {
332  uint32_t packet;
333  uint32_t control;
334 } Lpc178xTxDesc;
335 
336 
337 /**
338  * @brief Transmit status
339  **/
340 
341 typedef struct
342 {
343  uint32_t info;
345 
346 
347 /**
348  * @brief Receive descriptor
349  **/
350 
351 typedef struct
352 {
353  uint32_t packet;
354  uint32_t control;
355 } Lpc178xRxDesc;
356 
357 
358 /**
359  * @brief Receive status
360  **/
361 
362 typedef struct
363 {
364  uint32_t info;
365  uint32_t hashCrc;
367 
368 
369 //LPC178x Ethernet MAC driver
370 extern const NicDriver lpc178xEthDriver;
371 
372 //LPC178x Ethernet MAC related functions
374 void lpc178xEthInitGpio(NetInterface *interface);
375 void lpc178xEthInitDesc(NetInterface *interface);
376 
377 void lpc178xEthTick(NetInterface *interface);
378 
379 void lpc178xEthEnableIrq(NetInterface *interface);
380 void lpc178xEthDisableIrq(NetInterface *interface);
381 void lpc178xEthEventHandler(NetInterface *interface);
382 
384  const NetBuffer *buffer, size_t offset);
385 
387 
390 
391 void lpc178xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
392 uint16_t lpc178xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
393 
394 uint32_t lpc178xEthCalcCrc(const void *data, size_t length);
395 
396 //C++ guard
397 #ifdef __cplusplus
398  }
399 #endif
400 
401 #endif
void lpc178xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
uint32_t lpc178xEthCalcCrc(const void *data, size_t length)
CRC calculation.
void lpc178xEthDisableIrq(NetInterface *interface)
Disable interrupts.
void lpc178xEthTick(NetInterface *interface)
LPC178x Ethernet MAC timer handler.
error_t lpc178xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void lpc178xEthEventHandler(NetInterface *interface)
LPC178x Ethernet MAC event handler.
error_t lpc178xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t lpc178xEthInit(NetInterface *interface)
LPC178x Ethernet MAC initialization.
Transmit descriptor.
error_t lpc178xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
uint16_t regAddr
uint16_t lpc178xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void lpc178xEthEnableIrq(NetInterface *interface)
Enable interrupts.
const NicDriver lpc178xEthDriver
LPC178x Ethernet MAC driver.
error_t
Error codes.
Definition: error.h:40
Receive status.
Transmit status.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void lpc178xEthInitGpio(NetInterface *interface)
error_t lpc178xEthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t length
Definition: dtls_misc.h:140
Receive descriptor.
void lpc178xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Network interface controller abstraction layer.