lpc178x_eth_driver.c
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1 /**
2  * @file lpc178x_eth_driver.c
3  * @brief LPC1786/88 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "lpc177x_8x.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit descriptors
53 #pragma data_alignment = 4
55 //Transmit status array
56 #pragma data_alignment = 4
58 //Receive descriptors
59 #pragma data_alignment = 4
61 //Receive status array
62 #pragma data_alignment = 8
64 
65 //Keil MDK-ARM or GCC compiler?
66 #else
67 
68 //Transmit buffer
70  __attribute__((aligned(4)));
71 //Receive buffer
73  __attribute__((aligned(4)));
74 //Transmit descriptors
76  __attribute__((aligned(4)));
77 //Transmit status array
79  __attribute__((aligned(4)));
80 //Receive descriptors
82  __attribute__((aligned(4)));
83 //Receive status array
85  __attribute__((aligned(8)));
86 
87 #endif
88 
89 
90 /**
91  * @brief LPC178x Ethernet MAC driver
92  **/
93 
95 {
97  ETH_MTU,
108  TRUE,
109  TRUE,
110  TRUE,
111  FALSE
112 };
113 
114 
115 /**
116  * @brief LPC178x Ethernet MAC initialization
117  * @param[in] interface Underlying network interface
118  * @return Error code
119  **/
120 
122 {
123  error_t error;
124 
125  //Debug message
126  TRACE_INFO("Initializing LPC178x Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Power up EMAC controller
132  LPC_SC->PCONP |= PCONP_PCENET;
133 
134  //GPIO configuration
135  lpc178xEthInitGpio(interface);
136 
137  //Reset host registers, transmit datapath and receive datapath
138  LPC_EMAC->Command = COMMAND_RX_RESET | COMMAND_TX_RESET | COMMAND_REG_RESET;
139 
140  //Reset EMAC controller
141  LPC_EMAC->MAC1 = MAC1_SOFT_RESET | MAC1_SIMULATION_RESET |
143 
144  //Initialize MAC related registers
145  LPC_EMAC->MAC1 = 0;
146  LPC_EMAC->MAC2 = MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE;
147  LPC_EMAC->IPGR = IPGR_DEFAULT_VALUE;
148  LPC_EMAC->CLRT = CLRT_DEFAULT_VALUE;
149 
150  //Select RMII mode
151  LPC_EMAC->Command = COMMAND_RMII;
152 
153  //Configure MDC clock
154  LPC_EMAC->MCFG = MCFG_CLOCK_SELECT_DIV48;
155  //Reset MII management interface
156  LPC_EMAC->MCFG |= MCFG_RESET_MII_MGMT;
157  LPC_EMAC->MCFG &= ~MCFG_RESET_MII_MGMT;
158 
159  //PHY transceiver initialization
160  error = interface->phyDriver->init(interface);
161  //Failed to initialize PHY transceiver?
162  if(error)
163  return error;
164 
165  //Initialize TX and RX descriptor arrays
166  lpc178xEthInitDesc(interface);
167 
168  //Set the MAC address of the station
169  LPC_EMAC->SA0 = interface->macAddr.w[2];
170  LPC_EMAC->SA1 = interface->macAddr.w[1];
171  LPC_EMAC->SA2 = interface->macAddr.w[0];
172 
173  //Initialize hash table
174  LPC_EMAC->HashFilterL = 0;
175  LPC_EMAC->HashFilterH = 0;
176 
177  //Configure the receive filter
178  LPC_EMAC->RxFilterCtrl = RFC_ACCEPT_PERFECT_EN |
180 
181  //Program the MAXF register with the maximum frame length to be accepted
182  LPC_EMAC->MAXF = LPC178X_ETH_RX_BUFFER_SIZE;
183 
184  //Reset EMAC interrupt flags
185  LPC_EMAC->IntClear = 0xFFFF;
186  //Enable desired EMAC interrupts
187  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
188 
189  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
190  NVIC_SetPriorityGrouping(LPC178X_ETH_IRQ_PRIORITY_GROUPING);
191 
192  //Configure Ethernet interrupt priority
193  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(LPC178X_ETH_IRQ_PRIORITY_GROUPING,
195 
196  //Enable transmission and reception
197  LPC_EMAC->Command |= COMMAND_TX_ENABLE | COMMAND_RX_ENABLE;
198  //Allow frames to be received
199  LPC_EMAC->MAC1 |= MAC1_RECEIVE_ENABLE;
200 
201  //Accept any packets from the upper layer
202  osSetEvent(&interface->nicTxEvent);
203 
204  //Successful initialization
205  return NO_ERROR;
206 }
207 
208 
209 //LPC1788-32 Developer's Kit?
210 #if defined(USE_LPC1788_32_DEV_KIT)
211 
212 /**
213  * @brief GPIO configuration
214  * @param[in] interface Underlying network interface
215  **/
216 
217 void lpc178xEthInitGpio(NetInterface *interface)
218 {
219  //Power up GPIO
220  LPC_SC->PCONP |= PCONP_PCGPIO;
221 
222  //Configure P1.0 (ENET_TXD0)
223  LPC_IOCON->P1_0 = IOCON_SLEW | IOCON_FUNC_1;
224  //Configure P1.1 (ENET_TXD1)
225  LPC_IOCON->P1_1 = IOCON_SLEW | IOCON_FUNC_1;
226  //Configure P1.4 (ENET_TX_EN)
227  LPC_IOCON->P1_4 = IOCON_SLEW | IOCON_FUNC_1;
228  //Configure P1.8 (ENET_CRS)
229  LPC_IOCON->P1_8 = IOCON_SLEW | IOCON_FUNC_1;
230  //Configure P1.9 (ENET_RXD0)
231  LPC_IOCON->P1_9 = IOCON_SLEW | IOCON_FUNC_1;
232  //Configure P1.10 (ENET_RXD1)
233  LPC_IOCON->P1_10 = IOCON_SLEW | IOCON_FUNC_1;
234  //Configure P1.14 (RX_ER)
235  LPC_IOCON->P1_14 = IOCON_SLEW | IOCON_FUNC_1;
236  //Configure P1.15 (ENET_REF_CLK)
237  LPC_IOCON->P1_15 = IOCON_SLEW | IOCON_FUNC_1;
238  //Configure P1.16 (ENET_MDC)
239  LPC_IOCON->P1_16 = IOCON_MODE_PULL_UP | IOCON_FUNC_1;
240  //Configure P1.17 (ENET_MDIO)
241  LPC_IOCON->P1_17 = IOCON_MODE_PULL_UP | IOCON_FUNC_1;
242 }
243 
244 #endif
245 
246 
247 /**
248  * @brief Initialize TX and RX descriptors
249  * @param[in] interface Underlying network interface
250  **/
251 
253 {
254  uint_t i;
255 
256  //Initialize TX descriptors
257  for(i = 0; i < LPC178X_ETH_TX_BUFFER_COUNT; i++)
258  {
259  //Base address of the buffer containing transmit data
260  txDesc[i].packet = (uint32_t) txBuffer[i];
261  //Transmit descriptor control word
262  txDesc[i].control = 0;
263  //Transmit status information word
264  txStatus[i].info = 0;
265  }
266 
267  //Initialize RX descriptors
268  for(i = 0; i < LPC178X_ETH_RX_BUFFER_COUNT; i++)
269  {
270  //Base address of the buffer for storing receive data
271  rxDesc[i].packet = (uint32_t) rxBuffer[i];
272  //Receive descriptor control word
274  //Receive status information word
275  rxStatus[i].info = 0;
276  //Receive status HashCRC word
277  rxStatus[i].hashCrc = 0;
278  }
279 
280  //Initialize EMAC transmit descriptor registers
281  LPC_EMAC->TxDescriptor = (uint32_t) txDesc;
282  LPC_EMAC->TxStatus = (uint32_t) txStatus;
283  LPC_EMAC->TxDescriptorNumber = LPC178X_ETH_TX_BUFFER_COUNT - 1;
284  LPC_EMAC->TxProduceIndex = 0;
285 
286  //Initialize EMAC receive descriptor registers
287  LPC_EMAC->RxDescriptor = (uint32_t) rxDesc;
288  LPC_EMAC->RxStatus = (uint32_t) rxStatus;
289  LPC_EMAC->RxDescriptorNumber = LPC178X_ETH_RX_BUFFER_COUNT - 1;
290  LPC_EMAC->RxConsumeIndex = 0;
291 }
292 
293 
294 /**
295  * @brief LPC178x Ethernet MAC timer handler
296  *
297  * This routine is periodically called by the TCP/IP stack to
298  * handle periodic operations such as polling the link state
299  *
300  * @param[in] interface Underlying network interface
301  **/
302 
303 void lpc178xEthTick(NetInterface *interface)
304 {
305  //Handle periodic operations
306  interface->phyDriver->tick(interface);
307 }
308 
309 
310 /**
311  * @brief Enable interrupts
312  * @param[in] interface Underlying network interface
313  **/
314 
316 {
317  //Enable Ethernet MAC interrupts
318  NVIC_EnableIRQ(ENET_IRQn);
319  //Enable Ethernet PHY interrupts
320  interface->phyDriver->enableIrq(interface);
321 }
322 
323 
324 /**
325  * @brief Disable interrupts
326  * @param[in] interface Underlying network interface
327  **/
328 
330 {
331  //Disable Ethernet MAC interrupts
332  NVIC_DisableIRQ(ENET_IRQn);
333  //Disable Ethernet PHY interrupts
334  interface->phyDriver->disableIrq(interface);
335 }
336 
337 
338 /**
339  * @brief LPC178x Ethernet MAC interrupt service routine
340  **/
341 
342 void ENET_IRQHandler(void)
343 {
344  uint_t i;
345  bool_t flag;
346  uint32_t status;
347 
348  //Interrupt service routine prologue
349  osEnterIsr();
350 
351  //This flag will be set if a higher priority task must be woken
352  flag = FALSE;
353 
354  //Read interrupt status register
355  status = LPC_EMAC->IntStatus;
356 
357  //A packet has been transmitted?
358  if(status & INT_TX_DONE)
359  {
360  //Clear TxDone interrupt flag
361  LPC_EMAC->IntClear = INT_TX_DONE;
362 
363  //Get the index of the next descriptor
364  i = LPC_EMAC->TxProduceIndex + 1;
365 
366  //Wrap around if necessary
368  i = 0;
369 
370  //Check whether the TX buffer is available for writing
371  if(i != LPC_EMAC->TxConsumeIndex)
372  {
373  //Notify the TCP/IP stack that the transmitter is ready to send
374  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
375  }
376  }
377 
378  //A packet has been received?
379  if(status & INT_RX_DONE)
380  {
381  //Disable RxDone interrupts
382  LPC_EMAC->IntEnable &= ~INT_RX_DONE;
383 
384  //Set event flag
385  nicDriverInterface->nicEvent = TRUE;
386  //Notify the TCP/IP stack of the event
387  flag |= osSetEventFromIsr(&netEvent);
388  }
389 
390  //Interrupt service routine epilogue
391  osExitIsr(flag);
392 }
393 
394 
395 /**
396  * @brief LPC178x Ethernet MAC event handler
397  * @param[in] interface Underlying network interface
398  **/
399 
401 {
402  error_t error;
403 
404  //Packet received?
405  if(LPC_EMAC->IntStatus & INT_RX_DONE)
406  {
407  //Clear RxDone interrupt flag
408  LPC_EMAC->IntClear = INT_RX_DONE;
409 
410  //Process all pending packets
411  do
412  {
413  //Read incoming packet
414  error = lpc178xEthReceivePacket(interface);
415 
416  //No more data in the receive buffer?
417  } while(error != ERROR_BUFFER_EMPTY);
418  }
419 
420  //Re-enable TxDone and RxDone interrupts
421  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
422 }
423 
424 
425 /**
426  * @brief Send a packet
427  * @param[in] interface Underlying network interface
428  * @param[in] buffer Multi-part buffer containing the data to send
429  * @param[in] offset Offset to the first data byte
430  * @return Error code
431  **/
432 
434  const NetBuffer *buffer, size_t offset)
435 {
436  uint_t i;
437  uint_t j;
438  size_t length;
439 
440  //Retrieve the length of the packet
441  length = netBufferGetLength(buffer) - offset;
442 
443  //Check the frame length
444  if(!length)
445  {
446  //The transmitter can accept another packet
447  osSetEvent(&interface->nicTxEvent);
448  //We are done since the buffer is empty
449  return NO_ERROR;
450  }
452  {
453  //The transmitter can accept another packet
454  osSetEvent(&interface->nicTxEvent);
455  //Report an error
456  return ERROR_INVALID_LENGTH;
457  }
458 
459  //Get the index of the current descriptor
460  i = LPC_EMAC->TxProduceIndex;
461  //Get the index of the next descriptor
462  j = i + 1;
463 
464  //Wrap around if necessary
466  j = 0;
467 
468  //Check whether the transmit descriptor array is full
469  if(j == LPC_EMAC->TxConsumeIndex)
470  return ERROR_FAILURE;
471 
472  //Copy user data to the transmit buffer
473  netBufferRead((uint8_t *) txDesc[i].packet, buffer, offset, length);
474 
475  //Write the transmit control word
476  txDesc[i].control = TX_CTRL_INTERRUPT | TX_CTRL_LAST |
478 
479  //Increment index and wrap around if necessary
480  if(++i >= LPC178X_ETH_TX_BUFFER_COUNT)
481  i = 0;
482 
483  //Save the resulting value
484  LPC_EMAC->TxProduceIndex = i;
485 
486  //Get the index of the next descriptor
487  j = i + 1;
488 
489  //Wrap around if necessary
491  j = 0;
492 
493  //Check whether the next buffer is available for writing
494  if(j != LPC_EMAC->TxConsumeIndex)
495  {
496  //The transmitter can accept another packet
497  osSetEvent(&interface->nicTxEvent);
498  }
499 
500  //Successful write operation
501  return NO_ERROR;
502 }
503 
504 
505 /**
506  * @brief Receive a packet
507  * @param[in] interface Underlying network interface
508  * @return Error code
509  **/
510 
512 {
513  error_t error;
514  size_t n;
515  uint_t i;
516 
517  //Point to the current descriptor
518  i = LPC_EMAC->RxConsumeIndex;
519 
520  //Make sure the current buffer is available for reading
521  if(i != LPC_EMAC->RxProduceIndex)
522  {
523  //Retrieve the length of the frame
524  n = (rxStatus[i].info & RX_STATUS_SIZE) + 1;
525  //Limit the number of data to read
527 
528  //Pass the packet to the upper layer
529  nicProcessPacket(interface, (uint8_t *) rxDesc[i].packet, n);
530 
531  //Increment index and wrap around if necessary
532  if(++i >= LPC178X_ETH_RX_BUFFER_COUNT)
533  i = 0;
534 
535  //Save the resulting value
536  LPC_EMAC->RxConsumeIndex = i;
537 
538  //Valid packet received
539  error = NO_ERROR;
540  }
541  else
542  {
543  //No more data in the receive buffer
544  error = ERROR_BUFFER_EMPTY;
545  }
546 
547  //Return status code
548  return error;
549 }
550 
551 
552 /**
553  * @brief Configure MAC address filtering
554  * @param[in] interface Underlying network interface
555  * @return Error code
556  **/
557 
559 {
560  uint_t i;
561  uint_t k;
562  uint32_t crc;
563  uint32_t hashTable[2];
564  MacFilterEntry *entry;
565 
566  //Debug message
567  TRACE_DEBUG("Updating MAC filter...\r\n");
568 
569  //Set the MAC address of the station
570  LPC_EMAC->SA0 = interface->macAddr.w[2];
571  LPC_EMAC->SA1 = interface->macAddr.w[1];
572  LPC_EMAC->SA2 = interface->macAddr.w[0];
573 
574  //Clear hash table
575  hashTable[0] = 0;
576  hashTable[1] = 0;
577 
578  //The MAC address filter contains the list of MAC addresses to accept
579  //when receiving an Ethernet frame
580  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
581  {
582  //Point to the current entry
583  entry = &interface->macAddrFilter[i];
584 
585  //Valid entry?
586  if(entry->refCount > 0)
587  {
588  //Compute CRC over the current MAC address
589  crc = lpc178xEthCalcCrc(&entry->addr, sizeof(MacAddr));
590  //Bits [28:23] are used to form the hash
591  k = (crc >> 23) & 0x3F;
592  //Update hash table contents
593  hashTable[k / 32] |= (1 << (k % 32));
594  }
595  }
596 
597  //Write the hash table
598  LPC_EMAC->HashFilterL = hashTable[0];
599  LPC_EMAC->HashFilterH = hashTable[1];
600 
601  //Debug message
602  TRACE_DEBUG(" HashFilterL = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterL);
603  TRACE_DEBUG(" HashFilterH = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterH);
604 
605  //Successful processing
606  return NO_ERROR;
607 }
608 
609 
610 /**
611  * @brief Adjust MAC configuration parameters for proper operation
612  * @param[in] interface Underlying network interface
613  * @return Error code
614  **/
615 
617 {
618  //10BASE-T or 100BASE-TX operation mode?
619  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
620  LPC_EMAC->SUPP = SUPP_SPEED;
621  else
622  LPC_EMAC->SUPP = 0;
623 
624  //Half-duplex or full-duplex mode?
625  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
626  {
627  //The MAC operates in full-duplex mode
628  LPC_EMAC->MAC2 |= MAC2_FULL_DUPLEX;
629  LPC_EMAC->Command |= COMMAND_FULL_DUPLEX;
630  //Configure Back-to-Back Inter-Packet Gap
631  LPC_EMAC->IPGT = IPGT_FULL_DUPLEX;
632  }
633  else
634  {
635  //The MAC operates in half-duplex mode
636  LPC_EMAC->MAC2 &= ~MAC2_FULL_DUPLEX;
637  LPC_EMAC->Command &= ~COMMAND_FULL_DUPLEX;
638  //Configure Back-to-Back Inter-Packet Gap
639  LPC_EMAC->IPGT = IPGT_HALF_DUPLEX;
640  }
641 
642  //Successful processing
643  return NO_ERROR;
644 }
645 
646 
647 /**
648  * @brief Write PHY register
649  * @param[in] opcode Access type (2 bits)
650  * @param[in] phyAddr PHY address (5 bits)
651  * @param[in] regAddr Register address (5 bits)
652  * @param[in] data Register value
653  **/
654 
655 void lpc178xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
656  uint8_t regAddr, uint16_t data)
657 {
658  //Valid opcode?
659  if(opcode == SMI_OPCODE_WRITE)
660  {
661  //Clear MCMD register
662  LPC_EMAC->MCMD = 0;
663 
664  //PHY address
665  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
666  //Register address
667  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
668  //Data to be written in the PHY register
669  LPC_EMAC->MWTD = data & MWTD_WRITE_DATA;
670 
671  //Wait for the write to complete
672  while(LPC_EMAC->MIND & MIND_BUSY)
673  {
674  }
675  }
676  else
677  {
678  //The MAC peripheral only supports standard Clause 22 opcodes
679  }
680 }
681 
682 
683 /**
684  * @brief Read PHY register
685  * @param[in] opcode Access type (2 bits)
686  * @param[in] phyAddr PHY address (5 bits)
687  * @param[in] regAddr Register address (5 bits)
688  * @return Register value
689  **/
690 
691 uint16_t lpc178xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
692  uint8_t regAddr)
693 {
694  uint16_t data;
695 
696  //Valid opcode?
697  if(opcode == SMI_OPCODE_READ)
698  {
699  //PHY address
700  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
701  //Register address
702  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
703 
704  //Start a read operation
705  LPC_EMAC->MCMD = MCMD_READ;
706  //Wait for the read to complete
707  while(LPC_EMAC->MIND & MIND_BUSY)
708  {
709  }
710 
711  //Clear MCMD register
712  LPC_EMAC->MCMD = 0;
713 
714  //Get register value
715  data = LPC_EMAC->MRDD & MRDD_READ_DATA;
716  }
717  else
718  {
719  //The MAC peripheral only supports standard Clause 22 opcodes
720  data = 0;
721  }
722 
723  //Return the value of the PHY register
724  return data;
725 }
726 
727 
728 /**
729  * @brief CRC calculation
730  * @param[in] data Pointer to the data over which to calculate the CRC
731  * @param[in] length Number of bytes to process
732  * @return Resulting CRC value
733  **/
734 
735 uint32_t lpc178xEthCalcCrc(const void *data, size_t length)
736 {
737  uint_t i;
738  uint_t j;
739 
740  //Point to the data over which to calculate the CRC
741  const uint8_t *p = (uint8_t *) data;
742  //CRC preset value
743  uint32_t crc = 0xFFFFFFFF;
744 
745  //Loop through data
746  for(i = 0; i < length; i++)
747  {
748  //The message is processed bit by bit
749  for(j = 0; j < 8; j++)
750  {
751  //Update CRC value
752  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
753  crc = (crc << 1) ^ 0x04C11DB7;
754  else
755  crc = crc << 1;
756  }
757  }
758 
759  //Return CRC value
760  return crc;
761 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define MADR_PHY_ADDRESS
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define TX_CTRL_SIZE
Transmit descriptor.
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define LPC178X_ETH_TX_BUFFER_SIZE
LPC1786/88 Ethernet MAC controller.
uint8_t p
Definition: ndp.h:298
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define IPGR_DEFAULT_VALUE
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
void lpc178xEthInitGpio(NetInterface *interface)
#define COMMAND_TX_ENABLE
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define LPC178X_ETH_IRQ_PRIORITY_GROUPING
const NicDriver lpc178xEthDriver
LPC178x Ethernet MAC driver.
#define LPC178X_ETH_TX_BUFFER_COUNT
#define IPGT_FULL_DUPLEX
void lpc178xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define MAC1_SOFT_RESET
#define TX_CTRL_CRC
#define COMMAND_RMII
#define osExitIsr(flag)
#define TX_CTRL_INTERRUPT
uint16_t lpc178xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define RX_CTRL_INTERRUPT
Receive status.
Transmit status.
#define MAC1_RESET_TX
#define MAC1_RECEIVE_ENABLE
#define SUPP_SPEED
#define MWTD_WRITE_DATA
#define MAC2_FULL_DUPLEX
#define CLRT_DEFAULT_VALUE
#define FALSE
Definition: os_port.h:46
#define LPC178X_ETH_IRQ_GROUP_PRIORITY
#define MAC1_SIMULATION_RESET
void lpc178xEthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t
Error codes.
Definition: error.h:42
#define COMMAND_RX_RESET
#define COMMAND_RX_ENABLE
#define LPC178X_ETH_RX_BUFFER_SIZE
uint32_t lpc178xEthCalcCrc(const void *data, size_t length)
CRC calculation.
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define RFC_ACCEPT_BROADCAST_EN
#define txBuffer
#define NetInterface
Definition: net.h:36
#define INT_TX_DONE
MacAddr addr
MAC address.
Definition: ethernet.h:222
@ ERROR_INVALID_LENGTH
Definition: error.h:109
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
Receive descriptor.
OsEvent netEvent
Definition: net.c:77
#define SMI_OPCODE_READ
Definition: nic.h:63
#define COMMAND_TX_RESET
#define MAC1_RESET_MCS_TX
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MAC2_PAD_CRC_ENABLE
#define COMMAND_FULL_DUPLEX
#define MIN(a, b)
Definition: os_port.h:62
#define TX_CTRL_LAST
#define TX_CTRL_PAD
#define MAC1_RESET_MCS_RX
#define rxBuffer
error_t lpc178xEthReceivePacket(NetInterface *interface)
Receive a packet.
#define MIND_BUSY
void lpc178xEthEventHandler(NetInterface *interface)
LPC178x Ethernet MAC event handler.
#define TRACE_DEBUG(...)
Definition: debug.h:106
uint16_t regAddr
#define RX_STATUS_SIZE
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
error_t lpc178xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
MAC filter table entry.
Definition: ethernet.h:220
void lpc178xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
error_t lpc178xEthInit(NetInterface *interface)
LPC178x Ethernet MAC initialization.
#define MRDD_READ_DATA
#define osEnterIsr()
#define MAC2_CRC_ENABLE
#define LPC178X_ETH_IRQ_SUB_PRIORITY
void lpc178xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define LPC178X_ETH_RX_BUFFER_COUNT
#define MCFG_CLOCK_SELECT_DIV48
#define IPGT_HALF_DUPLEX
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MCFG_RESET_MII_MGMT
#define MCMD_READ
#define RFC_ACCEPT_MULTICAST_HASH_EN
#define INT_RX_DONE
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
error_t lpc178xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
#define COMMAND_REG_RESET
NIC driver.
Definition: nic.h:179
#define MADR_REGISTER_ADDRESS
#define RFC_ACCEPT_PERFECT_EN
#define MAC1_RESET_RX
void ENET_IRQHandler(void)
LPC178x Ethernet MAC interrupt service routine.
void lpc178xEthTick(NetInterface *interface)
LPC178x Ethernet MAC timer handler.
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
error_t lpc178xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
__start_packed struct @108 MacAddr
MAC address.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79