lpc178x_eth_driver.c
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1 /**
2  * @file lpc178x_eth_driver.c
3  * @brief LPC1786/88 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "lpc177x_8x.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit descriptors
53 #pragma data_alignment = 4
55 //Transmit status array
56 #pragma data_alignment = 4
58 //Receive descriptors
59 #pragma data_alignment = 4
61 //Receive status array
62 #pragma data_alignment = 8
64 
65 //Keil MDK-ARM or GCC compiler?
66 #else
67 
68 //Transmit buffer
70  __attribute__((aligned(4)));
71 //Receive buffer
73  __attribute__((aligned(4)));
74 //Transmit descriptors
76  __attribute__((aligned(4)));
77 //Transmit status array
79  __attribute__((aligned(4)));
80 //Receive descriptors
82  __attribute__((aligned(4)));
83 //Receive status array
85  __attribute__((aligned(8)));
86 
87 #endif
88 
89 
90 /**
91  * @brief LPC178x Ethernet MAC driver
92  **/
93 
95 {
97  ETH_MTU,
108  TRUE,
109  TRUE,
110  TRUE,
111  FALSE
112 };
113 
114 
115 /**
116  * @brief LPC178x Ethernet MAC initialization
117  * @param[in] interface Underlying network interface
118  * @return Error code
119  **/
120 
122 {
123  error_t error;
124 
125  //Debug message
126  TRACE_INFO("Initializing LPC178x Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Power up EMAC controller
132  LPC_SC->PCONP |= PCONP_PCENET;
133 
134  //GPIO configuration
135  lpc178xEthInitGpio(interface);
136 
137  //Reset host registers, transmit datapath and receive datapath
138  LPC_EMAC->Command = COMMAND_RX_RESET | COMMAND_TX_RESET | COMMAND_REG_RESET;
139 
140  //Reset EMAC controller
141  LPC_EMAC->MAC1 = MAC1_SOFT_RESET | MAC1_SIMULATION_RESET |
143 
144  //Initialize MAC related registers
145  LPC_EMAC->MAC1 = 0;
146  LPC_EMAC->MAC2 = MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE;
147  LPC_EMAC->IPGR = IPGR_DEFAULT_VALUE;
148  LPC_EMAC->CLRT = CLRT_DEFAULT_VALUE;
149 
150  //Select RMII mode
151  LPC_EMAC->Command = COMMAND_RMII;
152 
153  //Configure MDC clock
154  LPC_EMAC->MCFG = MCFG_CLOCK_SELECT_DIV48;
155  //Reset MII management interface
156  LPC_EMAC->MCFG |= MCFG_RESET_MII_MGMT;
157  LPC_EMAC->MCFG &= ~MCFG_RESET_MII_MGMT;
158 
159  //Valid Ethernet PHY or switch driver?
160  if(interface->phyDriver != NULL)
161  {
162  //Ethernet PHY initialization
163  error = interface->phyDriver->init(interface);
164  }
165  else if(interface->switchDriver != NULL)
166  {
167  //Ethernet switch initialization
168  error = interface->switchDriver->init(interface);
169  }
170  else
171  {
172  //The interface is not properly configured
173  error = ERROR_FAILURE;
174  }
175 
176  //Any error to report?
177  if(error)
178  {
179  return error;
180  }
181 
182  //Initialize TX and RX descriptor arrays
183  lpc178xEthInitDesc(interface);
184 
185  //Set the MAC address of the station
186  LPC_EMAC->SA0 = interface->macAddr.w[2];
187  LPC_EMAC->SA1 = interface->macAddr.w[1];
188  LPC_EMAC->SA2 = interface->macAddr.w[0];
189 
190  //Initialize hash table
191  LPC_EMAC->HashFilterL = 0;
192  LPC_EMAC->HashFilterH = 0;
193 
194  //Configure the receive filter
195  LPC_EMAC->RxFilterCtrl = RFC_ACCEPT_PERFECT_EN |
197 
198  //Program the MAXF register with the maximum frame length to be accepted
199  LPC_EMAC->MAXF = LPC178X_ETH_RX_BUFFER_SIZE;
200 
201  //Reset EMAC interrupt flags
202  LPC_EMAC->IntClear = 0xFFFF;
203  //Enable desired EMAC interrupts
204  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
205 
206  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
207  NVIC_SetPriorityGrouping(LPC178X_ETH_IRQ_PRIORITY_GROUPING);
208 
209  //Configure Ethernet interrupt priority
210  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(LPC178X_ETH_IRQ_PRIORITY_GROUPING,
212 
213  //Enable transmission and reception
214  LPC_EMAC->Command |= COMMAND_TX_ENABLE | COMMAND_RX_ENABLE;
215  //Allow frames to be received
216  LPC_EMAC->MAC1 |= MAC1_RECEIVE_ENABLE;
217 
218  //Accept any packets from the upper layer
219  osSetEvent(&interface->nicTxEvent);
220 
221  //Successful initialization
222  return NO_ERROR;
223 }
224 
225 
226 //LPC1788-32 Developer's Kit?
227 #if defined(USE_LPC1788_32_DEV_KIT)
228 
229 /**
230  * @brief GPIO configuration
231  * @param[in] interface Underlying network interface
232  **/
233 
234 void lpc178xEthInitGpio(NetInterface *interface)
235 {
236  //Power up GPIO
237  LPC_SC->PCONP |= PCONP_PCGPIO;
238 
239  //Configure P1.0 (ENET_TXD0)
240  LPC_IOCON->P1_0 = IOCON_SLEW | IOCON_FUNC_1;
241  //Configure P1.1 (ENET_TXD1)
242  LPC_IOCON->P1_1 = IOCON_SLEW | IOCON_FUNC_1;
243  //Configure P1.4 (ENET_TX_EN)
244  LPC_IOCON->P1_4 = IOCON_SLEW | IOCON_FUNC_1;
245  //Configure P1.8 (ENET_CRS)
246  LPC_IOCON->P1_8 = IOCON_SLEW | IOCON_FUNC_1;
247  //Configure P1.9 (ENET_RXD0)
248  LPC_IOCON->P1_9 = IOCON_SLEW | IOCON_FUNC_1;
249  //Configure P1.10 (ENET_RXD1)
250  LPC_IOCON->P1_10 = IOCON_SLEW | IOCON_FUNC_1;
251  //Configure P1.14 (RX_ER)
252  LPC_IOCON->P1_14 = IOCON_SLEW | IOCON_FUNC_1;
253  //Configure P1.15 (ENET_REF_CLK)
254  LPC_IOCON->P1_15 = IOCON_SLEW | IOCON_FUNC_1;
255  //Configure P1.16 (ENET_MDC)
256  LPC_IOCON->P1_16 = IOCON_MODE_PULL_UP | IOCON_FUNC_1;
257  //Configure P1.17 (ENET_MDIO)
258  LPC_IOCON->P1_17 = IOCON_MODE_PULL_UP | IOCON_FUNC_1;
259 }
260 
261 #endif
262 
263 
264 /**
265  * @brief Initialize TX and RX descriptors
266  * @param[in] interface Underlying network interface
267  **/
268 
270 {
271  uint_t i;
272 
273  //Initialize TX descriptors
274  for(i = 0; i < LPC178X_ETH_TX_BUFFER_COUNT; i++)
275  {
276  //Base address of the buffer containing transmit data
277  txDesc[i].packet = (uint32_t) txBuffer[i];
278  //Transmit descriptor control word
279  txDesc[i].control = 0;
280  //Transmit status information word
281  txStatus[i].info = 0;
282  }
283 
284  //Initialize RX descriptors
285  for(i = 0; i < LPC178X_ETH_RX_BUFFER_COUNT; i++)
286  {
287  //Base address of the buffer for storing receive data
288  rxDesc[i].packet = (uint32_t) rxBuffer[i];
289  //Receive descriptor control word
291  //Receive status information word
292  rxStatus[i].info = 0;
293  //Receive status HashCRC word
294  rxStatus[i].hashCrc = 0;
295  }
296 
297  //Initialize EMAC transmit descriptor registers
298  LPC_EMAC->TxDescriptor = (uint32_t) txDesc;
299  LPC_EMAC->TxStatus = (uint32_t) txStatus;
300  LPC_EMAC->TxDescriptorNumber = LPC178X_ETH_TX_BUFFER_COUNT - 1;
301  LPC_EMAC->TxProduceIndex = 0;
302 
303  //Initialize EMAC receive descriptor registers
304  LPC_EMAC->RxDescriptor = (uint32_t) rxDesc;
305  LPC_EMAC->RxStatus = (uint32_t) rxStatus;
306  LPC_EMAC->RxDescriptorNumber = LPC178X_ETH_RX_BUFFER_COUNT - 1;
307  LPC_EMAC->RxConsumeIndex = 0;
308 }
309 
310 
311 /**
312  * @brief LPC178x Ethernet MAC timer handler
313  *
314  * This routine is periodically called by the TCP/IP stack to handle periodic
315  * operations such as polling the link state
316  *
317  * @param[in] interface Underlying network interface
318  **/
319 
320 void lpc178xEthTick(NetInterface *interface)
321 {
322  //Valid Ethernet PHY or switch driver?
323  if(interface->phyDriver != NULL)
324  {
325  //Handle periodic operations
326  interface->phyDriver->tick(interface);
327  }
328  else if(interface->switchDriver != NULL)
329  {
330  //Handle periodic operations
331  interface->switchDriver->tick(interface);
332  }
333  else
334  {
335  //Just for sanity
336  }
337 }
338 
339 
340 /**
341  * @brief Enable interrupts
342  * @param[in] interface Underlying network interface
343  **/
344 
346 {
347  //Enable Ethernet MAC interrupts
348  NVIC_EnableIRQ(ENET_IRQn);
349 
350  //Valid Ethernet PHY or switch driver?
351  if(interface->phyDriver != NULL)
352  {
353  //Enable Ethernet PHY interrupts
354  interface->phyDriver->enableIrq(interface);
355  }
356  else if(interface->switchDriver != NULL)
357  {
358  //Enable Ethernet switch interrupts
359  interface->switchDriver->enableIrq(interface);
360  }
361  else
362  {
363  //Just for sanity
364  }
365 }
366 
367 
368 /**
369  * @brief Disable interrupts
370  * @param[in] interface Underlying network interface
371  **/
372 
374 {
375  //Disable Ethernet MAC interrupts
376  NVIC_DisableIRQ(ENET_IRQn);
377 
378  //Valid Ethernet PHY or switch driver?
379  if(interface->phyDriver != NULL)
380  {
381  //Disable Ethernet PHY interrupts
382  interface->phyDriver->disableIrq(interface);
383  }
384  else if(interface->switchDriver != NULL)
385  {
386  //Disable Ethernet switch interrupts
387  interface->switchDriver->disableIrq(interface);
388  }
389  else
390  {
391  //Just for sanity
392  }
393 }
394 
395 
396 /**
397  * @brief LPC178x Ethernet MAC interrupt service routine
398  **/
399 
400 void ENET_IRQHandler(void)
401 {
402  uint_t i;
403  bool_t flag;
404  uint32_t status;
405 
406  //Interrupt service routine prologue
407  osEnterIsr();
408 
409  //This flag will be set if a higher priority task must be woken
410  flag = FALSE;
411 
412  //Read interrupt status register
413  status = LPC_EMAC->IntStatus;
414 
415  //Packet transmitted?
416  if((status & INT_TX_DONE) != 0)
417  {
418  //Clear TxDone interrupt flag
419  LPC_EMAC->IntClear = INT_TX_DONE;
420 
421  //Get the index of the next descriptor
422  i = LPC_EMAC->TxProduceIndex + 1;
423 
424  //Wrap around if necessary
426  {
427  i = 0;
428  }
429 
430  //Check whether the TX buffer is available for writing
431  if(i != LPC_EMAC->TxConsumeIndex)
432  {
433  //Notify the TCP/IP stack that the transmitter is ready to send
434  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
435  }
436  }
437 
438  //Packet received?
439  if((status & INT_RX_DONE) != 0)
440  {
441  //Disable RxDone interrupts
442  LPC_EMAC->IntEnable &= ~INT_RX_DONE;
443 
444  //Set event flag
445  nicDriverInterface->nicEvent = TRUE;
446  //Notify the TCP/IP stack of the event
447  flag |= osSetEventFromIsr(&netEvent);
448  }
449 
450  //Interrupt service routine epilogue
451  osExitIsr(flag);
452 }
453 
454 
455 /**
456  * @brief LPC178x Ethernet MAC event handler
457  * @param[in] interface Underlying network interface
458  **/
459 
461 {
462  error_t error;
463 
464  //Packet received?
465  if((LPC_EMAC->IntStatus & INT_RX_DONE) != 0)
466  {
467  //Clear RxDone interrupt flag
468  LPC_EMAC->IntClear = INT_RX_DONE;
469 
470  //Process all pending packets
471  do
472  {
473  //Read incoming packet
474  error = lpc178xEthReceivePacket(interface);
475 
476  //No more data in the receive buffer?
477  } while(error != ERROR_BUFFER_EMPTY);
478  }
479 
480  //Re-enable TxDone and RxDone interrupts
481  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
482 }
483 
484 
485 /**
486  * @brief Send a packet
487  * @param[in] interface Underlying network interface
488  * @param[in] buffer Multi-part buffer containing the data to send
489  * @param[in] offset Offset to the first data byte
490  * @param[in] ancillary Additional options passed to the stack along with
491  * the packet
492  * @return Error code
493  **/
494 
496  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
497 {
498  uint_t i;
499  uint_t j;
500  size_t length;
501 
502  //Retrieve the length of the packet
503  length = netBufferGetLength(buffer) - offset;
504 
505  //Check the frame length
506  if(!length)
507  {
508  //The transmitter can accept another packet
509  osSetEvent(&interface->nicTxEvent);
510  //We are done since the buffer is empty
511  return NO_ERROR;
512  }
514  {
515  //The transmitter can accept another packet
516  osSetEvent(&interface->nicTxEvent);
517  //Report an error
518  return ERROR_INVALID_LENGTH;
519  }
520 
521  //Get the index of the current descriptor
522  i = LPC_EMAC->TxProduceIndex;
523  //Get the index of the next descriptor
524  j = i + 1;
525 
526  //Wrap around if necessary
528  {
529  j = 0;
530  }
531 
532  //Check whether the transmit descriptor array is full
533  if(j == LPC_EMAC->TxConsumeIndex)
534  {
535  return ERROR_FAILURE;
536  }
537 
538  //Copy user data to the transmit buffer
539  netBufferRead((uint8_t *) txDesc[i].packet, buffer, offset, length);
540 
541  //Write the transmit control word
542  txDesc[i].control = TX_CTRL_INTERRUPT | TX_CTRL_LAST |
544 
545  //Increment index and wrap around if necessary
546  if(++i >= LPC178X_ETH_TX_BUFFER_COUNT)
547  {
548  i = 0;
549  }
550 
551  //Save the resulting value
552  LPC_EMAC->TxProduceIndex = i;
553 
554  //Get the index of the next descriptor
555  j = i + 1;
556 
557  //Wrap around if necessary
559  {
560  j = 0;
561  }
562 
563  //Check whether the next buffer is available for writing
564  if(j != LPC_EMAC->TxConsumeIndex)
565  {
566  //The transmitter can accept another packet
567  osSetEvent(&interface->nicTxEvent);
568  }
569 
570  //Successful write operation
571  return NO_ERROR;
572 }
573 
574 
575 /**
576  * @brief Receive a packet
577  * @param[in] interface Underlying network interface
578  * @return Error code
579  **/
580 
582 {
583  error_t error;
584  size_t n;
585  uint_t i;
586  NetRxAncillary ancillary;
587 
588  //Point to the current descriptor
589  i = LPC_EMAC->RxConsumeIndex;
590 
591  //Make sure the current buffer is available for reading
592  if(i != LPC_EMAC->RxProduceIndex)
593  {
594  //Retrieve the length of the frame
595  n = (rxStatus[i].info & RX_STATUS_SIZE) + 1;
596  //Limit the number of data to read
598 
599  //Additional options can be passed to the stack along with the packet
600  ancillary = NET_DEFAULT_RX_ANCILLARY;
601 
602  //Pass the packet to the upper layer
603  nicProcessPacket(interface, (uint8_t *) rxDesc[i].packet, n, &ancillary);
604 
605  //Increment index and wrap around if necessary
606  if(++i >= LPC178X_ETH_RX_BUFFER_COUNT)
607  {
608  i = 0;
609  }
610 
611  //Save the resulting value
612  LPC_EMAC->RxConsumeIndex = i;
613 
614  //Valid packet received
615  error = NO_ERROR;
616  }
617  else
618  {
619  //No more data in the receive buffer
620  error = ERROR_BUFFER_EMPTY;
621  }
622 
623  //Return status code
624  return error;
625 }
626 
627 
628 /**
629  * @brief Configure MAC address filtering
630  * @param[in] interface Underlying network interface
631  * @return Error code
632  **/
633 
635 {
636  uint_t i;
637  uint_t k;
638  uint32_t crc;
639  uint32_t hashTable[2];
640  MacFilterEntry *entry;
641 
642  //Debug message
643  TRACE_DEBUG("Updating MAC filter...\r\n");
644 
645  //Set the MAC address of the station
646  LPC_EMAC->SA0 = interface->macAddr.w[2];
647  LPC_EMAC->SA1 = interface->macAddr.w[1];
648  LPC_EMAC->SA2 = interface->macAddr.w[0];
649 
650  //Clear hash table
651  hashTable[0] = 0;
652  hashTable[1] = 0;
653 
654  //The MAC address filter contains the list of MAC addresses to accept
655  //when receiving an Ethernet frame
656  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
657  {
658  //Point to the current entry
659  entry = &interface->macAddrFilter[i];
660 
661  //Valid entry?
662  if(entry->refCount > 0)
663  {
664  //Compute CRC over the current MAC address
665  crc = lpc178xEthCalcCrc(&entry->addr, sizeof(MacAddr));
666  //Bits [28:23] are used to form the hash
667  k = (crc >> 23) & 0x3F;
668  //Update hash table contents
669  hashTable[k / 32] |= (1 << (k % 32));
670  }
671  }
672 
673  //Write the hash table
674  LPC_EMAC->HashFilterL = hashTable[0];
675  LPC_EMAC->HashFilterH = hashTable[1];
676 
677  //Debug message
678  TRACE_DEBUG(" HashFilterL = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterL);
679  TRACE_DEBUG(" HashFilterH = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterH);
680 
681  //Successful processing
682  return NO_ERROR;
683 }
684 
685 
686 /**
687  * @brief Adjust MAC configuration parameters for proper operation
688  * @param[in] interface Underlying network interface
689  * @return Error code
690  **/
691 
693 {
694  //10BASE-T or 100BASE-TX operation mode?
695  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
696  {
697  LPC_EMAC->SUPP = SUPP_SPEED;
698  }
699  else
700  {
701  LPC_EMAC->SUPP = 0;
702  }
703 
704  //Half-duplex or full-duplex mode?
705  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
706  {
707  //The MAC operates in full-duplex mode
708  LPC_EMAC->MAC2 |= MAC2_FULL_DUPLEX;
709  LPC_EMAC->Command |= COMMAND_FULL_DUPLEX;
710  //Configure Back-to-Back Inter-Packet Gap
711  LPC_EMAC->IPGT = IPGT_FULL_DUPLEX;
712  }
713  else
714  {
715  //The MAC operates in half-duplex mode
716  LPC_EMAC->MAC2 &= ~MAC2_FULL_DUPLEX;
717  LPC_EMAC->Command &= ~COMMAND_FULL_DUPLEX;
718  //Configure Back-to-Back Inter-Packet Gap
719  LPC_EMAC->IPGT = IPGT_HALF_DUPLEX;
720  }
721 
722  //Successful processing
723  return NO_ERROR;
724 }
725 
726 
727 /**
728  * @brief Write PHY register
729  * @param[in] opcode Access type (2 bits)
730  * @param[in] phyAddr PHY address (5 bits)
731  * @param[in] regAddr Register address (5 bits)
732  * @param[in] data Register value
733  **/
734 
735 void lpc178xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
736  uint8_t regAddr, uint16_t data)
737 {
738  //Valid opcode?
739  if(opcode == SMI_OPCODE_WRITE)
740  {
741  //Clear MCMD register
742  LPC_EMAC->MCMD = 0;
743 
744  //PHY address
745  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
746  //Register address
747  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
748  //Data to be written in the PHY register
749  LPC_EMAC->MWTD = data & MWTD_WRITE_DATA;
750 
751  //Wait for the write to complete
752  while((LPC_EMAC->MIND & MIND_BUSY) != 0)
753  {
754  }
755  }
756  else
757  {
758  //The MAC peripheral only supports standard Clause 22 opcodes
759  }
760 }
761 
762 
763 /**
764  * @brief Read PHY register
765  * @param[in] opcode Access type (2 bits)
766  * @param[in] phyAddr PHY address (5 bits)
767  * @param[in] regAddr Register address (5 bits)
768  * @return Register value
769  **/
770 
771 uint16_t lpc178xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
772  uint8_t regAddr)
773 {
774  uint16_t data;
775 
776  //Valid opcode?
777  if(opcode == SMI_OPCODE_READ)
778  {
779  //PHY address
780  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
781  //Register address
782  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
783 
784  //Start a read operation
785  LPC_EMAC->MCMD = MCMD_READ;
786  //Wait for the read to complete
787  while((LPC_EMAC->MIND & MIND_BUSY) != 0)
788  {
789  }
790 
791  //Clear MCMD register
792  LPC_EMAC->MCMD = 0;
793 
794  //Get register value
795  data = LPC_EMAC->MRDD & MRDD_READ_DATA;
796  }
797  else
798  {
799  //The MAC peripheral only supports standard Clause 22 opcodes
800  data = 0;
801  }
802 
803  //Return the value of the PHY register
804  return data;
805 }
806 
807 
808 /**
809  * @brief CRC calculation
810  * @param[in] data Pointer to the data over which to calculate the CRC
811  * @param[in] length Number of bytes to process
812  * @return Resulting CRC value
813  **/
814 
815 uint32_t lpc178xEthCalcCrc(const void *data, size_t length)
816 {
817  uint_t i;
818  uint_t j;
819  uint32_t crc;
820  const uint8_t *p;
821 
822  //Point to the data over which to calculate the CRC
823  p = (uint8_t *) data;
824  //CRC preset value
825  crc = 0xFFFFFFFF;
826 
827  //Loop through data
828  for(i = 0; i < length; i++)
829  {
830  //The message is processed bit by bit
831  for(j = 0; j < 8; j++)
832  {
833  //Update CRC value
834  if((((crc >> 31) ^ (p[i] >> j)) & 0x01) != 0)
835  {
836  crc = (crc << 1) ^ 0x04C11DB7;
837  }
838  else
839  {
840  crc = crc << 1;
841  }
842  }
843  }
844 
845  //Return CRC value
846  return crc;
847 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
#define MADR_PHY_ADDRESS
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define netEvent
Definition: net_legacy.h:267
#define TX_CTRL_SIZE
Transmit descriptor.
uint8_t data[]
Definition: ethernet.h:209
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define LPC178X_ETH_TX_BUFFER_SIZE
LPC1786/88 Ethernet MAC driver.
uint8_t p
Definition: ndp.h:298
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define IPGR_DEFAULT_VALUE
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
void lpc178xEthInitGpio(NetInterface *interface)
#define COMMAND_TX_ENABLE
__start_packed struct @5 MacAddr
MAC address.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:249
#define LPC178X_ETH_IRQ_PRIORITY_GROUPING
const NicDriver lpc178xEthDriver
LPC178x Ethernet MAC driver.
#define LPC178X_ETH_TX_BUFFER_COUNT
#define IPGT_FULL_DUPLEX
void lpc178xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define MAC1_SOFT_RESET
#define TX_CTRL_CRC
#define COMMAND_RMII
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define osExitIsr(flag)
#define TX_CTRL_INTERRUPT
uint16_t lpc178xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define SMI_OPCODE_WRITE
Definition: nic.h:65
#define RX_CTRL_INTERRUPT
Receive status.
Transmit status.
#define MAC1_RESET_TX
#define MAC1_RECEIVE_ENABLE
#define SUPP_SPEED
#define MWTD_WRITE_DATA
#define MAC2_FULL_DUPLEX
#define CLRT_DEFAULT_VALUE
#define FALSE
Definition: os_port.h:46
#define LPC178X_ETH_IRQ_GROUP_PRIORITY
#define MAC1_SIMULATION_RESET
void lpc178xEthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t
Error codes.
Definition: error.h:42
#define COMMAND_RX_RESET
#define COMMAND_RX_ENABLE
#define LPC178X_ETH_RX_BUFFER_SIZE
uint32_t lpc178xEthCalcCrc(const void *data, size_t length)
CRC calculation.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
#define RFC_ACCEPT_BROADCAST_EN
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
#define INT_TX_DONE
MacAddr addr
MAC address.
Definition: ethernet.h:248
Receive descriptor.
#define NetTxAncillary
Definition: net_misc.h:36
#define SMI_OPCODE_READ
Definition: nic.h:66
#define COMMAND_TX_RESET
#define MAC1_RESET_MCS_TX
#define TRACE_INFO(...)
Definition: debug.h:95
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MAC2_PAD_CRC_ENABLE
#define COMMAND_FULL_DUPLEX
#define MIN(a, b)
Definition: os_port.h:62
#define TX_CTRL_LAST
#define TX_CTRL_PAD
#define MAC1_RESET_MCS_RX
#define rxBuffer
error_t lpc178xEthReceivePacket(NetInterface *interface)
Receive a packet.
#define MIND_BUSY
void lpc178xEthEventHandler(NetInterface *interface)
LPC178x Ethernet MAC event handler.
#define TRACE_DEBUG(...)
Definition: debug.h:107
uint16_t regAddr
#define RX_STATUS_SIZE
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
error_t lpc178xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
MAC filter table entry.
Definition: ethernet.h:246
void lpc178xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
error_t lpc178xEthInit(NetInterface *interface)
LPC178x Ethernet MAC initialization.
#define MRDD_READ_DATA
#define osEnterIsr()
#define MAC2_CRC_ENABLE
#define LPC178X_ETH_IRQ_SUB_PRIORITY
void lpc178xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define LPC178X_ETH_RX_BUFFER_COUNT
#define MCFG_CLOCK_SELECT_DIV48
#define IPGT_HALF_DUPLEX
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MCFG_RESET_MII_MGMT
#define MCMD_READ
#define RFC_ACCEPT_MULTICAST_HASH_EN
#define INT_RX_DONE
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
#define COMMAND_REG_RESET
NIC driver.
Definition: nic.h:257
#define MADR_REGISTER_ADDRESS
#define RFC_ACCEPT_PERFECT_EN
#define MAC1_RESET_RX
void ENET_IRQHandler(void)
LPC178x Ethernet MAC interrupt service routine.
void lpc178xEthTick(NetInterface *interface)
LPC178x Ethernet MAC timer handler.
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
error_t lpc178xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t lpc178xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Ethernet interface.
Definition: nic.h:82