lpc178x_eth_driver.c
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1 /**
2  * @file lpc178x_eth_driver.c
3  * @brief LPC1786/88 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "lpc177x_8x.h"
34 #include "core/net.h"
36 #include "debug.h"
37 
38 //Underlying network interface
39 static NetInterface *nicDriverInterface;
40 
41 //IAR EWARM compiler?
42 #if defined(__ICCARM__)
43 
44 //Transmit buffer
45 #pragma data_alignment = 4
47 //Receive buffer
48 #pragma data_alignment = 4
50 //Transmit descriptors
51 #pragma data_alignment = 4
53 //Transmit status array
54 #pragma data_alignment = 4
56 //Receive descriptors
57 #pragma data_alignment = 4
59 //Receive status array
60 #pragma data_alignment = 8
62 
63 //Keil MDK-ARM or GCC compiler?
64 #else
65 
66 //Transmit buffer
68  __attribute__((aligned(4)));
69 //Receive buffer
71  __attribute__((aligned(4)));
72 //Transmit descriptors
74  __attribute__((aligned(4)));
75 //Transmit status array
77  __attribute__((aligned(4)));
78 //Receive descriptors
80  __attribute__((aligned(4)));
81 //Receive status array
83  __attribute__((aligned(8)));
84 
85 #endif
86 
87 
88 /**
89  * @brief LPC178x Ethernet MAC driver
90  **/
91 
93 {
95  ETH_MTU,
106  TRUE,
107  TRUE,
108  TRUE,
109  FALSE
110 };
111 
112 
113 /**
114  * @brief LPC178x Ethernet MAC initialization
115  * @param[in] interface Underlying network interface
116  * @return Error code
117  **/
118 
120 {
121  error_t error;
122 
123  //Debug message
124  TRACE_INFO("Initializing LPC178x Ethernet MAC...\r\n");
125 
126  //Save underlying network interface
127  nicDriverInterface = interface;
128 
129  //Power up EMAC controller
130  LPC_SC->PCONP |= PCONP_PCENET;
131 
132  //GPIO configuration
133  lpc178xEthInitGpio(interface);
134 
135  //Reset host registers, transmit datapath and receive datapath
136  LPC_EMAC->Command = COMMAND_RX_RESET | COMMAND_TX_RESET | COMMAND_REG_RESET;
137 
138  //Reset EMAC controller
139  LPC_EMAC->MAC1 = MAC1_SOFT_RESET | MAC1_SIMULATION_RESET |
141 
142  //Initialize MAC related registers
143  LPC_EMAC->MAC1 = 0;
144  LPC_EMAC->MAC2 = MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE;
145  LPC_EMAC->IPGR = IPGR_DEFAULT_VALUE;
146  LPC_EMAC->CLRT = CLRT_DEFAULT_VALUE;
147 
148  //Select RMII mode
149  LPC_EMAC->Command = COMMAND_RMII;
150 
151  //Configure MDC clock
152  LPC_EMAC->MCFG = MCFG_CLOCK_SELECT_DIV48;
153  //Reset MII management interface
154  LPC_EMAC->MCFG |= MCFG_RESET_MII_MGMT;
155  LPC_EMAC->MCFG &= ~MCFG_RESET_MII_MGMT;
156 
157  //PHY transceiver initialization
158  error = interface->phyDriver->init(interface);
159  //Failed to initialize PHY transceiver?
160  if(error)
161  return error;
162 
163  //Initialize TX and RX descriptor arrays
164  lpc178xEthInitDesc(interface);
165 
166  //Set the MAC address
167  LPC_EMAC->SA0 = interface->macAddr.w[2];
168  LPC_EMAC->SA1 = interface->macAddr.w[1];
169  LPC_EMAC->SA2 = interface->macAddr.w[0];
170 
171  //Initialize hash table
172  LPC_EMAC->HashFilterL = 0;
173  LPC_EMAC->HashFilterH = 0;
174 
175  //Configure the receive filter
176  LPC_EMAC->RxFilterCtrl = RFC_ACCEPT_PERFECT_EN |
178 
179  //Program the MAXF register with the maximum frame length to be accepted
180  LPC_EMAC->MAXF = 1518;
181 
182  //Reset EMAC interrupt flags
183  LPC_EMAC->IntClear = 0xFFFF;
184  //Enable desired EMAC interrupts
185  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
186 
187  //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
188  NVIC_SetPriorityGrouping(LPC178X_ETH_IRQ_PRIORITY_GROUPING);
189 
190  //Configure Ethernet interrupt priority
191  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(LPC178X_ETH_IRQ_PRIORITY_GROUPING,
193 
194  //Enable transmission and reception
195  LPC_EMAC->Command |= COMMAND_TX_ENABLE | COMMAND_RX_ENABLE;
196  //Allow frames to be received
197  LPC_EMAC->MAC1 |= MAC1_RECEIVE_ENABLE;
198 
199  //Accept any packets from the upper layer
200  osSetEvent(&interface->nicTxEvent);
201 
202  //Successful initialization
203  return NO_ERROR;
204 }
205 
206 
207 //LPC1788-32 Developer's Kit?
208 #if defined(USE_LPC1788_32_DEV_KIT)
209 
210 /**
211  * @brief GPIO configuration
212  * @param[in] interface Underlying network interface
213  **/
214 
215 void lpc178xEthInitGpio(NetInterface *interface)
216 {
217  //Power up GPIO
218  LPC_SC->PCONP |= PCONP_PCGPIO;
219 
220  //Configure P1.0 (ENET_TXD0)
221  LPC_IOCON->P1_0 = IOCON_SLEW | IOCON_FUNC_1;
222  //Configure P1.1 (ENET_TXD1)
223  LPC_IOCON->P1_1 = IOCON_SLEW | IOCON_FUNC_1;
224  //Configure P1.4 (ENET_TX_EN)
225  LPC_IOCON->P1_4 = IOCON_SLEW | IOCON_FUNC_1;
226  //Configure P1.8 (ENET_CRS)
227  LPC_IOCON->P1_8 = IOCON_SLEW | IOCON_FUNC_1;
228  //Configure P1.9 (ENET_RXD0)
229  LPC_IOCON->P1_9 = IOCON_SLEW | IOCON_FUNC_1;
230  //Configure P1.10 (ENET_RXD1)
231  LPC_IOCON->P1_10 = IOCON_SLEW | IOCON_FUNC_1;
232  //Configure P1.14 (RX_ER)
233  LPC_IOCON->P1_14 = IOCON_SLEW | IOCON_FUNC_1;
234  //Configure P1.15 (ENET_REF_CLK)
235  LPC_IOCON->P1_15 = IOCON_SLEW | IOCON_FUNC_1;
236  //Configure P1.16 (ENET_MDC)
237  LPC_IOCON->P1_16 = IOCON_MODE_PULL_UP | IOCON_FUNC_1;
238  //Configure P1.17 (ENET_MDIO)
239  LPC_IOCON->P1_17 = IOCON_MODE_PULL_UP | IOCON_FUNC_1;
240 }
241 
242 #endif
243 
244 
245 /**
246  * @brief Initialize TX and RX descriptors
247  * @param[in] interface Underlying network interface
248  **/
249 
251 {
252  uint_t i;
253 
254  //Initialize TX descriptors
255  for(i = 0; i < LPC178X_ETH_TX_BUFFER_COUNT; i++)
256  {
257  //Base address of the buffer containing transmit data
258  txDesc[i].packet = (uint32_t) txBuffer[i];
259  //Transmit descriptor control word
260  txDesc[i].control = 0;
261  //Transmit status information word
262  txStatus[i].info = 0;
263  }
264 
265  //Initialize RX descriptors
266  for(i = 0; i < LPC178X_ETH_RX_BUFFER_COUNT; i++)
267  {
268  //Base address of the buffer for storing receive data
269  rxDesc[i].packet = (uint32_t) rxBuffer[i];
270  //Receive descriptor control word
272  //Receive status information word
273  rxStatus[i].info = 0;
274  //Receive status HashCRC word
275  rxStatus[i].hashCrc = 0;
276  }
277 
278  //Initialize EMAC transmit descriptor registers
279  LPC_EMAC->TxDescriptor = (uint32_t) txDesc;
280  LPC_EMAC->TxStatus = (uint32_t) txStatus;
281  LPC_EMAC->TxDescriptorNumber = LPC178X_ETH_TX_BUFFER_COUNT - 1;
282  LPC_EMAC->TxProduceIndex = 0;
283 
284  //Initialize EMAC receive descriptor registers
285  LPC_EMAC->RxDescriptor = (uint32_t) rxDesc;
286  LPC_EMAC->RxStatus = (uint32_t) rxStatus;
287  LPC_EMAC->RxDescriptorNumber = LPC178X_ETH_RX_BUFFER_COUNT - 1;
288  LPC_EMAC->RxConsumeIndex = 0;
289 }
290 
291 
292 /**
293  * @brief LPC178x Ethernet MAC timer handler
294  *
295  * This routine is periodically called by the TCP/IP stack to
296  * handle periodic operations such as polling the link state
297  *
298  * @param[in] interface Underlying network interface
299  **/
300 
301 void lpc178xEthTick(NetInterface *interface)
302 {
303  //Handle periodic operations
304  interface->phyDriver->tick(interface);
305 }
306 
307 
308 /**
309  * @brief Enable interrupts
310  * @param[in] interface Underlying network interface
311  **/
312 
314 {
315  //Enable Ethernet MAC interrupts
316  NVIC_EnableIRQ(ENET_IRQn);
317  //Enable Ethernet PHY interrupts
318  interface->phyDriver->enableIrq(interface);
319 }
320 
321 
322 /**
323  * @brief Disable interrupts
324  * @param[in] interface Underlying network interface
325  **/
326 
328 {
329  //Disable Ethernet MAC interrupts
330  NVIC_DisableIRQ(ENET_IRQn);
331  //Disable Ethernet PHY interrupts
332  interface->phyDriver->disableIrq(interface);
333 }
334 
335 
336 /**
337  * @brief LPC178x Ethernet MAC interrupt service routine
338  **/
339 
340 void ENET_IRQHandler(void)
341 {
342  uint_t i;
343  bool_t flag;
344  uint32_t status;
345 
346  //Enter interrupt service routine
347  osEnterIsr();
348 
349  //This flag will be set if a higher priority task must be woken
350  flag = FALSE;
351 
352  //Read interrupt status register
353  status = LPC_EMAC->IntStatus;
354 
355  //A packet has been transmitted?
356  if(status & INT_TX_DONE)
357  {
358  //Clear TxDone interrupt flag
359  LPC_EMAC->IntClear = INT_TX_DONE;
360 
361  //Get the index of the next descriptor
362  i = LPC_EMAC->TxProduceIndex + 1;
363 
364  //Wrap around if necessary
366  i = 0;
367 
368  //Check whether the TX buffer is available for writing
369  if(i != LPC_EMAC->TxConsumeIndex)
370  {
371  //Notify the TCP/IP stack that the transmitter is ready to send
372  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
373  }
374  }
375 
376  //A packet has been received?
377  if(status & INT_RX_DONE)
378  {
379  //Disable RxDone interrupts
380  LPC_EMAC->IntEnable &= ~INT_RX_DONE;
381 
382  //Set event flag
383  nicDriverInterface->nicEvent = TRUE;
384  //Notify the TCP/IP stack of the event
385  flag |= osSetEventFromIsr(&netEvent);
386  }
387 
388  //Leave interrupt service routine
389  osExitIsr(flag);
390 }
391 
392 
393 /**
394  * @brief LPC178x Ethernet MAC event handler
395  * @param[in] interface Underlying network interface
396  **/
397 
399 {
400  error_t error;
401 
402  //Packet received?
403  if(LPC_EMAC->IntStatus & INT_RX_DONE)
404  {
405  //Clear RxDone interrupt flag
406  LPC_EMAC->IntClear = INT_RX_DONE;
407 
408  //Process all pending packets
409  do
410  {
411  //Read incoming packet
412  error = lpc178xEthReceivePacket(interface);
413 
414  //No more data in the receive buffer?
415  } while(error != ERROR_BUFFER_EMPTY);
416  }
417 
418  //Re-enable TxDone and RxDone interrupts
419  LPC_EMAC->IntEnable = INT_TX_DONE | INT_RX_DONE;
420 }
421 
422 
423 /**
424  * @brief Send a packet
425  * @param[in] interface Underlying network interface
426  * @param[in] buffer Multi-part buffer containing the data to send
427  * @param[in] offset Offset to the first data byte
428  * @return Error code
429  **/
430 
432  const NetBuffer *buffer, size_t offset)
433 {
434  uint_t i;
435  uint_t j;
436  size_t length;
437 
438  //Retrieve the length of the packet
439  length = netBufferGetLength(buffer) - offset;
440 
441  //Check the frame length
442  if(!length)
443  {
444  //The transmitter can accept another packet
445  osSetEvent(&interface->nicTxEvent);
446  //We are done since the buffer is empty
447  return NO_ERROR;
448  }
450  {
451  //The transmitter can accept another packet
452  osSetEvent(&interface->nicTxEvent);
453  //Report an error
454  return ERROR_INVALID_LENGTH;
455  }
456 
457  //Get the index of the current descriptor
458  i = LPC_EMAC->TxProduceIndex;
459  //Get the index of the next descriptor
460  j = i + 1;
461 
462  //Wrap around if necessary
464  j = 0;
465 
466  //Check whether the transmit descriptor array is full
467  if(j == LPC_EMAC->TxConsumeIndex)
468  return ERROR_FAILURE;
469 
470  //Copy user data to the transmit buffer
471  netBufferRead((uint8_t *) txDesc[i].packet, buffer, offset, length);
472 
473  //Write the transmit control word
474  txDesc[i].control = TX_CTRL_INTERRUPT | TX_CTRL_LAST |
476 
477  //Increment index and wrap around if necessary
478  if(++i >= LPC178X_ETH_TX_BUFFER_COUNT)
479  i = 0;
480 
481  //Save the resulting value
482  LPC_EMAC->TxProduceIndex = i;
483 
484  //Get the index of the next descriptor
485  j = i + 1;
486 
487  //Wrap around if necessary
489  j = 0;
490 
491  //Check whether the next buffer is available for writing
492  if(j != LPC_EMAC->TxConsumeIndex)
493  {
494  //The transmitter can accept another packet
495  osSetEvent(&interface->nicTxEvent);
496  }
497 
498  //Successful write operation
499  return NO_ERROR;
500 }
501 
502 
503 /**
504  * @brief Receive a packet
505  * @param[in] interface Underlying network interface
506  * @return Error code
507  **/
508 
510 {
511  error_t error;
512  size_t n;
513  uint_t i;
514 
515  //Point to the current descriptor
516  i = LPC_EMAC->RxConsumeIndex;
517 
518  //Make sure the current buffer is available for reading
519  if(i != LPC_EMAC->RxProduceIndex)
520  {
521  //Retrieve the length of the frame
522  n = (rxStatus[i].info & RX_STATUS_SIZE) + 1;
523  //Limit the number of data to read
525 
526  //Pass the packet to the upper layer
527  nicProcessPacket(interface, (uint8_t *) rxDesc[i].packet, n);
528 
529  //Increment index and wrap around if necessary
530  if(++i >= LPC178X_ETH_RX_BUFFER_COUNT)
531  i = 0;
532 
533  //Save the resulting value
534  LPC_EMAC->RxConsumeIndex = i;
535 
536  //Valid packet received
537  error = NO_ERROR;
538  }
539  else
540  {
541  //No more data in the receive buffer
542  error = ERROR_BUFFER_EMPTY;
543  }
544 
545  //Return status code
546  return error;
547 }
548 
549 
550 /**
551  * @brief Configure MAC address filtering
552  * @param[in] interface Underlying network interface
553  * @return Error code
554  **/
555 
557 {
558  uint_t i;
559  uint_t k;
560  uint32_t crc;
561  uint32_t hashTable[2];
562  MacFilterEntry *entry;
563 
564  //Debug message
565  TRACE_DEBUG("Updating LPC178x hash table...\r\n");
566 
567  //Clear hash table
568  hashTable[0] = 0;
569  hashTable[1] = 0;
570 
571  //The MAC address filter contains the list of MAC addresses to accept
572  //when receiving an Ethernet frame
573  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
574  {
575  //Point to the current entry
576  entry = &interface->macAddrFilter[i];
577 
578  //Valid entry?
579  if(entry->refCount > 0)
580  {
581  //Compute CRC over the current MAC address
582  crc = lpc178xEthCalcCrc(&entry->addr, sizeof(MacAddr));
583  //Bits [28:23] are used to form the hash
584  k = (crc >> 23) & 0x3F;
585  //Update hash table contents
586  hashTable[k / 32] |= (1 << (k % 32));
587  }
588  }
589 
590  //Write the hash table
591  LPC_EMAC->HashFilterL = hashTable[0];
592  LPC_EMAC->HashFilterH = hashTable[1];
593 
594  //Debug message
595  TRACE_DEBUG(" HashFilterL = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterL);
596  TRACE_DEBUG(" HashFilterH = %08" PRIX32 "\r\n", LPC_EMAC->HashFilterH);
597 
598  //Successful processing
599  return NO_ERROR;
600 }
601 
602 
603 /**
604  * @brief Adjust MAC configuration parameters for proper operation
605  * @param[in] interface Underlying network interface
606  * @return Error code
607  **/
608 
610 {
611  //10BASE-T or 100BASE-TX operation mode?
612  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
613  LPC_EMAC->SUPP = SUPP_SPEED;
614  else
615  LPC_EMAC->SUPP = 0;
616 
617  //Half-duplex or full-duplex mode?
618  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
619  {
620  //The MAC operates in full-duplex mode
621  LPC_EMAC->MAC2 |= MAC2_FULL_DUPLEX;
622  LPC_EMAC->Command |= COMMAND_FULL_DUPLEX;
623  //Configure Back-to-Back Inter-Packet Gap
624  LPC_EMAC->IPGT = IPGT_FULL_DUPLEX;
625  }
626  else
627  {
628  //The MAC operates in half-duplex mode
629  LPC_EMAC->MAC2 &= ~MAC2_FULL_DUPLEX;
630  LPC_EMAC->Command &= ~COMMAND_FULL_DUPLEX;
631  //Configure Back-to-Back Inter-Packet Gap
632  LPC_EMAC->IPGT = IPGT_HALF_DUPLEX;
633  }
634 
635  //Successful processing
636  return NO_ERROR;
637 }
638 
639 
640 /**
641  * @brief Write PHY register
642  * @param[in] phyAddr PHY address
643  * @param[in] regAddr Register address
644  * @param[in] data Register value
645  **/
646 
647 void lpc178xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
648 {
649  //Clear MCMD register
650  LPC_EMAC->MCMD = 0;
651 
652  //PHY address
653  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
654  //Register address
655  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
656  //Data to be written in the PHY register
657  LPC_EMAC->MWTD = data & MWTD_WRITE_DATA;
658 
659  //Wait for the write to complete
660  while(LPC_EMAC->MIND & MIND_BUSY);
661 }
662 
663 
664 /**
665  * @brief Read PHY register
666  * @param[in] phyAddr PHY address
667  * @param[in] regAddr Register address
668  * @return Register value
669  **/
670 
671 uint16_t lpc178xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
672 {
673  //PHY address
674  LPC_EMAC->MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
675  //Register address
676  LPC_EMAC->MADR |= regAddr & MADR_REGISTER_ADDRESS;
677 
678  //Start a read operation
679  LPC_EMAC->MCMD = MCMD_READ;
680  //Wait for the read to complete
681  while(LPC_EMAC->MIND & MIND_BUSY);
682  //Clear MCMD register
683  LPC_EMAC->MCMD = 0;
684 
685  //Return PHY register contents
686  return LPC_EMAC->MRDD & MRDD_READ_DATA;
687 }
688 
689 
690 /**
691  * @brief CRC calculation
692  * @param[in] data Pointer to the data over which to calculate the CRC
693  * @param[in] length Number of bytes to process
694  * @return Resulting CRC value
695  **/
696 
697 uint32_t lpc178xEthCalcCrc(const void *data, size_t length)
698 {
699  uint_t i;
700  uint_t j;
701 
702  //Point to the data over which to calculate the CRC
703  const uint8_t *p = (uint8_t *) data;
704  //CRC preset value
705  uint32_t crc = 0xFFFFFFFF;
706 
707  //Loop through data
708  for(i = 0; i < length; i++)
709  {
710  //The message is processed bit by bit
711  for(j = 0; j < 8; j++)
712  {
713  //Update CRC value
714  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
715  crc = (crc << 1) ^ 0x04C11DB7;
716  else
717  crc = crc << 1;
718  }
719  }
720 
721  //Return CRC value
722  return crc;
723 }
#define LPC178X_ETH_TX_BUFFER_SIZE
#define LPC178X_ETH_IRQ_PRIORITY_GROUPING
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define LPC178X_ETH_IRQ_GROUP_PRIORITY
uint32_t lpc178xEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define MWTD_WRITE_DATA
#define IPGT_HALF_DUPLEX
#define MAC1_RESET_MCS_TX
const NicDriver lpc178xEthDriver
LPC178x Ethernet MAC driver.
#define RFC_ACCEPT_PERFECT_EN
#define COMMAND_TX_ENABLE
TCP/IP stack core.
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
Generic error code.
Definition: error.h:43
#define RX_STATUS_SIZE
#define txBuffer
error_t lpc178xEthInit(NetInterface *interface)
LPC178x Ethernet MAC initialization.
#define MAC1_SIMULATION_RESET
error_t lpc178xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define MAC2_CRC_ENABLE
#define CLRT_DEFAULT_VALUE
#define LPC178X_ETH_TX_BUFFER_COUNT
#define MAC2_PAD_CRC_ENABLE
void lpc178xEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
#define MAC1_RECEIVE_ENABLE
#define LPC178X_ETH_RX_BUFFER_COUNT
#define IPGR_DEFAULT_VALUE
#define MCMD_READ
#define INT_RX_DONE
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define TX_CTRL_CRC
uint16_t lpc178xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define MRDD_READ_DATA
#define MADR_REGISTER_ADDRESS
void ENET_IRQHandler(void)
LPC178x Ethernet MAC interrupt service routine.
#define COMMAND_REG_RESET
#define MIND_BUSY
#define MADR_PHY_ADDRESS
Transmit descriptor.
#define MAC2_FULL_DUPLEX
void lpc178xEthTick(NetInterface *interface)
LPC178x Ethernet MAC timer handler.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define TX_CTRL_LAST
#define TX_CTRL_PAD
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define COMMAND_RMII
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define RFC_ACCEPT_BROADCAST_EN
#define COMMAND_FULL_DUPLEX
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
error_t lpc178xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Success.
Definition: error.h:42
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define MAC1_RESET_MCS_RX
#define MAC1_RESET_RX
#define COMMAND_RX_RESET
#define LPC178X_ETH_IRQ_SUB_PRIORITY
Receive status.
Transmit status.
#define RFC_ACCEPT_MULTICAST_HASH_EN
unsigned int uint_t
Definition: compiler_port.h:43
#define INT_TX_DONE
__start_packed struct @112 MacAddr
MAC address.
#define IPGT_FULL_DUPLEX
uint8_t data[]
Definition: dtls_misc.h:167
#define MCFG_RESET_MII_MGMT
#define NetInterface
Definition: net.h:34
void lpc178xEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define TX_CTRL_SIZE
#define MAC1_SOFT_RESET
#define RX_CTRL_INTERRUPT
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void lpc178xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t lpc178xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define TX_CTRL_INTERRUPT
LPC1786/88 Ethernet MAC controller.
#define MAC1_RESET_TX
error_t lpc178xEthReceivePacket(NetInterface *interface)
Receive a packet.
#define SUPP_SPEED
void lpc178xEthInitGpio(NetInterface *interface)
#define osExitIsr(flag)
#define COMMAND_TX_RESET
#define MCFG_CLOCK_SELECT_DIV48
#define LPC178X_ETH_RX_BUFFER_SIZE
#define osEnterIsr()
void lpc178xEthEnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define COMMAND_RX_ENABLE
Receive descriptor.
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
void lpc178xEthEventHandler(NetInterface *interface)
LPC178x Ethernet MAC event handler.
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98