lpc18xx_eth_driver.h
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1 /**
2  * @file lpc18xx_eth_driver.h
3  * @brief LPC1800 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _LPC18XX_ETH_DRIVER_H
32 #define _LPC18XX_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef LPC18XX_ETH_TX_BUFFER_COUNT
39  #define LPC18XX_ETH_TX_BUFFER_COUNT 3
40 #elif (LPC18XX_ETH_TX_BUFFER_COUNT < 1)
41  #error LPC18XX_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef LPC18XX_ETH_TX_BUFFER_SIZE
46  #define LPC18XX_ETH_TX_BUFFER_SIZE 1536
47 #elif (LPC18XX_ETH_TX_BUFFER_SIZE != 1536)
48  #error LPC18XX_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef LPC18XX_ETH_RX_BUFFER_COUNT
53  #define LPC18XX_ETH_RX_BUFFER_COUNT 6
54 #elif (LPC18XX_ETH_RX_BUFFER_COUNT < 1)
55  #error LPC18XX_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef LPC18XX_ETH_RX_BUFFER_SIZE
60  #define LPC18XX_ETH_RX_BUFFER_SIZE 1536
61 #elif (LPC18XX_ETH_RX_BUFFER_SIZE != 1536)
62  #error LPC18XX_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef LPC18XX_ETH_IRQ_PRIORITY_GROUPING
67  #define LPC18XX_ETH_IRQ_PRIORITY_GROUPING 4
68 #elif (LPC18XX_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error LPC18XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef LPC18XX_ETH_IRQ_GROUP_PRIORITY
74  #define LPC18XX_ETH_IRQ_GROUP_PRIORITY 6
75 #elif (LPC18XX_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error LPC18XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef LPC18XX_ETH_IRQ_SUB_PRIORITY
81  #define LPC18XX_ETH_IRQ_SUB_PRIORITY 0
82 #elif (LPC18XX_ETH_IRQ_SUB_PRIORITY < 0)
83  #error LPC18XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //CREG6 register
87 #define CREG6_ETHMODE_MII (0 << CREG_CREG6_ETHMODE_Pos)
88 #define CREG6_ETHMODE_RMII (4 << CREG_CREG6_ETHMODE_Pos)
89 
90 //MAC_MII_ADDR register
91 #define ETHERNET_MAC_MII_ADDR_CR_DIV42 (0 << ETHERNET_MAC_MII_ADDR_CR_Pos)
92 #define ETHERNET_MAC_MII_ADDR_CR_DIV62 (1 << ETHERNET_MAC_MII_ADDR_CR_Pos)
93 #define ETHERNET_MAC_MII_ADDR_CR_DIV16 (2 << ETHERNET_MAC_MII_ADDR_CR_Pos)
94 #define ETHERNET_MAC_MII_ADDR_CR_DIV26 (3 << ETHERNET_MAC_MII_ADDR_CR_Pos)
95 #define ETHERNET_MAC_MII_ADDR_CR_DIV102 (4 << ETHERNET_MAC_MII_ADDR_CR_Pos)
96 #define ETHERNET_MAC_MII_ADDR_CR_DIV124 (5 << ETHERNET_MAC_MII_ADDR_CR_Pos)
97 
98 //DMA_BUS_MODE register
99 #define ETHERNET_DMA_BUS_MODE_RPBL_1 (1 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
100 #define ETHERNET_DMA_BUS_MODE_RPBL_2 (2 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
101 #define ETHERNET_DMA_BUS_MODE_RPBL_4 (4 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
102 #define ETHERNET_DMA_BUS_MODE_RPBL_8 (8 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
103 #define ETHERNET_DMA_BUS_MODE_RPBL_16 (16 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
104 #define ETHERNET_DMA_BUS_MODE_RPBL_32 (32 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
105 
106 #define ETHERNET_DMA_BUS_MODE_PR_1_1 (0 << ETHERNET_DMA_BUS_MODE_PR_Pos)
107 #define ETHERNET_DMA_BUS_MODE_PR_2_1 (1 << ETHERNET_DMA_BUS_MODE_PR_Pos)
108 #define ETHERNET_DMA_BUS_MODE_PR_3_1 (2 << ETHERNET_DMA_BUS_MODE_PR_Pos)
109 #define ETHERNET_DMA_BUS_MODE_PR_4_1 (3 << ETHERNET_DMA_BUS_MODE_PR_Pos)
110 
111 #define ETHERNET_DMA_BUS_MODE_PBL_1 (1 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
112 #define ETHERNET_DMA_BUS_MODE_PBL_2 (2 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
113 #define ETHERNET_DMA_BUS_MODE_PBL_4 (4 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
114 #define ETHERNET_DMA_BUS_MODE_PBL_8 (8 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
115 #define ETHERNET_DMA_BUS_MODE_PBL_16 (16 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
116 #define ETHERNET_DMA_BUS_MODE_PBL_32 (32 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
117 
118 //DMA_OP_MODE register
119 #define ETHERNET_DMA_OP_MODE_TTC_64 (0 << ETHERNET_DMA_OP_MODE_TTC_Pos)
120 #define ETHERNET_DMA_OP_MODE_TTC_128 (1 << ETHERNET_DMA_OP_MODE_TTC_Pos)
121 #define ETHERNET_DMA_OP_MODE_TTC_192 (2 << ETHERNET_DMA_OP_MODE_TTC_Pos)
122 #define ETHERNET_DMA_OP_MODE_TTC_256 (3 << ETHERNET_DMA_OP_MODE_TTC_Pos)
123 #define ETHERNET_DMA_OP_MODE_TTC_40 (4 << ETHERNET_DMA_OP_MODE_TTC_Pos)
124 #define ETHERNET_DMA_OP_MODE_TTC_32 (5 << ETHERNET_DMA_OP_MODE_TTC_Pos)
125 #define ETHERNET_DMA_OP_MODE_TTC_24 (6 << ETHERNET_DMA_OP_MODE_TTC_Pos)
126 #define ETHERNET_DMA_OP_MODE_TTC_16 (7 << ETHERNET_DMA_OP_MODE_TTC_Pos)
127 
128 #define ETHERNET_DMA_OP_MODE_RTC_64 (0 << ETHERNET_DMA_OP_MODE_RTC_Pos)
129 #define ETHERNET_DMA_OP_MODE_RTC_32 (1 << ETHERNET_DMA_OP_MODE_RTC_Pos)
130 #define ETHERNET_DMA_OP_MODE_RTC_96 (2 << ETHERNET_DMA_OP_MODE_RTC_Pos)
131 #define ETHERNET_DMA_OP_MODE_RTC_128 (3 << ETHERNET_DMA_OP_MODE_RTC_Pos)
132 
133 //Transmit DMA descriptor flags
134 #define ETH_TDES0_OWN 0x80000000
135 #define ETH_TDES0_IC 0x40000000
136 #define ETH_TDES0_LS 0x20000000
137 #define ETH_TDES0_FS 0x10000000
138 #define ETH_TDES0_DC 0x08000000
139 #define ETH_TDES0_DP 0x04000000
140 #define ETH_TDES0_TTSE 0x02000000
141 #define ETH_TDES0_TER 0x00200000
142 #define ETH_TDES0_TCH 0x00100000
143 #define ETH_TDES0_TTSS 0x00020000
144 #define ETH_TDES0_IHE 0x00010000
145 #define ETH_TDES0_ES 0x00008000
146 #define ETH_TDES0_JT 0x00004000
147 #define ETH_TDES0_FF 0x00002000
148 #define ETH_TDES0_IPE 0x00001000
149 #define ETH_TDES0_LCA 0x00000800
150 #define ETH_TDES0_NC 0x00000400
151 #define ETH_TDES0_LCO 0x00000200
152 #define ETH_TDES0_EC 0x00000100
153 #define ETH_TDES0_VF 0x00000080
154 #define ETH_TDES0_CC 0x00000078
155 #define ETH_TDES0_ED 0x00000004
156 #define ETH_TDES0_UF 0x00000002
157 #define ETH_TDES0_DB 0x00000001
158 #define ETH_TDES1_TBS2 0x1FFF0000
159 #define ETH_TDES1_TBS1 0x00001FFF
160 #define ETH_TDES2_B1ADD 0xFFFFFFFF
161 #define ETH_TDES3_B2ADD 0xFFFFFFFF
162 #define ETH_TDES6_TTSL 0xFFFFFFFF
163 #define ETH_TDES7_TTSH 0xFFFFFFFF
164 
165 //Receive DMA descriptor flags
166 #define ETH_RDES0_OWN 0x80000000
167 #define ETH_RDES0_AFM 0x40000000
168 #define ETH_RDES0_FL 0x3FFF0000
169 #define ETH_RDES0_ES 0x00008000
170 #define ETH_RDES0_DE 0x00004000
171 #define ETH_RDES0_SAF 0x00002000
172 #define ETH_RDES0_LE 0x00001000
173 #define ETH_RDES0_OE 0x00000800
174 #define ETH_RDES0_VLAN 0x00000400
175 #define ETH_RDES0_FS 0x00000200
176 #define ETH_RDES0_LS 0x00000100
177 #define ETH_RDES0_TSA 0x00000080
178 #define ETH_RDES0_LCO 0x00000040
179 #define ETH_RDES0_FT 0x00000020
180 #define ETH_RDES0_RWT 0x00000010
181 #define ETH_RDES0_RE 0x00000008
182 #define ETH_RDES0_DBE 0x00000004
183 #define ETH_RDES0_CE 0x00000002
184 #define ETH_RDES0_ESA 0x00000001
185 #define ETH_RDES1_RBS2 0x1FFF0000
186 #define ETH_RDES1_RER 0x00008000
187 #define ETH_RDES1_RCH 0x00004000
188 #define ETH_RDES1_RBS1 0x00001FFF
189 #define ETH_RDES2_B1ADD 0xFFFFFFFF
190 #define ETH_RDES3_B2ADD 0xFFFFFFFF
191 #define ETH_RDES4_PTPVERSION 0x00002000
192 #define ETH_RDES4_PTPTYPE 0x00001000
193 #define ETH_RDES4_MT 0x00000F00
194 #define ETH_RDES4_IPV6 0x00000080
195 #define ETH_RDES4_IPV4 0x00000040
196 #define ETH_RDES6_RTSL 0xFFFFFFFF
197 #define ETH_RDES7_RTSH 0xFFFFFFFF
198 
199 //C++ guard
200 #ifdef __cplusplus
201 extern "C" {
202 #endif
203 
204 
205 /**
206  * @brief Enhanced TX DMA descriptor
207  **/
208 
209 typedef struct
210 {
211  uint32_t tdes0;
212  uint32_t tdes1;
213  uint32_t tdes2;
214  uint32_t tdes3;
215  uint32_t tdes4;
216  uint32_t tdes5;
217  uint32_t tdes6;
218  uint32_t tdes7;
220 
221 
222 /**
223  * @brief Enhanced RX DMA descriptor
224  **/
225 
226 typedef struct
227 {
228  uint32_t rdes0;
229  uint32_t rdes1;
230  uint32_t rdes2;
231  uint32_t rdes3;
232  uint32_t rdes4;
233  uint32_t rdes5;
234  uint32_t rdes6;
235  uint32_t rdes7;
237 
238 
239 //LPC18xx Ethernet MAC driver
240 extern const NicDriver lpc18xxEthDriver;
241 
242 //LPC18xx Ethernet MAC related functions
244 void lpc18xxEthInitGpio(NetInterface *interface);
245 void lpc18xxEthInitDmaDesc(NetInterface *interface);
246 
247 void lpc18xxEthTick(NetInterface *interface);
248 
249 void lpc18xxEthEnableIrq(NetInterface *interface);
250 void lpc18xxEthDisableIrq(NetInterface *interface);
251 void lpc18xxEthEventHandler(NetInterface *interface);
252 
254  const NetBuffer *buffer, size_t offset);
255 
257 
260 
261 void lpc18xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
262  uint8_t regAddr, uint16_t data);
263 
264 uint16_t lpc18xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
265  uint8_t regAddr);
266 
267 uint32_t lpc18xxEthCalcCrc(const void *data, size_t length);
268 
269 //C++ guard
270 #ifdef __cplusplus
271 }
272 #endif
273 
274 #endif
void lpc18xxEthTick(NetInterface *interface)
LPC18xx Ethernet MAC timer handler.
error_t lpc18xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
void lpc18xxEthInitGpio(NetInterface *interface)
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
const NicDriver lpc18xxEthDriver
LPC18xx Ethernet MAC driver.
uint32_t lpc18xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
void lpc18xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t lpc18xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t lpc18xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void lpc18xxEthEventHandler(NetInterface *interface)
LPC18xx Ethernet MAC event handler.
void lpc18xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
Enhanced RX DMA descriptor.
uint16_t regAddr
void lpc18xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
Network interface controller abstraction layer.
error_t lpc18xxEthInit(NetInterface *interface)
LPC18xx Ethernet MAC initialization.
Enhanced TX DMA descriptor.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
error_t lpc18xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void lpc18xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t lpc18xxEthReceivePacket(NetInterface *interface)
Receive a packet.