lpc18xx_eth_driver.h
Go to the documentation of this file.
1 /**
2  * @file lpc18xx_eth_driver.h
3  * @brief LPC1800 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _LPC18XX_ETH_DRIVER_H
30 #define _LPC18XX_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef LPC18XX_ETH_TX_BUFFER_COUNT
37  #define LPC18XX_ETH_TX_BUFFER_COUNT 3
38 #elif (LPC18XX_ETH_TX_BUFFER_COUNT < 1)
39  #error LPC18XX_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef LPC18XX_ETH_TX_BUFFER_SIZE
44  #define LPC18XX_ETH_TX_BUFFER_SIZE 1536
45 #elif (LPC18XX_ETH_TX_BUFFER_SIZE != 1536)
46  #error LPC18XX_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef LPC18XX_ETH_RX_BUFFER_COUNT
51  #define LPC18XX_ETH_RX_BUFFER_COUNT 6
52 #elif (LPC18XX_ETH_RX_BUFFER_COUNT < 1)
53  #error LPC18XX_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef LPC18XX_ETH_RX_BUFFER_SIZE
58  #define LPC18XX_ETH_RX_BUFFER_SIZE 1536
59 #elif (LPC18XX_ETH_RX_BUFFER_SIZE != 1536)
60  #error LPC18XX_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Interrupt priority grouping
64 #ifndef LPC18XX_ETH_IRQ_PRIORITY_GROUPING
65  #define LPC18XX_ETH_IRQ_PRIORITY_GROUPING 4
66 #elif (LPC18XX_ETH_IRQ_PRIORITY_GROUPING < 0)
67  #error LPC18XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
68 #endif
69 
70 //Ethernet interrupt group priority
71 #ifndef LPC18XX_ETH_IRQ_GROUP_PRIORITY
72  #define LPC18XX_ETH_IRQ_GROUP_PRIORITY 6
73 #elif (LPC18XX_ETH_IRQ_GROUP_PRIORITY < 0)
74  #error LPC18XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
75 #endif
76 
77 //Ethernet interrupt subpriority
78 #ifndef LPC18XX_ETH_IRQ_SUB_PRIORITY
79  #define LPC18XX_ETH_IRQ_SUB_PRIORITY 0
80 #elif (LPC18XX_ETH_IRQ_SUB_PRIORITY < 0)
81  #error LPC18XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
82 #endif
83 
84 //CREG6 register
85 #define CREG6_ETHMODE_MII (0 << CREG_CREG6_ETHMODE_Pos)
86 #define CREG6_ETHMODE_RMII (4 << CREG_CREG6_ETHMODE_Pos)
87 
88 //MAC_MII_ADDR register
89 #define ETHERNET_MAC_MII_ADDR_CR_DIV42 (0 << ETHERNET_MAC_MII_ADDR_CR_Pos)
90 #define ETHERNET_MAC_MII_ADDR_CR_DIV62 (1 << ETHERNET_MAC_MII_ADDR_CR_Pos)
91 #define ETHERNET_MAC_MII_ADDR_CR_DIV16 (2 << ETHERNET_MAC_MII_ADDR_CR_Pos)
92 #define ETHERNET_MAC_MII_ADDR_CR_DIV26 (3 << ETHERNET_MAC_MII_ADDR_CR_Pos)
93 #define ETHERNET_MAC_MII_ADDR_CR_DIV102 (4 << ETHERNET_MAC_MII_ADDR_CR_Pos)
94 #define ETHERNET_MAC_MII_ADDR_CR_DIV124 (5 << ETHERNET_MAC_MII_ADDR_CR_Pos)
95 
96 //DMA_BUS_MODE register
97 #define ETHERNET_DMA_BUS_MODE_RPBL_1 (1 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
98 #define ETHERNET_DMA_BUS_MODE_RPBL_2 (2 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
99 #define ETHERNET_DMA_BUS_MODE_RPBL_4 (4 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
100 #define ETHERNET_DMA_BUS_MODE_RPBL_8 (8 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
101 #define ETHERNET_DMA_BUS_MODE_RPBL_16 (16 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
102 #define ETHERNET_DMA_BUS_MODE_RPBL_32 (32 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
103 
104 #define ETHERNET_DMA_BUS_MODE_PR_1_1 (0 << ETHERNET_DMA_BUS_MODE_PR_Pos)
105 #define ETHERNET_DMA_BUS_MODE_PR_2_1 (1 << ETHERNET_DMA_BUS_MODE_PR_Pos)
106 #define ETHERNET_DMA_BUS_MODE_PR_3_1 (2 << ETHERNET_DMA_BUS_MODE_PR_Pos)
107 #define ETHERNET_DMA_BUS_MODE_PR_4_1 (3 << ETHERNET_DMA_BUS_MODE_PR_Pos)
108 
109 #define ETHERNET_DMA_BUS_MODE_PBL_1 (1 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
110 #define ETHERNET_DMA_BUS_MODE_PBL_2 (2 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
111 #define ETHERNET_DMA_BUS_MODE_PBL_4 (4 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
112 #define ETHERNET_DMA_BUS_MODE_PBL_8 (8 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
113 #define ETHERNET_DMA_BUS_MODE_PBL_16 (16 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
114 #define ETHERNET_DMA_BUS_MODE_PBL_32 (32 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
115 
116 //DMA_OP_MODE register
117 #define ETHERNET_DMA_OP_MODE_TTC_64 (0 << ETHERNET_DMA_OP_MODE_TTC_Pos)
118 #define ETHERNET_DMA_OP_MODE_TTC_128 (1 << ETHERNET_DMA_OP_MODE_TTC_Pos)
119 #define ETHERNET_DMA_OP_MODE_TTC_192 (2 << ETHERNET_DMA_OP_MODE_TTC_Pos)
120 #define ETHERNET_DMA_OP_MODE_TTC_256 (3 << ETHERNET_DMA_OP_MODE_TTC_Pos)
121 #define ETHERNET_DMA_OP_MODE_TTC_40 (4 << ETHERNET_DMA_OP_MODE_TTC_Pos)
122 #define ETHERNET_DMA_OP_MODE_TTC_32 (5 << ETHERNET_DMA_OP_MODE_TTC_Pos)
123 #define ETHERNET_DMA_OP_MODE_TTC_24 (6 << ETHERNET_DMA_OP_MODE_TTC_Pos)
124 #define ETHERNET_DMA_OP_MODE_TTC_16 (7 << ETHERNET_DMA_OP_MODE_TTC_Pos)
125 
126 #define ETHERNET_DMA_OP_MODE_RTC_64 (0 << ETHERNET_DMA_OP_MODE_RTC_Pos)
127 #define ETHERNET_DMA_OP_MODE_RTC_32 (1 << ETHERNET_DMA_OP_MODE_RTC_Pos)
128 #define ETHERNET_DMA_OP_MODE_RTC_96 (2 << ETHERNET_DMA_OP_MODE_RTC_Pos)
129 #define ETHERNET_DMA_OP_MODE_RTC_128 (3 << ETHERNET_DMA_OP_MODE_RTC_Pos)
130 
131 //Transmit DMA descriptor flags
132 #define ETH_TDES0_OWN 0x80000000
133 #define ETH_TDES0_IC 0x40000000
134 #define ETH_TDES0_LS 0x20000000
135 #define ETH_TDES0_FS 0x10000000
136 #define ETH_TDES0_DC 0x08000000
137 #define ETH_TDES0_DP 0x04000000
138 #define ETH_TDES0_TTSE 0x02000000
139 #define ETH_TDES0_TER 0x00200000
140 #define ETH_TDES0_TCH 0x00100000
141 #define ETH_TDES0_TTSS 0x00020000
142 #define ETH_TDES0_IHE 0x00010000
143 #define ETH_TDES0_ES 0x00008000
144 #define ETH_TDES0_JT 0x00004000
145 #define ETH_TDES0_FF 0x00002000
146 #define ETH_TDES0_IPE 0x00001000
147 #define ETH_TDES0_LCA 0x00000800
148 #define ETH_TDES0_NC 0x00000400
149 #define ETH_TDES0_LCO 0x00000200
150 #define ETH_TDES0_EC 0x00000100
151 #define ETH_TDES0_VF 0x00000080
152 #define ETH_TDES0_CC 0x00000078
153 #define ETH_TDES0_ED 0x00000004
154 #define ETH_TDES0_UF 0x00000002
155 #define ETH_TDES0_DB 0x00000001
156 #define ETH_TDES1_TBS2 0x1FFF0000
157 #define ETH_TDES1_TBS1 0x00001FFF
158 #define ETH_TDES2_B1ADD 0xFFFFFFFF
159 #define ETH_TDES3_B2ADD 0xFFFFFFFF
160 #define ETH_TDES6_TTSL 0xFFFFFFFF
161 #define ETH_TDES7_TTSH 0xFFFFFFFF
162 
163 //Receive DMA descriptor flags
164 #define ETH_RDES0_OWN 0x80000000
165 #define ETH_RDES0_AFM 0x40000000
166 #define ETH_RDES0_FL 0x3FFF0000
167 #define ETH_RDES0_ES 0x00008000
168 #define ETH_RDES0_DE 0x00004000
169 #define ETH_RDES0_SAF 0x00002000
170 #define ETH_RDES0_LE 0x00001000
171 #define ETH_RDES0_OE 0x00000800
172 #define ETH_RDES0_VLAN 0x00000400
173 #define ETH_RDES0_FS 0x00000200
174 #define ETH_RDES0_LS 0x00000100
175 #define ETH_RDES0_TSA 0x00000080
176 #define ETH_RDES0_LCO 0x00000040
177 #define ETH_RDES0_FT 0x00000020
178 #define ETH_RDES0_RWT 0x00000010
179 #define ETH_RDES0_RE 0x00000008
180 #define ETH_RDES0_DBE 0x00000004
181 #define ETH_RDES0_CE 0x00000002
182 #define ETH_RDES0_ESA 0x00000001
183 #define ETH_RDES1_RBS2 0x1FFF0000
184 #define ETH_RDES1_RER 0x00008000
185 #define ETH_RDES1_RCH 0x00004000
186 #define ETH_RDES1_RBS1 0x00001FFF
187 #define ETH_RDES2_B1ADD 0xFFFFFFFF
188 #define ETH_RDES3_B2ADD 0xFFFFFFFF
189 #define ETH_RDES4_PTPVERSION 0x00002000
190 #define ETH_RDES4_PTPTYPE 0x00001000
191 #define ETH_RDES4_MT 0x00000F00
192 #define ETH_RDES4_IPV6 0x00000080
193 #define ETH_RDES4_IPV4 0x00000040
194 #define ETH_RDES6_RTSL 0xFFFFFFFF
195 #define ETH_RDES7_RTSH 0xFFFFFFFF
196 
197 //C++ guard
198 #ifdef __cplusplus
199  extern "C" {
200 #endif
201 
202 
203 /**
204  * @brief Enhanced TX DMA descriptor
205  **/
206 
207 typedef struct
208 {
209  uint32_t tdes0;
210  uint32_t tdes1;
211  uint32_t tdes2;
212  uint32_t tdes3;
213  uint32_t tdes4;
214  uint32_t tdes5;
215  uint32_t tdes6;
216  uint32_t tdes7;
218 
219 
220 /**
221  * @brief Enhanced RX DMA descriptor
222  **/
223 
224 typedef struct
225 {
226  uint32_t rdes0;
227  uint32_t rdes1;
228  uint32_t rdes2;
229  uint32_t rdes3;
230  uint32_t rdes4;
231  uint32_t rdes5;
232  uint32_t rdes6;
233  uint32_t rdes7;
235 
236 
237 //LPC18xx Ethernet MAC driver
238 extern const NicDriver lpc18xxEthDriver;
239 
240 //LPC18xx Ethernet MAC related functions
242 void lpc18xxEthInitGpio(NetInterface *interface);
243 void lpc18xxEthInitDmaDesc(NetInterface *interface);
244 
245 void lpc18xxEthTick(NetInterface *interface);
246 
247 void lpc18xxEthEnableIrq(NetInterface *interface);
248 void lpc18xxEthDisableIrq(NetInterface *interface);
249 void lpc18xxEthEventHandler(NetInterface *interface);
250 
252  const NetBuffer *buffer, size_t offset);
253 
255 
258 
259 void lpc18xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
260 uint16_t lpc18xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
261 
262 uint32_t lpc18xxEthCalcCrc(const void *data, size_t length);
263 
264 //C++ guard
265 #ifdef __cplusplus
266  }
267 #endif
268 
269 #endif
uint16_t lpc18xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void lpc18xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
void lpc18xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t lpc18xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t lpc18xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t lpc18xxEthReceivePacket(NetInterface *interface)
Receive a packet.
error_t lpc18xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
const NicDriver lpc18xxEthDriver
LPC18xx Ethernet MAC driver.
void lpc18xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void lpc18xxEthTick(NetInterface *interface)
LPC18xx Ethernet MAC timer handler.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
Enhanced RX DMA descriptor.
void lpc18xxEthInitGpio(NetInterface *interface)
uint16_t regAddr
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
Enhanced TX DMA descriptor.
void lpc18xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
void lpc18xxEthEventHandler(NetInterface *interface)
LPC18xx Ethernet MAC event handler.
uint8_t length
Definition: dtls_misc.h:140
error_t lpc18xxEthInit(NetInterface *interface)
LPC18xx Ethernet MAC initialization.
Network interface controller abstraction layer.
uint32_t lpc18xxEthCalcCrc(const void *data, size_t length)
CRC calculation.