lpc23xx_eth_driver.h
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1 /**
2  * @file lpc23xx_eth_driver.h
3  * @brief LPC2300 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _LPC23XX_ETH_DRIVER_H
30 #define _LPC23XX_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef LPC23XX_ETH_TX_BUFFER_COUNT
37  #define LPC23XX_ETH_TX_BUFFER_COUNT 2
38 #elif (LPC23XX_ETH_TX_BUFFER_COUNT < 1)
39  #error LPC23XX_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef LPC23XX_ETH_TX_BUFFER_SIZE
44  #define LPC23XX_ETH_TX_BUFFER_SIZE 1536
45 #elif (LPC23XX_ETH_TX_BUFFER_SIZE != 1536)
46  #error LPC23XX_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef LPC23XX_ETH_RX_BUFFER_COUNT
51  #define LPC23XX_ETH_RX_BUFFER_COUNT 4
52 #elif (LPC23XX_ETH_RX_BUFFER_COUNT < 1)
53  #error LPC23XX_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef LPC23XX_ETH_RX_BUFFER_SIZE
58  #define LPC23XX_ETH_RX_BUFFER_SIZE 1536
59 #elif (LPC23XX_ETH_RX_BUFFER_SIZE != 1536)
60  #error LPC23XX_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Ethernet interrupt priority
64 #ifndef LPC23XX_ETH_IRQ_PRIORITY
65  #define LPC23XX_ETH_IRQ_PRIORITY 15
66 #elif (LPC23XX_ETH_IRQ_PRIORITY < 0)
67  #error LPC23XX_ETH_IRQ_PRIORITY parameter is not valid
68 #endif
69 
70 //MAC1 register
71 #define MAC1_SOFT_RESET 0x00008000
72 #define MAC1_SIMULATION_RESET 0x00004000
73 #define MAC1_RESET_MCS_RX 0x00000800
74 #define MAC1_RESET_RX 0x00000400
75 #define MAC1_RESET_MCS_TX 0x00000200
76 #define MAC1_RESET_TX 0x00000100
77 #define MAC1_LOOPBACK 0x00000010
78 #define MAC1_TX_FLOW_CONTROL 0x00000008
79 #define MAC1_RX_FLOW_CONTROL 0x00000004
80 #define MAC1_PASS_ALL_FRAMES 0x00000002
81 #define MAC1_RECEIVE_ENABLE 0x00000001
82 
83 //MAC2 register
84 #define MAC2_EXCESS_DEFER 0x00004000
85 #define MAC2_BACK_PRESSURE_NO_BACKOFF 0x00002000
86 #define MAC2_NO_BACKOFF 0x00001000
87 #define MAC2_LONG_PREAMBLE_ENFORCEMENT 0x00000200
88 #define MAC2_PURE_PREAMBLE_ENFORCEMENT 0x00000100
89 #define MAC2_AUTO_DETECT_PAD_ENABLE 0x00000080
90 #define MAC2_VLAN_PAD_ENABLE 0x00000040
91 #define MAC2_PAD_CRC_ENABLE 0x00000020
92 #define MAC2_CRC_ENABLE 0x00000010
93 #define MAC2_DELAYED_CRC 0x00000008
94 #define MAC2_HUGE_FRAME_ENABLE 0x00000004
95 #define MAC2_FRAME_LENGTH_CHECKING 0x00000002
96 #define MAC2_FULL_DUPLEX 0x00000001
97 
98 //IPGT register
99 #define IPGT_BACK_TO_BACK_IPG 0x0000007F
100 #define IPGT_HALF_DUPLEX 0x00000012
101 #define IPGT_FULL_DUPLEX 0x00000015
102 
103 //IPGR register
104 #define IPGR_NON_BACK_TO_BACK_IPG1 0x00007F00
105 #define IPGR_NON_BACK_TO_BACK_IPG2 0x0000007F
106 #define IPGR_DEFAULT_VALUE 0x00000C12
107 
108 //CLRT register
109 #define CLRT_COLLISION_WINDOW 0x00003F00
110 #define CLRT_RETRANSMISSION_MAXIMUM 0x00003F00
111 #define CLRT_DEFAULT_VALUE 0x0000370F
112 
113 //MAXF register
114 #define MAXF_MAXIMUM_FRAME_LENGTH 0x0000FFFF
115 
116 //SUPP register
117 #define SUPP_SPEED 0x00000100
118 
119 //TEST register
120 #define TEST_BACKPRESSURE 0x00000004
121 #define TEST_PAUSE 0x00000002
122 #define TEST_SHORTCUT_PAUSE_QUANTA 0x00000001
123 
124 //MCFG register
125 #define MCFG_RESET_MII_MGMT 0x00008000
126 #define MCFG_CLOCK SELECT 0x0000001C
127 #define MCFG_SUPPRESS_PREAMBLE 0x00000002
128 #define MCFG_SCAN_INCREMENT 0x00000001
129 
130 #define MCFG_CLOCK_SELECT_DIV4 0x00000000
131 #define MCFG_CLOCK_SELECT_DIV6 0x00000008
132 #define MCFG_CLOCK_SELECT_DIV8 0x0000000C
133 #define MCFG_CLOCK_SELECT_DIV10 0x00000010
134 #define MCFG_CLOCK_SELECT_DIV14 0x00000014
135 #define MCFG_CLOCK_SELECT_DIV20 0x00000018
136 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
137 
138 //MCMD register
139 #define MCMD_SCAN 0x00000002
140 #define MCMD_READ 0x00000001
141 
142 //MADR register
143 #define MADR_PHY_ADDRESS 0x00001F00
144 #define MADR_REGISTER_ADDRESS 0x0000001F
145 
146 //MWTD register
147 #define MWTD_WRITE_DATA 0x0000FFFF
148 
149 //MRDD register
150 #define MRDD_READ_DATA 0x0000FFFF
151 
152 //MIND register
153 #define MIND_MII_LINK_FAIL 0x00000008
154 #define MIND_NOT_VALID 0x00000004
155 #define MIND_SCANNING 0x00000002
156 #define MIND_BUSY 0x00000001
157 
158 //Command register
159 #define COMMAND_FULL_DUPLEX 0x00000400
160 #define COMMAND_RMII 0x00000200
161 #define COMMAND_TX_FLOW_CONTROL 0x00000100
162 #define COMMAND_PASS_RX_FILTER 0x00000080
163 #define COMMAND_PASS_RUNT_FRAME 0x00000040
164 #define COMMAND_RX_RESET 0x00000020
165 #define COMMAND_TX_RESET 0x00000010
166 #define COMMAND_REG_RESET 0x00000008
167 #define COMMAND_TX_ENABLE 0x00000002
168 #define COMMAND_RX_ENABLE 0x00000001
169 
170 //Status register
171 #define STATUS_TX 0x00000002
172 #define STATUS_RX 0x00000001
173 
174 //TSV0 register
175 #define TSV0_VLAN 0x80000000
176 #define TSV0_BACKPRESSURE 0x40000000
177 #define TSV0_PAUSE 0x20000000
178 #define TSV0_CONTROL_FRAME 0x10000000
179 #define TSV0_TOTAL_BYTES 0x0FFFF000
180 #define TSV0_UNDERRUN 0x00000800
181 #define TSV0_GIANT 0x00000400
182 #define TSV0_LATE_COLLISION 0x00000200
183 #define TSV0_EXCESSIVE_COLLISION 0x00000100
184 #define TSV0_EXCESSIVE_DEFER 0x00000080
185 #define TSV0_PACKET_DEFER 0x00000040
186 #define TSV0_BROADCAST 0x00000020
187 #define TSV0_MULTICAST 0x00000010
188 #define TSV0_DONE 0x00000008
189 #define TSV0_LENGTH_OUT_OF_RANGE 0x00000004
190 #define TSV0_LENGTH_CHECK_ERROR 0x00000002
191 #define TSV0_CRC_ERROR 0x00000001
192 
193 //TSV1 register
194 #define TSV1_TRANSMIT_COLLISION_COUNT 0x000F0000
195 #define TSV1_TRANSMIT_BYTE_COUNT 0x0000FFFF
196 
197 //RSV register
198 #define RSV_VLAN 0x40000000
199 #define RSV_UNSUPPORTED_OPCODE 0x20000000
200 #define RSV_PAUSE 0x10000000
201 #define RSV_CONTROL_FRAME 0x08000000
202 #define RSV_DRIBBLE_NIBBLE 0x04000000
203 #define RSV_BROADCAST 0x02000000
204 #define RSV_MULTICAST 0x01000000
205 #define RSV_RECEIVE_OK 0x00800000
206 #define RSV_LENGTH_OUT_OF_RANGE 0x00400000
207 #define RSV_LENGTH_CHECK_ERROR 0x00200000
208 #define RSV_CRC_ERROR 0x00100000
209 #define RSV_RECEIVE_CODE_VIOLATION 0x00080000
210 #define RSV_CARRIER_EVENT_PREV_SEEN 0x00040000
211 #define RSV_RXDV_EVENT_PREV_SEEN 0x00020000
212 #define RSV_PACKET_PREVIOUSLY_IGNORED 0x00010000
213 #define RSV_RECEIVED_BYTE_COUNT 0x0000FFFF
214 
215 //FlowControlCounter register
216 #define FCC_PAUSE_TIMER 0xFFFF0000
217 #define FCC_MIRROR_COUNTER 0x0000FFFF
218 
219 //FlowControlStatus register
220 #define FCS_MIRROR_COUNTER_CURRENT 0x0000FFFF
221 
222 //RxFilterCtrl register
223 #define RFC_RX_FILTER_EN_WOL 0x00002000
224 #define RFC_MAGIC_PACKET_EN_WOL 0x00001000
225 #define RFC_ACCEPT_PERFECT_EN 0x00000020
226 #define RFC_ACCEPT_MULTICAST_HASH_EN 0x00000010
227 #define RFC_ACCEPT_UNICAST_HASH_EN 0x00000008
228 #define RFC_ACCEPT_MULTICAST_EN 0x00000004
229 #define RFC_ACCEPT_BROADCAST_EN 0x00000002
230 #define RFC_ACCEPT_UNICAST_EN 0x00000001
231 
232 //RxFilterWoLStatus and RxFilterWoLClear registers
233 #define RFWS_MAGIC_PACKET_WOL 0x00000100
234 #define RFWS_RX_FILTER_WOL 0x00000080
235 #define RFWS_ACCEPT_PERFECT_WOL 0x00000020
236 #define RFWS_ACCEPT_MULTICAST_HASH_WOL 0x00000010
237 #define RFWS_ACCEPT_UNICAST_HASH_WOL 0x00000008
238 #define RFWS_ACCEPT_MULTICAST_WOL 0x00000004
239 #define RFWS_ACCEPT_BROADCAST_WOL 0x00000002
240 #define RFWS_ACCEPT_UNICAST_WOL 0x00000001
241 
242 //IntStatus, IntEnable, IntClear and IntSet registers
243 #define INT_WAKEUP 0x00002000
244 #define INT_SOFT_INT 0x00001000
245 #define INT_TX_DONE 0x00000080
246 #define INT_TX_FINISHED 0x00000040
247 #define INT_TX_ERROR 0x00000020
248 #define INT_TX_UNDERRUN 0x00000010
249 #define INT_RX_DONE 0x00000008
250 #define INT_RX_FINISHED 0x00000004
251 #define INT_RX_ERROR 0x00000002
252 #define INT_RX_OVERRUN 0x00000001
253 
254 //Transmit descriptor control word
255 #define TX_CTRL_INTERRUPT 0x80000000
256 #define TX_CTRL_LAST 0x40000000
257 #define TX_CTRL_CRC 0x20000000
258 #define TX_CTRL_PAD 0x10000000
259 #define TX_CTRL_HUGE 0x08000000
260 #define TX_CTRL_OVERRIDE 0x04000000
261 #define TX_CTRL_SIZE 0x000007FF
262 
263 //Transmit status information word
264 #define TX_STATUS_ERROR 0x80000000
265 #define TX_STATUS_NO_DESCRIPTOR 0x40000000
266 #define TX_STATUS_UNDERRUN 0x20000000
267 #define TX_STATUS_LATE_COLLISION 0x10000000
268 #define TX_STATUS_EXCESSIVE_COLLISION 0x08000000
269 #define TX_STATUS_EXCESSIVE_DEFER 0x04000000
270 #define TX_STATUS_DEFER 0x02000000
271 #define TX_STATUS_COLLISION_COUNT 0x01E00000
272 
273 //Receive descriptor control word
274 #define RX_CTRL_INTERRUPT 0x80000000
275 #define RX_CTRL_SIZE 0x000007FF
276 
277 //Receive status information word
278 #define RX_STATUS_ERROR 0x80000000
279 #define RX_STATUS_LAST_FLAG 0x40000000
280 #define RX_STATUS_NO_DESCRIPTOR 0x20000000
281 #define RX_STATUS_OVERRUN 0x10000000
282 #define RX_STATUS_ALIGNMENT_ERROR 0x08000000
283 #define RX_STATUS_RANGE_ERROR 0x04000000
284 #define RX_STATUS_LENGTH_ERROR 0x02000000
285 #define RX_STATUS_SYMBOL_ERROR 0x01000000
286 #define RX_STATUS_CRC_ERROR 0x00800000
287 #define RX_STATUS_BROADCAST 0x00400000
288 #define RX_STATUS_MULTICAST 0x00200000
289 #define RX_STATUS_FAIL_FILTER 0x00100000
290 #define RX_STATUS_VLAN 0x00080000
291 #define RX_STATUS_CONTROL_FRAME 0x00040000
292 #define RX_STATUS_SIZE 0x000007FF
293 
294 //Receive status HashCRC word
295 #define RX_HASH_CRC_DA 0x001FF000
296 #define RX_HASH_CRC_SA 0x000001FF
297 
298 //C++ guard
299 #ifdef __cplusplus
300  extern "C" {
301 #endif
302 
303 
304 /**
305  * @brief Transmit descriptor
306  **/
307 
308 typedef struct
309 {
310  uint32_t packet;
311  uint32_t control;
312 } Lpc23xxTxDesc;
313 
314 
315 /**
316  * @brief Transmit status
317  **/
318 
319 typedef struct
320 {
321  uint32_t info;
323 
324 
325 /**
326  * @brief Receive descriptor
327  **/
328 
329 typedef struct
330 {
331  uint32_t packet;
332  uint32_t control;
333 } Lpc23xxRxDesc;
334 
335 
336 /**
337  * @brief Receive status
338  **/
339 
340 typedef struct
341 {
342  uint32_t info;
343  uint32_t hashCrc;
345 
346 
347 //LPC23xx Ethernet MAC driver
348 extern const NicDriver lpc23xxEthDriver;
349 
350 //LPC23xx Ethernet MAC related functions
352 void lpc23xxEthInitGpio(NetInterface *interface);
353 void lpc23xxEthInitDesc(NetInterface *interface);
354 
355 void lpc23xxEthTick(NetInterface *interface);
356 
357 void lpc23xxEthEnableIrq(NetInterface *interface);
358 void lpc23xxEthDisableIrq(NetInterface *interface);
359 __irq void lpc23xxEthIrqHandler(void);
360 void lpc23xxEthEventHandler(NetInterface *interface);
361 
363  const NetBuffer *buffer, size_t offset);
364 
366 
369 
370 void lpc23xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
371 uint16_t lpc23xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
372 
373 uint32_t lpc23xxEthCalcCrc(const void *data, size_t length);
374 
375 //C++ guard
376 #ifdef __cplusplus
377  }
378 #endif
379 
380 #endif
uint32_t lpc23xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
void lpc23xxEthTick(NetInterface *interface)
LPC23xx Ethernet MAC timer handler.
Receive descriptor.
error_t lpc23xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t lpc23xxEthInit(NetInterface *interface)
LPC23xx Ethernet MAC initialization.
void lpc23xxEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
error_t lpc23xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void lpc23xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t lpc23xxEthReceivePacket(NetInterface *interface)
Receive a packet.
const NicDriver lpc23xxEthDriver
LPC23xx Ethernet MAC driver.
__irq void lpc23xxEthIrqHandler(void)
LPC23xx Ethernet MAC interrupt service routine.
NIC driver.
Definition: nic.h:161
void lpc23xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
uint16_t regAddr
void lpc23xxEthInitGpio(NetInterface *interface)
uint16_t lpc23xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t
Error codes.
Definition: error.h:40
void lpc23xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
Transmit descriptor.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
error_t lpc23xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void lpc23xxEthEventHandler(NetInterface *interface)
LPC23xx Ethernet MAC event handler.
Receive status.
Transmit status.
uint8_t length
Definition: dtls_misc.h:140
Network interface controller abstraction layer.