lpc23xx_eth_driver.h
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1 /**
2  * @file lpc23xx_eth_driver.h
3  * @brief LPC2300 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _LPC23XX_ETH_DRIVER_H
32 #define _LPC23XX_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef LPC23XX_ETH_TX_BUFFER_COUNT
39  #define LPC23XX_ETH_TX_BUFFER_COUNT 2
40 #elif (LPC23XX_ETH_TX_BUFFER_COUNT < 1)
41  #error LPC23XX_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef LPC23XX_ETH_TX_BUFFER_SIZE
46  #define LPC23XX_ETH_TX_BUFFER_SIZE 1536
47 #elif (LPC23XX_ETH_TX_BUFFER_SIZE != 1536)
48  #error LPC23XX_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef LPC23XX_ETH_RX_BUFFER_COUNT
53  #define LPC23XX_ETH_RX_BUFFER_COUNT 4
54 #elif (LPC23XX_ETH_RX_BUFFER_COUNT < 1)
55  #error LPC23XX_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef LPC23XX_ETH_RX_BUFFER_SIZE
60  #define LPC23XX_ETH_RX_BUFFER_SIZE 1536
61 #elif (LPC23XX_ETH_RX_BUFFER_SIZE != 1536)
62  #error LPC23XX_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Ethernet interrupt priority
66 #ifndef LPC23XX_ETH_IRQ_PRIORITY
67  #define LPC23XX_ETH_IRQ_PRIORITY 15
68 #elif (LPC23XX_ETH_IRQ_PRIORITY < 0)
69  #error LPC23XX_ETH_IRQ_PRIORITY parameter is not valid
70 #endif
71 
72 //MAC1 register
73 #define MAC1_SOFT_RESET 0x00008000
74 #define MAC1_SIMULATION_RESET 0x00004000
75 #define MAC1_RESET_MCS_RX 0x00000800
76 #define MAC1_RESET_RX 0x00000400
77 #define MAC1_RESET_MCS_TX 0x00000200
78 #define MAC1_RESET_TX 0x00000100
79 #define MAC1_LOOPBACK 0x00000010
80 #define MAC1_TX_FLOW_CONTROL 0x00000008
81 #define MAC1_RX_FLOW_CONTROL 0x00000004
82 #define MAC1_PASS_ALL_FRAMES 0x00000002
83 #define MAC1_RECEIVE_ENABLE 0x00000001
84 
85 //MAC2 register
86 #define MAC2_EXCESS_DEFER 0x00004000
87 #define MAC2_BACK_PRESSURE_NO_BACKOFF 0x00002000
88 #define MAC2_NO_BACKOFF 0x00001000
89 #define MAC2_LONG_PREAMBLE_ENFORCEMENT 0x00000200
90 #define MAC2_PURE_PREAMBLE_ENFORCEMENT 0x00000100
91 #define MAC2_AUTO_DETECT_PAD_ENABLE 0x00000080
92 #define MAC2_VLAN_PAD_ENABLE 0x00000040
93 #define MAC2_PAD_CRC_ENABLE 0x00000020
94 #define MAC2_CRC_ENABLE 0x00000010
95 #define MAC2_DELAYED_CRC 0x00000008
96 #define MAC2_HUGE_FRAME_ENABLE 0x00000004
97 #define MAC2_FRAME_LENGTH_CHECKING 0x00000002
98 #define MAC2_FULL_DUPLEX 0x00000001
99 
100 //IPGT register
101 #define IPGT_BACK_TO_BACK_IPG 0x0000007F
102 #define IPGT_HALF_DUPLEX 0x00000012
103 #define IPGT_FULL_DUPLEX 0x00000015
104 
105 //IPGR register
106 #define IPGR_NON_BACK_TO_BACK_IPG1 0x00007F00
107 #define IPGR_NON_BACK_TO_BACK_IPG2 0x0000007F
108 #define IPGR_DEFAULT_VALUE 0x00000C12
109 
110 //CLRT register
111 #define CLRT_COLLISION_WINDOW 0x00003F00
112 #define CLRT_RETRANSMISSION_MAXIMUM 0x00003F00
113 #define CLRT_DEFAULT_VALUE 0x0000370F
114 
115 //MAXF register
116 #define MAXF_MAXIMUM_FRAME_LENGTH 0x0000FFFF
117 
118 //SUPP register
119 #define SUPP_SPEED 0x00000100
120 
121 //TEST register
122 #define TEST_BACKPRESSURE 0x00000004
123 #define TEST_PAUSE 0x00000002
124 #define TEST_SHORTCUT_PAUSE_QUANTA 0x00000001
125 
126 //MCFG register
127 #define MCFG_RESET_MII_MGMT 0x00008000
128 #define MCFG_CLOCK SELECT 0x0000001C
129 #define MCFG_SUPPRESS_PREAMBLE 0x00000002
130 #define MCFG_SCAN_INCREMENT 0x00000001
131 
132 #define MCFG_CLOCK_SELECT_DIV4 0x00000000
133 #define MCFG_CLOCK_SELECT_DIV6 0x00000008
134 #define MCFG_CLOCK_SELECT_DIV8 0x0000000C
135 #define MCFG_CLOCK_SELECT_DIV10 0x00000010
136 #define MCFG_CLOCK_SELECT_DIV14 0x00000014
137 #define MCFG_CLOCK_SELECT_DIV20 0x00000018
138 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
139 
140 //MCMD register
141 #define MCMD_SCAN 0x00000002
142 #define MCMD_READ 0x00000001
143 
144 //MADR register
145 #define MADR_PHY_ADDRESS 0x00001F00
146 #define MADR_REGISTER_ADDRESS 0x0000001F
147 
148 //MWTD register
149 #define MWTD_WRITE_DATA 0x0000FFFF
150 
151 //MRDD register
152 #define MRDD_READ_DATA 0x0000FFFF
153 
154 //MIND register
155 #define MIND_MII_LINK_FAIL 0x00000008
156 #define MIND_NOT_VALID 0x00000004
157 #define MIND_SCANNING 0x00000002
158 #define MIND_BUSY 0x00000001
159 
160 //Command register
161 #define COMMAND_FULL_DUPLEX 0x00000400
162 #define COMMAND_RMII 0x00000200
163 #define COMMAND_TX_FLOW_CONTROL 0x00000100
164 #define COMMAND_PASS_RX_FILTER 0x00000080
165 #define COMMAND_PASS_RUNT_FRAME 0x00000040
166 #define COMMAND_RX_RESET 0x00000020
167 #define COMMAND_TX_RESET 0x00000010
168 #define COMMAND_REG_RESET 0x00000008
169 #define COMMAND_TX_ENABLE 0x00000002
170 #define COMMAND_RX_ENABLE 0x00000001
171 
172 //Status register
173 #define STATUS_TX 0x00000002
174 #define STATUS_RX 0x00000001
175 
176 //TSV0 register
177 #define TSV0_VLAN 0x80000000
178 #define TSV0_BACKPRESSURE 0x40000000
179 #define TSV0_PAUSE 0x20000000
180 #define TSV0_CONTROL_FRAME 0x10000000
181 #define TSV0_TOTAL_BYTES 0x0FFFF000
182 #define TSV0_UNDERRUN 0x00000800
183 #define TSV0_GIANT 0x00000400
184 #define TSV0_LATE_COLLISION 0x00000200
185 #define TSV0_EXCESSIVE_COLLISION 0x00000100
186 #define TSV0_EXCESSIVE_DEFER 0x00000080
187 #define TSV0_PACKET_DEFER 0x00000040
188 #define TSV0_BROADCAST 0x00000020
189 #define TSV0_MULTICAST 0x00000010
190 #define TSV0_DONE 0x00000008
191 #define TSV0_LENGTH_OUT_OF_RANGE 0x00000004
192 #define TSV0_LENGTH_CHECK_ERROR 0x00000002
193 #define TSV0_CRC_ERROR 0x00000001
194 
195 //TSV1 register
196 #define TSV1_TRANSMIT_COLLISION_COUNT 0x000F0000
197 #define TSV1_TRANSMIT_BYTE_COUNT 0x0000FFFF
198 
199 //RSV register
200 #define RSV_VLAN 0x40000000
201 #define RSV_UNSUPPORTED_OPCODE 0x20000000
202 #define RSV_PAUSE 0x10000000
203 #define RSV_CONTROL_FRAME 0x08000000
204 #define RSV_DRIBBLE_NIBBLE 0x04000000
205 #define RSV_BROADCAST 0x02000000
206 #define RSV_MULTICAST 0x01000000
207 #define RSV_RECEIVE_OK 0x00800000
208 #define RSV_LENGTH_OUT_OF_RANGE 0x00400000
209 #define RSV_LENGTH_CHECK_ERROR 0x00200000
210 #define RSV_CRC_ERROR 0x00100000
211 #define RSV_RECEIVE_CODE_VIOLATION 0x00080000
212 #define RSV_CARRIER_EVENT_PREV_SEEN 0x00040000
213 #define RSV_RXDV_EVENT_PREV_SEEN 0x00020000
214 #define RSV_PACKET_PREVIOUSLY_IGNORED 0x00010000
215 #define RSV_RECEIVED_BYTE_COUNT 0x0000FFFF
216 
217 //FlowControlCounter register
218 #define FCC_PAUSE_TIMER 0xFFFF0000
219 #define FCC_MIRROR_COUNTER 0x0000FFFF
220 
221 //FlowControlStatus register
222 #define FCS_MIRROR_COUNTER_CURRENT 0x0000FFFF
223 
224 //RxFilterCtrl register
225 #define RFC_RX_FILTER_EN_WOL 0x00002000
226 #define RFC_MAGIC_PACKET_EN_WOL 0x00001000
227 #define RFC_ACCEPT_PERFECT_EN 0x00000020
228 #define RFC_ACCEPT_MULTICAST_HASH_EN 0x00000010
229 #define RFC_ACCEPT_UNICAST_HASH_EN 0x00000008
230 #define RFC_ACCEPT_MULTICAST_EN 0x00000004
231 #define RFC_ACCEPT_BROADCAST_EN 0x00000002
232 #define RFC_ACCEPT_UNICAST_EN 0x00000001
233 
234 //RxFilterWoLStatus and RxFilterWoLClear registers
235 #define RFWS_MAGIC_PACKET_WOL 0x00000100
236 #define RFWS_RX_FILTER_WOL 0x00000080
237 #define RFWS_ACCEPT_PERFECT_WOL 0x00000020
238 #define RFWS_ACCEPT_MULTICAST_HASH_WOL 0x00000010
239 #define RFWS_ACCEPT_UNICAST_HASH_WOL 0x00000008
240 #define RFWS_ACCEPT_MULTICAST_WOL 0x00000004
241 #define RFWS_ACCEPT_BROADCAST_WOL 0x00000002
242 #define RFWS_ACCEPT_UNICAST_WOL 0x00000001
243 
244 //IntStatus, IntEnable, IntClear and IntSet registers
245 #define INT_WAKEUP 0x00002000
246 #define INT_SOFT_INT 0x00001000
247 #define INT_TX_DONE 0x00000080
248 #define INT_TX_FINISHED 0x00000040
249 #define INT_TX_ERROR 0x00000020
250 #define INT_TX_UNDERRUN 0x00000010
251 #define INT_RX_DONE 0x00000008
252 #define INT_RX_FINISHED 0x00000004
253 #define INT_RX_ERROR 0x00000002
254 #define INT_RX_OVERRUN 0x00000001
255 
256 //Transmit descriptor control word
257 #define TX_CTRL_INTERRUPT 0x80000000
258 #define TX_CTRL_LAST 0x40000000
259 #define TX_CTRL_CRC 0x20000000
260 #define TX_CTRL_PAD 0x10000000
261 #define TX_CTRL_HUGE 0x08000000
262 #define TX_CTRL_OVERRIDE 0x04000000
263 #define TX_CTRL_SIZE 0x000007FF
264 
265 //Transmit status information word
266 #define TX_STATUS_ERROR 0x80000000
267 #define TX_STATUS_NO_DESCRIPTOR 0x40000000
268 #define TX_STATUS_UNDERRUN 0x20000000
269 #define TX_STATUS_LATE_COLLISION 0x10000000
270 #define TX_STATUS_EXCESSIVE_COLLISION 0x08000000
271 #define TX_STATUS_EXCESSIVE_DEFER 0x04000000
272 #define TX_STATUS_DEFER 0x02000000
273 #define TX_STATUS_COLLISION_COUNT 0x01E00000
274 
275 //Receive descriptor control word
276 #define RX_CTRL_INTERRUPT 0x80000000
277 #define RX_CTRL_SIZE 0x000007FF
278 
279 //Receive status information word
280 #define RX_STATUS_ERROR 0x80000000
281 #define RX_STATUS_LAST_FLAG 0x40000000
282 #define RX_STATUS_NO_DESCRIPTOR 0x20000000
283 #define RX_STATUS_OVERRUN 0x10000000
284 #define RX_STATUS_ALIGNMENT_ERROR 0x08000000
285 #define RX_STATUS_RANGE_ERROR 0x04000000
286 #define RX_STATUS_LENGTH_ERROR 0x02000000
287 #define RX_STATUS_SYMBOL_ERROR 0x01000000
288 #define RX_STATUS_CRC_ERROR 0x00800000
289 #define RX_STATUS_BROADCAST 0x00400000
290 #define RX_STATUS_MULTICAST 0x00200000
291 #define RX_STATUS_FAIL_FILTER 0x00100000
292 #define RX_STATUS_VLAN 0x00080000
293 #define RX_STATUS_CONTROL_FRAME 0x00040000
294 #define RX_STATUS_SIZE 0x000007FF
295 
296 //Receive status HashCRC word
297 #define RX_HASH_CRC_DA 0x001FF000
298 #define RX_HASH_CRC_SA 0x000001FF
299 
300 //C++ guard
301 #ifdef __cplusplus
302 extern "C" {
303 #endif
304 
305 
306 /**
307  * @brief Transmit descriptor
308  **/
309 
310 typedef struct
311 {
312  uint32_t packet;
313  uint32_t control;
314 } Lpc23xxTxDesc;
315 
316 
317 /**
318  * @brief Transmit status
319  **/
320 
321 typedef struct
322 {
323  uint32_t info;
325 
326 
327 /**
328  * @brief Receive descriptor
329  **/
330 
331 typedef struct
332 {
333  uint32_t packet;
334  uint32_t control;
335 } Lpc23xxRxDesc;
336 
337 
338 /**
339  * @brief Receive status
340  **/
341 
342 typedef struct
343 {
344  uint32_t info;
345  uint32_t hashCrc;
347 
348 
349 //LPC23xx Ethernet MAC driver
350 extern const NicDriver lpc23xxEthDriver;
351 
352 //LPC23xx Ethernet MAC related functions
354 void lpc23xxEthInitGpio(NetInterface *interface);
355 void lpc23xxEthInitDesc(NetInterface *interface);
356 
357 void lpc23xxEthTick(NetInterface *interface);
358 
359 void lpc23xxEthEnableIrq(NetInterface *interface);
360 void lpc23xxEthDisableIrq(NetInterface *interface);
361 __irq void lpc23xxEthIrqHandler(void);
362 void lpc23xxEthEventHandler(NetInterface *interface);
363 
365  const NetBuffer *buffer, size_t offset);
366 
368 
371 
372 void lpc23xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
373  uint8_t regAddr, uint16_t data);
374 
375 uint16_t lpc23xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
376  uint8_t regAddr);
377 
378 uint32_t lpc23xxEthCalcCrc(const void *data, size_t length);
379 
380 //C++ guard
381 #ifdef __cplusplus
382 }
383 #endif
384 
385 #endif
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void lpc23xxEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
error_t lpc23xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void lpc23xxEthEventHandler(NetInterface *interface)
LPC23xx Ethernet MAC event handler.
void lpc23xxEthTick(NetInterface *interface)
LPC23xx Ethernet MAC timer handler.
error_t lpc23xxEthInit(NetInterface *interface)
LPC23xx Ethernet MAC initialization.
error_t
Error codes.
Definition: error.h:42
Transmit descriptor.
void lpc23xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver lpc23xxEthDriver
LPC23xx Ethernet MAC driver.
#define NetInterface
Definition: net.h:36
error_t lpc23xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint32_t lpc23xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t lpc23xxEthReceivePacket(NetInterface *interface)
Receive a packet.
void lpc23xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
__irq void lpc23xxEthIrqHandler(void)
LPC23xx Ethernet MAC interrupt service routine.
error_t lpc23xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint16_t regAddr
void lpc23xxEthInitGpio(NetInterface *interface)
uint16_t lpc23xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Network interface controller abstraction layer.
void lpc23xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
Receive status.
Transmit status.
Receive descriptor.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179