lpc23xx_eth_driver.c
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1 /**
2  * @file lpc23xx_eth_driver.c
3  * @brief LPC2300 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "lpc23xx.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit descriptors
53 #pragma data_alignment = 4
55 //Transmit status array
56 #pragma data_alignment = 4
58 //Receive descriptors
59 #pragma data_alignment = 4
61 //Receive status array
62 #pragma data_alignment = 8
64 
65 //Keil MDK-ARM or GCC compiler?
66 #else
67 
68 //Transmit buffer
70  __attribute__((aligned(4)));
71 //Receive buffer
73  __attribute__((aligned(4)));
74 //Transmit descriptors
76  __attribute__((aligned(4)));
77 //Transmit status array
79  __attribute__((aligned(4)));
80 //Receive descriptors
82  __attribute__((aligned(4)));
83 //Receive status array
85  __attribute__((aligned(8)));
86 
87 #endif
88 
89 
90 /**
91  * @brief LPC23xx Ethernet MAC driver
92  **/
93 
95 {
97  ETH_MTU,
108  TRUE,
109  TRUE,
110  TRUE,
111  FALSE
112 };
113 
114 
115 /**
116  * @brief LPC23xx Ethernet MAC initialization
117  * @param[in] interface Underlying network interface
118  * @return Error code
119  **/
120 
122 {
123  error_t error;
124 
125  //Debug message
126  TRACE_INFO("Initializing LPC23xx Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Power up EMAC controller
132  PCONP |= PCONP_PCENET;
133 
134  //GPIO configuration
135  lpc23xxEthInitGpio(interface);
136 
137  //Reset host registers, transmit datapath and receive datapath
139 
140  //Reset EMAC controller
143 
144  //Initialize MAC related registers
145  MAC_MAC1 = 0;
147  MAC_IPGR = IPGR_DEFAULT_VALUE;
148  MAC_CLRT = CLRT_DEFAULT_VALUE;
149 
150  //Select RMII mode
151  MAC_COMMAND = COMMAND_RMII;
152 
153  //Configure MDC clock
154  MAC_MCFG = MCFG_CLOCK_SELECT_DIV28;
155  //Reset MII management interface
156  MAC_MCFG |= MCFG_RESET_MII_MGMT;
157  MAC_MCFG &= ~MCFG_RESET_MII_MGMT;
158 
159  //PHY transceiver initialization
160  error = interface->phyDriver->init(interface);
161  //Failed to initialize PHY transceiver?
162  if(error)
163  return error;
164 
165  //Initialize TX and RX descriptor arrays
166  lpc23xxEthInitDesc(interface);
167 
168  //Set the MAC address of the station
169  MAC_SA0 = interface->macAddr.w[2];
170  MAC_SA1 = interface->macAddr.w[1];
171  MAC_SA2 = interface->macAddr.w[0];
172 
173  //Initialize hash table
174  MAC_HASHFILTERL = 0;
175  MAC_HASHFILTERH = 0;
176 
177  //Configure the receive filter
178  MAC_RXFILTERCTRL = RFC_ACCEPT_PERFECT_EN |
180 
181  //Program the MAXF register with the maximum frame length to be accepted
182  MAC_MAXF = LPC23XX_ETH_RX_BUFFER_SIZE;
183 
184  //Reset EMAC interrupt flags
185  MAC_INTCLEAR = 0xFFFF;
186  //Enable desired EMAC interrupts
187  MAC_INTENABLE = INT_TX_DONE | INT_RX_DONE;
188 
189  //The interrupt request is assigned to the IRQ category
190  VICIntSelect &= ~VIC_INT_ETHERNET;
191  //Register interrupt handler
192  VICVectAddr21 = (uint32_t) lpc23xxEthIrqHandler;
193  //Configure interrupt priority
194  VICVectPriority21 = LPC23XX_ETH_IRQ_PRIORITY;
195 
196  //Enable transmission and reception
197  MAC_COMMAND |= COMMAND_TX_ENABLE | COMMAND_RX_ENABLE;
198  //Allow frames to be received
199  MAC_MAC1 |= MAC1_RECEIVE_ENABLE;
200 
201  //Accept any packets from the upper layer
202  osSetEvent(&interface->nicTxEvent);
203 
204  //Successful initialization
205  return NO_ERROR;
206 }
207 
208 
209 //LPC2378-STK evaluation board?
210 #if defined(USE_LPC2378_STK)
211 
212 /**
213  * @brief GPIO configuration
214  * @param[in] interface Underlying network interface
215  **/
216 
217 void lpc23xxEthInitGpio(NetInterface *interface)
218 {
219  //Configure P1.0 (ENET_TXD0), P1.1 (ENET_TXD1), P1.4 (ENET_TX_EN), P1.8 (ENET_CRS),
220  //P1.9 (ENET_RXD0), P1.10 (ENET_RXD1), P1.14 (RX_ER) and P1.15 (ENET_REF_CLK)
221  PINSEL2 &= ~(PINSEL2_P1_0_MASK | PINSEL2_P1_1_MASK |
222  PINSEL2_P1_4_MASK | PINSEL2_P1_8_MASK | PINSEL2_P1_9_MASK |
223  PINSEL2_P1_10_MASK | PINSEL2_P1_14_MASK | PINSEL2_P1_15_MASK);
224 
225  PINSEL2 |= PINSEL2_P1_0_ENET_TXD0 | PINSEL2_P1_1_ENET_TXD1 |
226  PINSEL2_P1_4_ENET_TX_EN | PINSEL2_P1_8_ENET_CRS | PINSEL2_P1_9_ENET_RXD0 |
227  PINSEL2_P1_10_ENET_RXD1 | PINSEL2_P1_14_ENET_RX_ER | PINSEL2_P1_15_ENET_REF_CLK;
228 
229  //Configure P1.16 (ENET_MDC) and P1.17 (ENET_MDIO)
230  PINSEL3 &= ~(PINSEL3_P1_16_MASK | PINSEL3_P1_17_MASK);
231  PINSEL3 |= PINSEL3_P1_16_ENET_MDC | PINSEL3_P1_17_ENET_MDIO;
232 }
233 
234 #endif
235 
236 
237 /**
238  * @brief Initialize TX and RX descriptors
239  * @param[in] interface Underlying network interface
240  **/
241 
243 {
244  uint_t i;
245 
246  //Initialize TX descriptors
247  for(i = 0; i < LPC23XX_ETH_TX_BUFFER_COUNT; i++)
248  {
249  //Base address of the buffer containing transmit data
250  txDesc[i].packet = (uint32_t) txBuffer[i];
251  //Transmit descriptor control word
252  txDesc[i].control = 0;
253  //Transmit status information word
254  txStatus[i].info = 0;
255  }
256 
257  //Initialize RX descriptors
258  for(i = 0; i < LPC23XX_ETH_RX_BUFFER_COUNT; i++)
259  {
260  //Base address of the buffer for storing receive data
261  rxDesc[i].packet = (uint32_t) rxBuffer[i];
262  //Receive descriptor control word
264  //Receive status information word
265  rxStatus[i].info = 0;
266  //Receive status HashCRC word
267  rxStatus[i].hashCrc = 0;
268  }
269 
270  //Initialize EMAC transmit descriptor registers
271  MAC_TXDESCRIPTOR = (uint32_t) txDesc;
272  MAC_TXSTATUS = (uint32_t) txStatus;
273  MAC_TXDESCRIPTORNUM = LPC23XX_ETH_TX_BUFFER_COUNT - 1;
274  MAC_TXPRODUCEINDEX = 0;
275 
276  //Initialize EMAC receive descriptor registers
277  MAC_RXDESCRIPTOR = (uint32_t) rxDesc;
278  MAC_RXSTATUS = (uint32_t) rxStatus;
279  MAC_RXDESCRIPTORNUM = LPC23XX_ETH_RX_BUFFER_COUNT - 1;
280  MAC_RXCONSUMEINDEX = 0;
281 }
282 
283 
284 /**
285  * @brief LPC23xx Ethernet MAC timer handler
286  *
287  * This routine is periodically called by the TCP/IP stack to
288  * handle periodic operations such as polling the link state
289  *
290  * @param[in] interface Underlying network interface
291  **/
292 
293 void lpc23xxEthTick(NetInterface *interface)
294 {
295  //Handle periodic operations
296  interface->phyDriver->tick(interface);
297 }
298 
299 
300 /**
301  * @brief Enable interrupts
302  * @param[in] interface Underlying network interface
303  **/
304 
306 {
307  //Enable Ethernet MAC interrupts
308  VICIntEnable = VIC_INT_ETHERNET;
309  //Enable Ethernet PHY interrupts
310  interface->phyDriver->enableIrq(interface);
311 }
312 
313 
314 /**
315  * @brief Disable interrupts
316  * @param[in] interface Underlying network interface
317  **/
318 
320 {
321  //Disable Ethernet MAC interrupts
322  VICIntEnClr = VIC_INT_ETHERNET;
323  //Disable Ethernet PHY interrupts
324  interface->phyDriver->disableIrq(interface);
325 }
326 
327 
328 /**
329  * @brief LPC23xx Ethernet MAC interrupt service routine
330  **/
331 
332 __irq void lpc23xxEthIrqHandler(void)
333 {
334  uint_t i;
335  bool_t flag;
336  uint32_t status;
337 
338  //Interrupt service routine prologue
339  osEnterIsr();
340 
341  //This flag will be set if a higher priority task must be woken
342  flag = FALSE;
343 
344  //Read interrupt status register
345  status = MAC_INTSTATUS;
346 
347  //A packet has been transmitted?
348  if(status & INT_TX_DONE)
349  {
350  //Clear TxDone interrupt flag
351  MAC_INTCLEAR = INT_TX_DONE;
352 
353  //Get the index of the next descriptor
354  i = MAC_TXPRODUCEINDEX + 1;
355 
356  //Wrap around if necessary
358  i = 0;
359 
360  //Check whether the TX buffer is available for writing
361  if(i != MAC_TXCONSUMEINDEX)
362  {
363  //Notify the TCP/IP stack that the transmitter is ready to send
364  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
365  }
366  }
367 
368  //A packet has been received?
369  if(status & INT_RX_DONE)
370  {
371  //Disable RxDone interrupts
372  MAC_INTENABLE &= ~INT_RX_DONE;
373 
374  //Set event flag
375  nicDriverInterface->nicEvent = TRUE;
376  //Notify the TCP/IP stack of the event
377  flag |= osSetEventFromIsr(&netEvent);
378  }
379 
380  //Interrupt service routine epilogue
381  osExitIsr(flag);
382 }
383 
384 
385 /**
386  * @brief LPC23xx Ethernet MAC event handler
387  * @param[in] interface Underlying network interface
388  **/
389 
391 {
392  error_t error;
393 
394  //Packet received?
395  if(MAC_INTSTATUS & INT_RX_DONE)
396  {
397  //Clear RxDone interrupt flag
398  MAC_INTCLEAR = INT_RX_DONE;
399 
400  //Process all pending packets
401  do
402  {
403  //Read incoming packet
404  error = lpc23xxEthReceivePacket(interface);
405 
406  //No more data in the receive buffer?
407  } while(error != ERROR_BUFFER_EMPTY);
408  }
409 
410  //Re-enable TxDone and RxDone interrupts
411  MAC_INTENABLE = INT_TX_DONE | INT_RX_DONE;
412 }
413 
414 
415 /**
416  * @brief Send a packet
417  * @param[in] interface Underlying network interface
418  * @param[in] buffer Multi-part buffer containing the data to send
419  * @param[in] offset Offset to the first data byte
420  * @return Error code
421  **/
422 
424  const NetBuffer *buffer, size_t offset)
425 {
426  uint_t i;
427  uint_t j;
428  size_t length;
429 
430  //Retrieve the length of the packet
431  length = netBufferGetLength(buffer) - offset;
432 
433  //Check the frame length
434  if(!length)
435  {
436  //The transmitter can accept another packet
437  osSetEvent(&interface->nicTxEvent);
438  //We are done since the buffer is empty
439  return NO_ERROR;
440  }
442  {
443  //The transmitter can accept another packet
444  osSetEvent(&interface->nicTxEvent);
445  //Report an error
446  return ERROR_INVALID_LENGTH;
447  }
448 
449  //Get the index of the current descriptor
450  i = MAC_TXPRODUCEINDEX;
451  //Get the index of the next descriptor
452  j = i + 1;
453 
454  //Wrap around if necessary
456  j = 0;
457 
458  //Check whether the transmit descriptor array is full
459  if(j == MAC_TXCONSUMEINDEX)
460  return ERROR_FAILURE;
461 
462  //Copy user data to the transmit buffer
463  netBufferRead((uint8_t *) txDesc[i].packet, buffer, offset, length);
464 
465  //Write the transmit control word
466  txDesc[i].control = TX_CTRL_INTERRUPT | TX_CTRL_LAST |
468 
469  //Increment index and wrap around if necessary
470  if(++i >= LPC23XX_ETH_TX_BUFFER_COUNT)
471  i = 0;
472 
473  //Save the resulting value
474  MAC_TXPRODUCEINDEX = i;
475 
476  //Get the index of the next descriptor
477  j = i + 1;
478 
479  //Wrap around if necessary
481  j = 0;
482 
483  //Check whether the next buffer is available for writing
484  if(j != MAC_TXCONSUMEINDEX)
485  {
486  //The transmitter can accept another packet
487  osSetEvent(&interface->nicTxEvent);
488  }
489 
490  //Successful write operation
491  return NO_ERROR;
492 }
493 
494 
495 /**
496  * @brief Receive a packet
497  * @param[in] interface Underlying network interface
498  * @return Error code
499  **/
500 
502 {
503  error_t error;
504  size_t n;
505  uint_t i;
506 
507  //Point to the current descriptor
508  i = MAC_RXCONSUMEINDEX;
509 
510  //Make sure the current buffer is available for reading
511  if(i != MAC_RXPRODUCEINDEX)
512  {
513  //Retrieve the length of the frame
514  n = (rxStatus[i].info & RX_STATUS_SIZE) + 1;
515  //Limit the number of data to read
517 
518  //Pass the packet to the upper layer
519  nicProcessPacket(interface, (uint8_t *) rxDesc[i].packet, n);
520 
521  //Increment index and wrap around if necessary
522  if(++i >= LPC23XX_ETH_RX_BUFFER_COUNT)
523  i = 0;
524 
525  //Save the resulting value
526  MAC_RXCONSUMEINDEX = i;
527 
528  //Valid packet received
529  error = NO_ERROR;
530  }
531  else
532  {
533  //No more data in the receive buffer
534  error = ERROR_BUFFER_EMPTY;
535  }
536 
537  //Return status code
538  return error;
539 }
540 
541 
542 /**
543  * @brief Configure MAC address filtering
544  * @param[in] interface Underlying network interface
545  * @return Error code
546  **/
547 
549 {
550  uint_t i;
551  uint_t k;
552  uint32_t crc;
553  uint32_t hashTable[2];
554  MacFilterEntry *entry;
555 
556  //Debug message
557  TRACE_DEBUG("Updating MAC filter...\r\n");
558 
559  //Set the MAC address of the station
560  MAC_SA0 = interface->macAddr.w[2];
561  MAC_SA1 = interface->macAddr.w[1];
562  MAC_SA2 = interface->macAddr.w[0];
563 
564  //Clear hash table
565  hashTable[0] = 0;
566  hashTable[1] = 0;
567 
568  //The MAC address filter contains the list of MAC addresses to accept
569  //when receiving an Ethernet frame
570  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
571  {
572  //Point to the current entry
573  entry = &interface->macAddrFilter[i];
574 
575  //Valid entry?
576  if(entry->refCount > 0)
577  {
578  //Compute CRC over the current MAC address
579  crc = lpc23xxEthCalcCrc(&entry->addr, sizeof(MacAddr));
580  //Bits [28:23] are used to form the hash
581  k = (crc >> 23) & 0x3F;
582  //Update hash table contents
583  hashTable[k / 32] |= (1 << (k % 32));
584  }
585  }
586 
587  //Write the hash table
588  MAC_HASHFILTERL = hashTable[0];
589  MAC_HASHFILTERH = hashTable[1];
590 
591  //Debug message
592  TRACE_DEBUG(" HashFilterL = %08" PRIX32 "\r\n", MAC_HASHFILTERL);
593  TRACE_DEBUG(" HashFilterH = %08" PRIX32 "\r\n", MAC_HASHFILTERH);
594 
595  //Successful processing
596  return NO_ERROR;
597 }
598 
599 
600 /**
601  * @brief Adjust MAC configuration parameters for proper operation
602  * @param[in] interface Underlying network interface
603  * @return Error code
604  **/
605 
607 {
608  //10BASE-T or 100BASE-TX operation mode?
609  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
610  MAC_SUPP = SUPP_SPEED;
611  else
612  MAC_SUPP = 0;
613 
614  //Half-duplex or full-duplex mode?
615  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
616  {
617  //The MAC operates in full-duplex mode
618  MAC_MAC2 |= MAC2_FULL_DUPLEX;
619  MAC_COMMAND |= COMMAND_FULL_DUPLEX;
620  //Configure Back-to-Back Inter-Packet Gap
621  MAC_IPGT = IPGT_FULL_DUPLEX;
622  }
623  else
624  {
625  //The MAC operates in half-duplex mode
626  MAC_MAC2 &= ~MAC2_FULL_DUPLEX;
627  MAC_COMMAND &= ~COMMAND_FULL_DUPLEX;
628  //Configure Back-to-Back Inter-Packet Gap
629  MAC_IPGT = IPGT_HALF_DUPLEX;
630  }
631 
632  //Successful processing
633  return NO_ERROR;
634 }
635 
636 
637 /**
638  * @brief Write PHY register
639  * @param[in] opcode Access type (2 bits)
640  * @param[in] phyAddr PHY address (5 bits)
641  * @param[in] regAddr Register address (5 bits)
642  * @param[in] data Register value
643  **/
644 
645 void lpc23xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
646  uint8_t regAddr, uint16_t data)
647 {
648  //Valid opcode?
649  if(opcode == SMI_OPCODE_WRITE)
650  {
651  //Clear MCMD register
652  MAC_MCMD = 0;
653 
654  //PHY address
655  MAC_MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
656  //Register address
657  MAC_MADR |= regAddr & MADR_REGISTER_ADDRESS;
658  //Data to be written in the PHY register
659  MAC_MWTD = data & MWTD_WRITE_DATA;
660 
661  //Wait for the write to complete
662  while(MAC_MIND & MIND_BUSY)
663  {
664  }
665  }
666  else
667  {
668  //The MAC peripheral only supports standard Clause 22 opcodes
669  }
670 }
671 
672 
673 /**
674  * @brief Read PHY register
675  * @param[in] opcode Access type (2 bits)
676  * @param[in] phyAddr PHY address (5 bits)
677  * @param[in] regAddr Register address (5 bits)
678  * @return Register value
679  **/
680 
681 uint16_t lpc23xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
682  uint8_t regAddr)
683 {
684  uint16_t data;
685 
686  //Valid opcode?
687  if(opcode == SMI_OPCODE_READ)
688  {
689  //PHY address
690  MAC_MADR = (phyAddr << 8) & MADR_PHY_ADDRESS;
691  //Register address
692  MAC_MADR |= regAddr & MADR_REGISTER_ADDRESS;
693 
694  //Start a read operation
695  MAC_MCMD = MCMD_READ;
696  //Wait for the read to complete
697  while(MAC_MIND & MIND_BUSY)
698  {
699  }
700 
701  //Clear MCMD register
702  MAC_MCMD = 0;
703 
704  //Get register value
705  data = MAC_MRDD & MRDD_READ_DATA;
706  }
707  else
708  {
709  //The MAC peripheral only supports standard Clause 22 opcodes
710  data = 0;
711  }
712 
713  //Return the value of the PHY register
714  return data;
715 }
716 
717 
718 /**
719  * @brief CRC calculation
720  * @param[in] data Pointer to the data over which to calculate the CRC
721  * @param[in] length Number of bytes to process
722  * @return Resulting CRC value
723  **/
724 
725 uint32_t lpc23xxEthCalcCrc(const void *data, size_t length)
726 {
727  uint_t i;
728  uint_t j;
729 
730  //Point to the data over which to calculate the CRC
731  const uint8_t *p = (uint8_t *) data;
732  //CRC preset value
733  uint32_t crc = 0xFFFFFFFF;
734 
735  //Loop through data
736  for(i = 0; i < length; i++)
737  {
738  //The message is processed bit by bit
739  for(j = 0; j < 8; j++)
740  {
741  //Update CRC value
742  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
743  crc = (crc << 1) ^ 0x04C11DB7;
744  else
745  crc = crc << 1;
746  }
747  }
748 
749  //Return CRC value
750  return crc;
751 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define MADR_PHY_ADDRESS
uint8_t length
Definition: dtls_misc.h:149
void lpc23xxEthTick(NetInterface *interface)
LPC23xx Ethernet MAC timer handler.
void lpc23xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
uint8_t opcode
Definition: dns_common.h:172
const NicDriver lpc23xxEthDriver
LPC23xx Ethernet MAC driver.
int bool_t
Definition: compiler_port.h:49
#define TX_CTRL_SIZE
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
uint8_t p
Definition: ndp.h:298
#define LPC23XX_ETH_IRQ_PRIORITY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define IPGR_DEFAULT_VALUE
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
error_t lpc23xxEthReceivePacket(NetInterface *interface)
Receive a packet.
#define COMMAND_TX_ENABLE
void lpc23xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define IPGT_FULL_DUPLEX
#define MAC1_SOFT_RESET
error_t lpc23xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define TX_CTRL_CRC
#define COMMAND_RMII
#define LPC23XX_ETH_TX_BUFFER_COUNT
#define osExitIsr(flag)
#define TX_CTRL_INTERRUPT
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define RX_CTRL_INTERRUPT
#define MAC1_RESET_TX
#define MAC1_RECEIVE_ENABLE
#define SUPP_SPEED
#define MWTD_WRITE_DATA
#define MAC2_FULL_DUPLEX
#define CLRT_DEFAULT_VALUE
#define FALSE
Definition: os_port.h:46
#define MAC1_SIMULATION_RESET
error_t
Error codes.
Definition: error.h:42
#define COMMAND_RX_RESET
#define COMMAND_RX_ENABLE
Transmit descriptor.
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define RFC_ACCEPT_BROADCAST_EN
#define txBuffer
#define NetInterface
Definition: net.h:36
#define INT_TX_DONE
MacAddr addr
MAC address.
Definition: ethernet.h:222
LPC2300 Ethernet MAC controller.
@ ERROR_INVALID_LENGTH
Definition: error.h:109
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
#define LPC23XX_ETH_RX_BUFFER_SIZE
uint16_t lpc23xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
OsEvent netEvent
Definition: net.c:77
#define SMI_OPCODE_READ
Definition: nic.h:63
#define COMMAND_TX_RESET
#define MAC1_RESET_MCS_TX
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MAC2_PAD_CRC_ENABLE
#define COMMAND_FULL_DUPLEX
#define MIN(a, b)
Definition: os_port.h:62
#define TX_CTRL_LAST
#define TX_CTRL_PAD
#define MAC1_RESET_MCS_RX
#define rxBuffer
error_t lpc23xxEthInit(NetInterface *interface)
LPC23xx Ethernet MAC initialization.
#define MIND_BUSY
#define TRACE_DEBUG(...)
Definition: debug.h:106
uint16_t regAddr
#define RX_STATUS_SIZE
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
MAC filter table entry.
Definition: ethernet.h:220
void lpc23xxEthInitGpio(NetInterface *interface)
error_t lpc23xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define LPC23XX_ETH_RX_BUFFER_COUNT
#define MRDD_READ_DATA
#define osEnterIsr()
#define MAC2_CRC_ENABLE
void lpc23xxEthInitDesc(NetInterface *interface)
Initialize TX and RX descriptors.
Receive status.
Transmit status.
#define IPGT_HALF_DUPLEX
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void lpc23xxEthEventHandler(NetInterface *interface)
LPC23xx Ethernet MAC event handler.
#define MCFG_RESET_MII_MGMT
Receive descriptor.
#define MCMD_READ
__irq void lpc23xxEthIrqHandler(void)
LPC23xx Ethernet MAC interrupt service routine.
#define RFC_ACCEPT_MULTICAST_HASH_EN
#define INT_RX_DONE
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
#define LPC23XX_ETH_TX_BUFFER_SIZE
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
uint32_t lpc23xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
#define COMMAND_REG_RESET
#define MCFG_CLOCK_SELECT_DIV28
NIC driver.
Definition: nic.h:179
#define MADR_REGISTER_ADDRESS
#define RFC_ACCEPT_PERFECT_EN
#define MAC1_RESET_RX
error_t lpc23xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
__start_packed struct @108 MacAddr
MAC address.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79
void lpc23xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.