m2sxxx_eth_driver.h
Go to the documentation of this file.
1 /**
2  * @file m2sxxx_eth_driver.h
3  * @brief SmartFusion2 (M2Sxxx) Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 #ifndef _M2SXXX_ETH_DRIVER_H
32 #define _M2SXXX_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef M2SXXX_ETH_TX_BUFFER_COUNT
39  #define M2SXXX_ETH_TX_BUFFER_COUNT 2
40 #elif (M2SXXX_ETH_TX_BUFFER_COUNT < 1)
41  #error M2SXXX_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef M2SXXX_ETH_TX_BUFFER_SIZE
46  #define M2SXXX_ETH_TX_BUFFER_SIZE 1536
47 #elif (M2SXXX_ETH_TX_BUFFER_SIZE != 1536)
48  #error M2SXXX_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef M2SXXX_ETH_RX_BUFFER_COUNT
53  #define M2SXXX_ETH_RX_BUFFER_COUNT 4
54 #elif (M2SXXX_ETH_RX_BUFFER_COUNT < 1)
55  #error M2SXXX_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef M2SXXX_ETH_RX_BUFFER_SIZE
60  #define M2SXXX_ETH_RX_BUFFER_SIZE 1536
61 #elif (M2SXXX_ETH_RX_BUFFER_SIZE != 1536)
62  #error M2SXXX_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef M2SXXX_ETH_IRQ_PRIORITY_GROUPING
67  #define M2SXXX_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (M2SXXX_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error M2SXXX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef M2SXXX_ETH_IRQ_GROUP_PRIORITY
74  #define M2SXXX_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (M2SXXX_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error M2SXXX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef M2SXXX_ETH_IRQ_SUB_PRIORITY
81  #define M2SXXX_ETH_IRQ_SUB_PRIORITY 0
82 #elif (M2SXXX_ETH_IRQ_SUB_PRIORITY < 0)
83  #error M2SXXX_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //EDAC_CR register
87 #define EDAC_CR_CAN_EDAC_EN 0x00000040
88 #define EDAC_CR_USB_EDAC_EN 0x00000020
89 #define EDAC_CR_MAC_EDAC_RX_EN 0x00000010
90 #define EDAC_CR_MAC_EDAC_TX_EN 0x00000008
91 #define EDAC_CR_ESRAM1_EDAC_EN 0x00000002
92 #define EDAC_CR_ESRAM0_EDAC_EN 0x00000001
93 
94 //MAC_CR register
95 #define MAC_CR_RGMII_TXC_DELAY_SEL 0x000001E0
96 #define MAC_CR_ETH_PHY_MODE 0x0000001C
97 #define MAC_CR_ETH_LINE_SPEED 0x00000003
98 
99 #define MAC_CR_ETH_PHY_MODE_RMII 0x00000000
100 #define MAC_CR_ETH_PHY_MODE_TBI 0x00000008
101 #define MAC_CR_ETH_PHY_MODE_MII 0x0000000C
102 #define MAC_CR_ETH_PHY_MODE_GMII 0x00000010
103 
104 #define MAC_CR_ETH_LINE_SPEED_10MBPS 0x00000000
105 #define MAC_CR_ETH_LINE_SPEED_100MBPS 0x00000001
106 #define MAC_CR_ETH_LINE_SPEED_1000MBPS 0x00000002
107 
108 //DMA_TX_CTRL register
109 #define DMA_TX_CTRL_TX_EN 0x00000001
110 
111 //DMA_TX_STATUS register
112 #define DMA_TX_STATUS_TX_PKT_COUNT 0x00FF0000
113 #define DMA_TX_STATUS_TX_BUS_ERROR 0x00000008
114 #define DMA_TX_STATUS_TX_UNDERRUN 0x00000002
115 #define DMA_TX_STATUS_TX_PKT_SENT 0x00000001
116 
117 //DMA_RX_CTRL register
118 #define DMA_RX_CTRL_RX_EN 0x00000001
119 
120 //DMA_RX_STATUS register
121 #define DMA_RX_STATUS_RX_PKT_COUNT 0x00FF0000
122 #define DMA_RX_STATUS_RX_BUS_ERROR 0x00000008
123 #define DMA_RX_STATUS_RX_OVERFLOW 0x00000004
124 #define DMA_RX_STATUS_RX_PKT_RECEIVED 0x00000001
125 
126 //DMA_IRQ_MASK register
127 #define DMA_IRQ_MASK_RX_BUS_ERROR 0x00000080
128 #define DMA_IRQ_MASK_RX_OVERFLOW 0x00000040
129 #define DMA_IRQ_MASK_RX_PKT_RECEIVED 0x00000010
130 #define DMA_IRQ_MASK_TX_BUS_ERROR 0x00000008
131 #define DMA_IRQ_MASK_TX_UNDERRUN 0x00000002
132 #define DMA_IRQ_MASK_TX_PKT_SENT 0x00000001
133 
134 //DMA_IRQ register
135 #define DMA_IRQ_RX_BUS_ERROR 0x00000080
136 #define DMA_IRQ_RX_OVERFLOW 0x00000040
137 #define DMA_IRQ_RX_PKT_RECEIVED 0x00000010
138 #define DMA_IRQ_TX_BUS_ERROR 0x00000008
139 #define DMA_IRQ_TX_UNDERRUN 0x00000002
140 #define DMA_IRQ_TX_PKT_SENT 0x00000001
141 
142 //CFG1 register
143 #define CFG1_SOFT_RESET 0x80000000
144 #define CFG1_SIMULATION_RESET 0x40000000
145 #define CFG1_RESET_RX_MAC_CTRL 0x00080000
146 #define CFG1_RESET_TX_MAC_CTRL 0x00040000
147 #define CFG1_RESET_RX_FUNCTION 0x00020000
148 #define CFG1_RESET_TX_FUNCTION 0x00010000
149 #define CFG1_LOOP_BACK 0x00000100
150 #define CFG1_RX_FLOW_CTRL_EN 0x00000020
151 #define CFG1_TX_FLOW_CTRL_EN 0x00000010
152 #define CFG1_SYNC_RX_EN 0x00000008
153 #define CFG1_RX_EN 0x00000004
154 #define CFG1_SYNC_TX_EN 0x00000002
155 #define CFG1_TX_EN 0x00000001
156 
157 //CFG2 register
158 #define CFG2_PREAMBLE_LENGTH 0x0000F000
159 #define CFG2_INTERFACE_MODE 0x00000300
160 #define CFG2_HUGE FRAME_EN 0x00000020
161 #define CFG2_LENGTH_FIELD_CHECK 0x00000010
162 #define CFG2_PAD_CRC_EN 0x00000004
163 #define CFG2_CRC_EN 0x00000002
164 #define CFG2_FULL_DUPLEX 0x00000001
165 
166 #define CFG2_PREAMBLE_7 0x00007000
167 
168 #define CFG2_INTERFACE_MODE_NIBBLE 0x00000100
169 #define CFG2_INTERFACE_MODE_BYTE 0x00000200
170 
171 //MII_CONFIG register
172 #define MII_CONFIG_CLKSEL_DIV4 0x00000000
173 #define MII_CONFIG_CLKSEL_DIV6 0x00000002
174 #define MII_CONFIG_CLKSEL_DIV8 0x00000003
175 #define MII_CONFIG_CLKSEL_DIV10 0x00000004
176 #define MII_CONFIG_CLKSEL_DIV14 0x00000005
177 #define MII_CONFIG_CLKSEL_DIV20 0x00000006
178 #define MII_CONFIG_CLKSEL_DIV28 0x00000007
179 
180 //MII_COMMAND register
181 #define MII_COMMAND_SCAN 0x00000002
182 #define MII_COMMAND_READ 0x00000001
183 
184 //MII_ADDRESS register
185 #define MII_ADDRESS_PHY_ADDR 0x00001F00
186 #define MII_ADDRESS_REG_ADDR 0x0000001F
187 
188 #define MII_ADDRESS_PHY_ADDR_POS 8
189 #define MII_ADDRESS_REG_ADDR_POS 0
190 
191 //MII_INDICATORS register
192 #define MII_INDICATORS_NOT_VALID 0x00000004
193 #define MII_INDICATORS_SCANNING 0x00000002
194 #define MII_INDICATORS_BUSY 0x00000001
195 
196 //INTERFACE_CTRL register
197 #define INTERFACE_CTRL_RESET 0x80000000
198 #define INTERFACE_CTRL_TBI_MODE 0x08000000
199 #define INTERFACE_CTRL_GHD_MODE 0x04000000
200 #define INTERFACE_CTRL_LHD_MODE 0x02000000
201 #define INTERFACE_CTRL_PHY_MODE 0x01000000
202 #define INTERFACE_CTRL_RESET_PERMII 0x00800000
203 #define INTERFACE_CTRL_SPEED 0x00010000
204 #define INTERFACE_CTRL_RESET_PE100X 0x00008000
205 #define INTERFACE_CTRL_FORCE_QUIET 0x00000400
206 #define INTERFACE_CTRL_NO_CIPHER 0x00000200
207 #define INTERFACE_CTRL_DISABLE_LINK_FAIL 0x00000100
208 #define INTERFACE_CTRL_EN_JABBER_PROTECT 0x00000001
209 
210 //FIFO_CFG0 register
211 #define FIFO_CFG0_STFENRPLY 0x00080000
212 #define FIFO_CFG0_FRFENRPLY 0x00040000
213 #define FIFO_CFG0_SRFENRPLY 0x00020000
214 #define FIFO_CFG0_WTMENRPLY 0x00010000
215 #define FIFO_CFG0_FTFENREQ 0x00001000
216 #define FIFO_CFG0_STFENREQ 0x00000800
217 #define FIFO_CFG0_FRFENREQ 0x00000400
218 #define FIFO_CFG0_SRFENREQ 0x00000200
219 #define FIFO_CFG0_WTMENREQ 0x00000100
220 #define FIFO_CFG0_HSTRSTFT 0x00000010
221 #define FIFO_CFG0_HSTRSTST 0x00000008
222 #define FIFO_CFG0_HSTRSTFR 0x00000004
223 #define FIFO_CFG0_HSTRSTSR 0x00000002
224 #define FIFO_CFG0_HSTRSTWT 0x00000001
225 
226 //FIFO_CFG1 register
227 #define FIFO_CFG1_CFGSRTH 0x0FFF0000
228 #define FIFO_CFG1_CFGXOFFRTX 0x0000FFFF
229 
230 #define FIFO_CFG1_DEFAULT_VALUE 0x0FFF0000
231 
232 //FIFO_CFG2 register
233 #define FIFO_CFG2_CFGHWM 0x1FFF0000
234 #define FIFO_CFG2_CFGLWM 0x00001FFF
235 
236 #define FIFO_CFG2_DEFAULT_VALUE 0x04000180
237 
238 //FIFO_CFG3 register
239 #define FIFO_CFG3_CFGHWMFT 0x0FFF0000
240 #define FIFO_CFG3_CFGFTTH 0x00000FFF
241 
242 #define FIFO_CFG3_DEFAULT_VALUE 0x0258FFFF
243 
244 //FIFO_CFG4 register
245 #define FIFO_CFG4_HSTFLTRFRM 0x0003FFFF
246 #define FIFO_CFG4_RECEIVE_LONG_EVENT 0x00020000
247 #define FIFO_CFG4_VLAN 0x00010000
248 #define FIFO_CFG4_CONTROL_NOT_PAUSE 0x00008000
249 #define FIFO_CFG4_CONTROL_PAUSE 0x00004000
250 #define FIFO_CFG4_CONTROL 0x00002000
251 #define FIFO_CFG4_TRUNCATED 0x00001000
252 #define FIFO_CFG4_LONG_EVENT 0x00000800
253 #define FIFO_CFG4_DRIBBLE_NIBBLE 0x00000400
254 #define FIFO_CFG4_BROADCAST 0x00000200
255 #define FIFO_CFG4_MULTICAST 0x00000100
256 #define FIFO_CFG4_RECEPTION_OK 0x00000080
257 #define FIFO_CFG4_TYPE_ERROR 0x00000040
258 #define FIFO_CFG4_LENGTH_ERROR 0x00000020
259 #define FIFO_CFG4_INVALID_CRC 0x00000010
260 #define FIFO_CFG4_RECEIVE_ERROR 0x00000008
261 #define FIFO_CFG4_FALSE_CARRIER 0x00000004
262 #define FIFO_CFG4_RX_DV_EVENT 0x00000002
263 #define FIFO_CFG4_PRIOR_PKT_DROPPED 0x00000001
264 
265 //FIFO_CFG5 register
266 #define FIFO_CFG5_CFGHDPLX 0x00400000
267 #define FIFO_CFG5_SRFULL 0x00200000
268 #define FIFO_CFG5_HSTSRFULLCLR 0x00100000
269 #define FIFO_CFG5_CFGBYTMODE 0x00080000
270 #define FIFO_CFG5_HSTDRPLT64 0x00040000
271 #define FIFO_CFG5_HSTFLTRFRMDC 0x0003FFFF
272 #define FIFO_CFG5_RECEIVE_LONG_EVENT 0x00020000
273 #define FIFO_CFG5_VLAN 0x00010000
274 #define FIFO_CFG5_CONTROL_NOT_PAUSE 0x00008000
275 #define FIFO_CFG5_CONTROL_PAUSE 0x00004000
276 #define FIFO_CFG5_CONTROL 0x00002000
277 #define FIFO_CFG5_TRUNCATED 0x00001000
278 #define FIFO_CFG5_LONG_EVENT 0x00000800
279 #define FIFO_CFG5_DRIBBLE_NIBBLE 0x00000400
280 #define FIFO_CFG5_BROADCAST 0x00000200
281 #define FIFO_CFG5_MULTICAST 0x00000100
282 #define FIFO_CFG5_RECEPTION_OK 0x00000080
283 #define FIFO_CFG5_TYPE_ERROR 0x00000040
284 #define FIFO_CFG5_LENGTH_ERROR 0x00000020
285 #define FIFO_CFG5_INVALID_CRC 0x00000010
286 #define FIFO_CFG5_RECEIVE_ERROR 0x00000008
287 #define FIFO_CFG5_FALSE_CARRIER 0x00000004
288 #define FIFO_CFG5_RX_DV_EVENT 0x00000002
289 #define FIFO_CFG5_PRIOR_PKT_DROPPED 0x00000001
290 
291 //DMA descriptor flags
292 #define DMA_DESC_EMPTY_FLAG 0x80000000
293 #define DMA_DESC_SIZE_MASK 0x00000FFF
294 
295 //C++ guard
296 #ifdef __cplusplus
297 extern "C" {
298 #endif
299 
300 
301 /**
302  * @brief Transmit DMA descriptor
303  **/
304 
305 typedef struct
306 {
307  uint32_t addr;
308  uint32_t size;
309  uint32_t next;
311 
312 
313 /**
314  * @brief Receive DMA descriptor
315  **/
316 
317 typedef struct
318 {
319  uint32_t addr;
320  uint32_t size;
321  uint32_t next;
323 
324 
325 //M2Sxxx Ethernet MAC driver
326 extern const NicDriver m2sxxxEthDriver;
327 
328 //M2Sxxx Ethernet MAC related functions
330 void m2sxxxEthInitGpio(NetInterface *interface);
331 void m2sxxxEthInitDmaDesc(NetInterface *interface);
332 
333 void m2sxxxEthTick(NetInterface *interface);
334 
335 void m2sxxxEthEnableIrq(NetInterface *interface);
336 void m2sxxxEthDisableIrq(NetInterface *interface);
337 void m2sxxxEthEventHandler(NetInterface *interface);
338 
340  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
341 
343 
346 
347 void m2sxxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
348  uint8_t regAddr, uint16_t data);
349 
350 uint16_t m2sxxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
351  uint8_t regAddr);
352 
353 //C++ guard
354 #ifdef __cplusplus
355 }
356 #endif
357 
358 #endif
error_t m2sxxxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint8_t opcode
Definition: dns_common.h:172
uint8_t data[]
Definition: ethernet.h:209
Transmit DMA descriptor.
void m2sxxxEthEnableIrq(NetInterface *interface)
Enable interrupts.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void m2sxxxEthTick(NetInterface *interface)
M2Sxxx Ethernet MAC timer handler.
uint16_t m2sxxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t m2sxxxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t m2sxxxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t
Error codes.
Definition: error.h:42
void m2sxxxEthInitGpio(NetInterface *interface)
void m2sxxxEthDisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver m2sxxxEthDriver
M2Sxxx Ethernet MAC driver.
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
void m2sxxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void m2sxxxEthEventHandler(NetInterface *interface)
M2Sxxx Ethernet MAC event handler.
uint16_t regAddr
error_t m2sxxxEthInit(NetInterface *interface)
M2Sxxx Ethernet MAC initialization.
Network interface controller abstraction layer.
error_t m2sxxxEthReceivePacket(NetInterface *interface)
Receive a packet.
NIC driver.
Definition: nic.h:257
Receive DMA descriptor.
void m2sxxxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.