m2sxxx_eth_driver.h
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1 /**
2  * @file m2sxxx_eth_driver.h
3  * @brief SmartFusion2 (M2Sxxx) Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _M2SXXX_ETH_DRIVER_H
30 #define _M2SXXX_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef M2SXXX_ETH_TX_BUFFER_COUNT
37  #define M2SXXX_ETH_TX_BUFFER_COUNT 2
38 #elif (M2SXXX_ETH_TX_BUFFER_COUNT < 1)
39  #error M2SXXX_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef M2SXXX_ETH_TX_BUFFER_SIZE
44  #define M2SXXX_ETH_TX_BUFFER_SIZE 1536
45 #elif (M2SXXX_ETH_TX_BUFFER_SIZE != 1536)
46  #error M2SXXX_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef M2SXXX_ETH_RX_BUFFER_COUNT
51  #define M2SXXX_ETH_RX_BUFFER_COUNT 4
52 #elif (M2SXXX_ETH_RX_BUFFER_COUNT < 1)
53  #error M2SXXX_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef M2SXXX_ETH_RX_BUFFER_SIZE
58  #define M2SXXX_ETH_RX_BUFFER_SIZE 1536
59 #elif (M2SXXX_ETH_RX_BUFFER_SIZE != 1536)
60  #error M2SXXX_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Interrupt priority grouping
64 #ifndef M2SXXX_ETH_IRQ_PRIORITY_GROUPING
65  #define M2SXXX_ETH_IRQ_PRIORITY_GROUPING 3
66 #elif (M2SXXX_ETH_IRQ_PRIORITY_GROUPING < 0)
67  #error M2SXXX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
68 #endif
69 
70 //Ethernet interrupt group priority
71 #ifndef M2SXXX_ETH_IRQ_GROUP_PRIORITY
72  #define M2SXXX_ETH_IRQ_GROUP_PRIORITY 12
73 #elif (M2SXXX_ETH_IRQ_GROUP_PRIORITY < 0)
74  #error M2SXXX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
75 #endif
76 
77 //Ethernet interrupt subpriority
78 #ifndef M2SXXX_ETH_IRQ_SUB_PRIORITY
79  #define M2SXXX_ETH_IRQ_SUB_PRIORITY 0
80 #elif (M2SXXX_ETH_IRQ_SUB_PRIORITY < 0)
81  #error M2SXXX_ETH_IRQ_SUB_PRIORITY parameter is not valid
82 #endif
83 
84 //EDAC_CR register
85 #define EDAC_CR_CAN_EDAC_EN 0x00000040
86 #define EDAC_CR_USB_EDAC_EN 0x00000020
87 #define EDAC_CR_MAC_EDAC_RX_EN 0x00000010
88 #define EDAC_CR_MAC_EDAC_TX_EN 0x00000008
89 #define EDAC_CR_ESRAM1_EDAC_EN 0x00000002
90 #define EDAC_CR_ESRAM0_EDAC_EN 0x00000001
91 
92 //MAC_CR register
93 #define MAC_CR_RGMII_TXC_DELAY_SEL 0x000001E0
94 #define MAC_CR_ETH_PHY_MODE 0x0000001C
95 #define MAC_CR_ETH_LINE_SPEED 0x00000003
96 
97 #define MAC_CR_ETH_PHY_MODE_RMII 0x00000000
98 #define MAC_CR_ETH_PHY_MODE_TBI 0x00000008
99 #define MAC_CR_ETH_PHY_MODE_MII 0x0000000C
100 #define MAC_CR_ETH_PHY_MODE_GMII 0x00000010
101 
102 #define MAC_CR_ETH_LINE_SPEED_10MBPS 0x00000000
103 #define MAC_CR_ETH_LINE_SPEED_100MBPS 0x00000001
104 #define MAC_CR_ETH_LINE_SPEED_1000MBPS 0x00000002
105 
106 //DMA_TX_CTRL register
107 #define DMA_TX_CTRL_TX_EN 0x00000001
108 
109 //DMA_TX_STATUS register
110 #define DMA_TX_STATUS_TX_PKT_COUNT 0x00FF0000
111 #define DMA_TX_STATUS_TX_BUS_ERROR 0x00000008
112 #define DMA_TX_STATUS_TX_UNDERRUN 0x00000002
113 #define DMA_TX_STATUS_TX_PKT_SENT 0x00000001
114 
115 //DMA_RX_CTRL register
116 #define DMA_RX_CTRL_RX_EN 0x00000001
117 
118 //DMA_RX_STATUS register
119 #define DMA_RX_STATUS_RX_PKT_COUNT 0x00FF0000
120 #define DMA_RX_STATUS_RX_BUS_ERROR 0x00000008
121 #define DMA_RX_STATUS_RX_OVERFLOW 0x00000004
122 #define DMA_RX_STATUS_RX_PKT_RECEIVED 0x00000001
123 
124 //DMA_IRQ_MASK register
125 #define DMA_IRQ_MASK_RX_BUS_ERROR 0x00000080
126 #define DMA_IRQ_MASK_RX_OVERFLOW 0x00000040
127 #define DMA_IRQ_MASK_RX_PKT_RECEIVED 0x00000010
128 #define DMA_IRQ_MASK_TX_BUS_ERROR 0x00000008
129 #define DMA_IRQ_MASK_TX_UNDERRUN 0x00000002
130 #define DMA_IRQ_MASK_TX_PKT_SENT 0x00000001
131 
132 //DMA_IRQ register
133 #define DMA_IRQ_RX_BUS_ERROR 0x00000080
134 #define DMA_IRQ_RX_OVERFLOW 0x00000040
135 #define DMA_IRQ_RX_PKT_RECEIVED 0x00000010
136 #define DMA_IRQ_TX_BUS_ERROR 0x00000008
137 #define DMA_IRQ_TX_UNDERRUN 0x00000002
138 #define DMA_IRQ_TX_PKT_SENT 0x00000001
139 
140 //CFG1 register
141 #define CFG1_SOFT_RESET 0x80000000
142 #define CFG1_SIMULATION_RESET 0x40000000
143 #define CFG1_RESET_RX_MAC_CTRL 0x00080000
144 #define CFG1_RESET_TX_MAC_CTRL 0x00040000
145 #define CFG1_RESET_RX_FUNCTION 0x00020000
146 #define CFG1_RESET_TX_FUNCTION 0x00010000
147 #define CFG1_LOOP_BACK 0x00000100
148 #define CFG1_RX_FLOW_CTRL_EN 0x00000020
149 #define CFG1_TX_FLOW_CTRL_EN 0x00000010
150 #define CFG1_SYNC_RX_EN 0x00000008
151 #define CFG1_RX_EN 0x00000004
152 #define CFG1_SYNC_TX_EN 0x00000002
153 #define CFG1_TX_EN 0x00000001
154 
155 //CFG2 register
156 #define CFG2_PREAMBLE_LENGTH 0x0000F000
157 #define CFG2_INTERFACE_MODE 0x00000300
158 #define CFG2_HUGE FRAME_EN 0x00000020
159 #define CFG2_LENGTH_FIELD_CHECK 0x00000010
160 #define CFG2_PAD_CRC_EN 0x00000004
161 #define CFG2_CRC_EN 0x00000002
162 #define CFG2_FULL_DUPLEX 0x00000001
163 
164 #define CFG2_PREAMBLE_7 0x00007000
165 
166 #define CFG2_INTERFACE_MODE_NIBBLE 0x00000100
167 #define CFG2_INTERFACE_MODE_BYTE 0x00000200
168 
169 //MII_CONFIG register
170 #define MII_CONFIG_CLKSEL_DIV4 0x00000000
171 #define MII_CONFIG_CLKSEL_DIV6 0x00000002
172 #define MII_CONFIG_CLKSEL_DIV8 0x00000003
173 #define MII_CONFIG_CLKSEL_DIV10 0x00000004
174 #define MII_CONFIG_CLKSEL_DIV14 0x00000005
175 #define MII_CONFIG_CLKSEL_DIV20 0x00000006
176 #define MII_CONFIG_CLKSEL_DIV28 0x00000007
177 
178 //MII_COMMAND register
179 #define MII_COMMAND_SCAN 0x00000002
180 #define MII_COMMAND_READ 0x00000001
181 
182 //MII_ADDRESS register
183 #define MII_ADDRESS_PHY_ADDR 0x00001F00
184 #define MII_ADDRESS_REG_ADDR 0x0000001F
185 
186 #define MII_ADDRESS_PHY_ADDR_POS 8
187 #define MII_ADDRESS_REG_ADDR_POS 0
188 
189 //MII_INDICATORS register
190 #define MII_INDICATORS_NOT_VALID 0x00000004
191 #define MII_INDICATORS_SCANNING 0x00000002
192 #define MII_INDICATORS_BUSY 0x00000001
193 
194 //INTERFACE_CTRL register
195 #define INTERFACE_CTRL_RESET 0x80000000
196 #define INTERFACE_CTRL_TBI_MODE 0x08000000
197 #define INTERFACE_CTRL_GHD_MODE 0x04000000
198 #define INTERFACE_CTRL_LHD_MODE 0x02000000
199 #define INTERFACE_CTRL_PHY_MODE 0x01000000
200 #define INTERFACE_CTRL_RESET_PERMII 0x00800000
201 #define INTERFACE_CTRL_SPEED 0x00010000
202 #define INTERFACE_CTRL_RESET_PE100X 0x00008000
203 #define INTERFACE_CTRL_FORCE_QUIET 0x00000400
204 #define INTERFACE_CTRL_NO_CIPHER 0x00000200
205 #define INTERFACE_CTRL_DISABLE_LINK_FAIL 0x00000100
206 #define INTERFACE_CTRL_EN_JABBER_PROTECT 0x00000001
207 
208 //FIFO_CFG0 register
209 #define FIFO_CFG0_STFENRPLY 0x00080000
210 #define FIFO_CFG0_FRFENRPLY 0x00040000
211 #define FIFO_CFG0_SRFENRPLY 0x00020000
212 #define FIFO_CFG0_WTMENRPLY 0x00010000
213 #define FIFO_CFG0_FTFENREQ 0x00001000
214 #define FIFO_CFG0_STFENREQ 0x00000800
215 #define FIFO_CFG0_FRFENREQ 0x00000400
216 #define FIFO_CFG0_SRFENREQ 0x00000200
217 #define FIFO_CFG0_WTMENREQ 0x00000100
218 #define FIFO_CFG0_HSTRSTFT 0x00000010
219 #define FIFO_CFG0_HSTRSTST 0x00000008
220 #define FIFO_CFG0_HSTRSTFR 0x00000004
221 #define FIFO_CFG0_HSTRSTSR 0x00000002
222 #define FIFO_CFG0_HSTRSTWT 0x00000001
223 
224 //FIFO_CFG1 register
225 #define FIFO_CFG1_CFGSRTH 0x0FFF0000
226 #define FIFO_CFG1_CFGXOFFRTX 0x0000FFFF
227 
228 #define FIFO_CFG1_DEFAULT_VALUE 0x0FFF0000
229 
230 //FIFO_CFG2 register
231 #define FIFO_CFG2_CFGHWM 0x1FFF0000
232 #define FIFO_CFG2_CFGLWM 0x00001FFF
233 
234 #define FIFO_CFG2_DEFAULT_VALUE 0x04000180
235 
236 //FIFO_CFG3 register
237 #define FIFO_CFG3_CFGHWMFT 0x0FFF0000
238 #define FIFO_CFG3_CFGFTTH 0x00000FFF
239 
240 #define FIFO_CFG3_DEFAULT_VALUE 0x0258FFFF
241 
242 //FIFO_CFG4 register
243 #define FIFO_CFG4_HSTFLTRFRM 0x0003FFFF
244 #define FIFO_CFG4_RECEIVE_LONG_EVENT 0x00020000
245 #define FIFO_CFG4_VLAN 0x00010000
246 #define FIFO_CFG4_CONTROL_NOT_PAUSE 0x00008000
247 #define FIFO_CFG4_CONTROL_PAUSE 0x00004000
248 #define FIFO_CFG4_CONTROL 0x00002000
249 #define FIFO_CFG4_TRUNCATED 0x00001000
250 #define FIFO_CFG4_LONG_EVENT 0x00000800
251 #define FIFO_CFG4_DRIBBLE_NIBBLE 0x00000400
252 #define FIFO_CFG4_BROADCAST 0x00000200
253 #define FIFO_CFG4_MULTICAST 0x00000100
254 #define FIFO_CFG4_RECEPTION_OK 0x00000080
255 #define FIFO_CFG4_TYPE_ERROR 0x00000040
256 #define FIFO_CFG4_LENGTH_ERROR 0x00000020
257 #define FIFO_CFG4_INVALID_CRC 0x00000010
258 #define FIFO_CFG4_RECEIVE_ERROR 0x00000008
259 #define FIFO_CFG4_FALSE_CARRIER 0x00000004
260 #define FIFO_CFG4_RX_DV_EVENT 0x00000002
261 #define FIFO_CFG4_PRIOR_PKT_DROPPED 0x00000001
262 
263 //FIFO_CFG5 register
264 #define FIFO_CFG5_CFGHDPLX 0x00400000
265 #define FIFO_CFG5_SRFULL 0x00200000
266 #define FIFO_CFG5_HSTSRFULLCLR 0x00100000
267 #define FIFO_CFG5_CFGBYTMODE 0x00080000
268 #define FIFO_CFG5_HSTDRPLT64 0x00040000
269 #define FIFO_CFG5_HSTFLTRFRMDC 0x0003FFFF
270 #define FIFO_CFG5_RECEIVE_LONG_EVENT 0x00020000
271 #define FIFO_CFG5_VLAN 0x00010000
272 #define FIFO_CFG5_CONTROL_NOT_PAUSE 0x00008000
273 #define FIFO_CFG5_CONTROL_PAUSE 0x00004000
274 #define FIFO_CFG5_CONTROL 0x00002000
275 #define FIFO_CFG5_TRUNCATED 0x00001000
276 #define FIFO_CFG5_LONG_EVENT 0x00000800
277 #define FIFO_CFG5_DRIBBLE_NIBBLE 0x00000400
278 #define FIFO_CFG5_BROADCAST 0x00000200
279 #define FIFO_CFG5_MULTICAST 0x00000100
280 #define FIFO_CFG5_RECEPTION_OK 0x00000080
281 #define FIFO_CFG5_TYPE_ERROR 0x00000040
282 #define FIFO_CFG5_LENGTH_ERROR 0x00000020
283 #define FIFO_CFG5_INVALID_CRC 0x00000010
284 #define FIFO_CFG5_RECEIVE_ERROR 0x00000008
285 #define FIFO_CFG5_FALSE_CARRIER 0x00000004
286 #define FIFO_CFG5_RX_DV_EVENT 0x00000002
287 #define FIFO_CFG5_PRIOR_PKT_DROPPED 0x00000001
288 
289 //DMA descriptor flags
290 #define DMA_DESC_EMPTY_FLAG 0x80000000
291 #define DMA_DESC_SIZE_MASK 0x00000FFF
292 
293 //C++ guard
294 #ifdef __cplusplus
295  extern "C" {
296 #endif
297 
298 
299 /**
300  * @brief Transmit DMA descriptor
301  **/
302 
303 typedef struct
304 {
305  uint32_t addr;
306  uint32_t size;
307  uint32_t next;
309 
310 
311 /**
312  * @brief Receive DMA descriptor
313  **/
314 
315 typedef struct
316 {
317  uint32_t addr;
318  uint32_t size;
319  uint32_t next;
321 
322 
323 //M2Sxxx Ethernet MAC driver
324 extern const NicDriver m2sxxxEthDriver;
325 
326 //M2Sxxx Ethernet MAC related functions
328 void m2sxxxEthInitGpio(NetInterface *interface);
329 void m2sxxxEthInitDmaDesc(NetInterface *interface);
330 
331 void m2sxxxEthTick(NetInterface *interface);
332 
333 void m2sxxxEthEnableIrq(NetInterface *interface);
334 void m2sxxxEthDisableIrq(NetInterface *interface);
335 void m2sxxxEthEventHandler(NetInterface *interface);
336 
338  const NetBuffer *buffer, size_t offset);
339 
341 
344 
345 void m2sxxxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
346 uint16_t m2sxxxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
347 
348 //C++ guard
349 #ifdef __cplusplus
350  }
351 #endif
352 
353 #endif
void m2sxxxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t m2sxxxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void m2sxxxEthEnableIrq(NetInterface *interface)
Enable interrupts.
void m2sxxxEthTick(NetInterface *interface)
M2Sxxx Ethernet MAC timer handler.
uint16_t m2sxxxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t m2sxxxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void m2sxxxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void m2sxxxEthDisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver m2sxxxEthDriver
M2Sxxx Ethernet MAC driver.
void m2sxxxEthInitGpio(NetInterface *interface)
Receive DMA descriptor.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
uint16_t regAddr
error_t m2sxxxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
Transmit DMA descriptor.
error_t m2sxxxEthInit(NetInterface *interface)
M2Sxxx Ethernet MAC initialization.
error_t
Error codes.
Definition: error.h:40
void m2sxxxEthEventHandler(NetInterface *interface)
M2Sxxx Ethernet MAC event handler.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
error_t m2sxxxEthReceivePacket(NetInterface *interface)
Receive a packet.
Network interface controller abstraction layer.