m2sxxx_eth_driver.c
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1 /**
2  * @file m2sxxx_eth_driver.c
3  * @brief SmartFusion2 (M2Sxxx) Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "m2sxxx.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit DMA descriptors
53 #pragma data_alignment = 4
55 //Receive DMA descriptors
56 #pragma data_alignment = 4
58 
59 //Keil MDK-ARM or GCC compiler?
60 #else
61 
62 //Transmit buffer
64  __attribute__((aligned(4)));
65 //Receive buffer
67  __attribute__((aligned(4)));
68 //Transmit DMA descriptors
70  __attribute__((aligned(4)));
71 //Receive DMA descriptors
73  __attribute__((aligned(4)));
74 
75 #endif
76 
77 //Pointer to the current TX DMA descriptor
78 static M2sxxxTxDmaDesc *txCurDmaDesc;
79 //Pointer to the current RX DMA descriptor
80 static M2sxxxRxDmaDesc *rxCurDmaDesc;
81 
82 
83 /**
84  * @brief M2Sxxx Ethernet MAC driver
85  **/
86 
88 {
90  ETH_MTU,
101  TRUE,
102  TRUE,
103  TRUE,
104  FALSE
105 };
106 
107 
108 /**
109  * @brief M2Sxxx Ethernet MAC initialization
110  * @param[in] interface Underlying network interface
111  * @return Error code
112  **/
113 
115 {
116  error_t error;
117 
118  //Debug message
119  TRACE_INFO("Initializing M2Sxxx Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Disable EDAC feature
125  SYSREG->EDAC_CR &= ~(EDAC_CR_MAC_EDAC_RX_EN | EDAC_CR_MAC_EDAC_TX_EN);
126 
127  //Reset the MAC module
130 
131  //Reset the interface module
132  MAC->INTERFACE_CTRL = INTERFACE_CTRL_RESET;
133 
134  //Reset FIFOs
135  MAC->FIFO_CFG0 = FIFO_CFG0_HSTRSTFT | FIFO_CFG0_HSTRSTST |
137 
138  //Take the MAC module out of reset
139  MAC->CFG1 = 0;
140  //Take the interface module out of reset
141  MAC->INTERFACE_CTRL = 0;
142  //Take the FIFOs out of reset
143  MAC->FIFO_CFG0 = 0;
144 
145  //Select interface mode (MII, RMII, GMII or TBI)
146  m2sxxxEthInitGpio(interface);
147 
148  //Select the proper divider for the MDC clock
149  MAC->MII_CONFIG = MII_CONFIG_CLKSEL_DIV28;
150 
151  //PHY transceiver initialization
152  error = interface->phyDriver->init(interface);
153  //Failed to initialize PHY transceiver?
154  if(error)
155  return error;
156 
157  //Set the upper 16 bits of the MAC address
158  MAC->STATION_ADDRESS2 = (interface->macAddr.b[0] << 16) |
159  (interface->macAddr.b[1] << 24);
160 
161  //Set the lower 32 bits of the MAC address
162  MAC->STATION_ADDRESS1 = interface->macAddr.b[2] |
163  (interface->macAddr.b[3] << 8) |
164  (interface->macAddr.b[4] << 16) |
165  (interface->macAddr.b[5] << 24);
166 
167  //Maximum frame length to be accepted
168  MAC->MAX_FRAME_LENGTH = M2SXXX_ETH_RX_BUFFER_SIZE;
169 
170  //Disable flow control
171  MAC->CFG1 = 0;
172 
173  //All short frames will be zero-padded to 60 bytes and a valid CRC
174  //is then appended
177 
178  //Enable TX and RX FIFOs
179  MAC->FIFO_CFG0 = FIFO_CFG0_FTFENREQ | FIFO_CFG0_STFENREQ |
181 
182  //Use default FIFO configuration
183  MAC->FIFO_CFG1 = FIFO_CFG1_DEFAULT_VALUE;
184  MAC->FIFO_CFG2 = FIFO_CFG2_DEFAULT_VALUE;
185  MAC->FIFO_CFG3 = FIFO_CFG3_DEFAULT_VALUE;
186 
187  //Drop frames less than 64 bytes
188  MAC->FIFO_CFG5 = FIFO_CFG5_HSTDRPLT64 | FIFO_CFG5_HSTFLTRFRMDC;
189 
190  //Specify the statistics vectors that will be checked
191  MAC->FIFO_CFG5 &= ~(FIFO_CFG5_TRUNCATED | FIFO_CFG5_RECEPTION_OK |
193 
194  //Configure frame filtering
195  MAC->FIFO_CFG4 = FIFO_CFG4_TRUNCATED | FIFO_CFG4_INVALID_CRC |
197 
198  //Initialize DMA descriptor lists
199  m2sxxxEthInitDmaDesc(interface);
200 
201  //Enable the desired Ethernet interrupts
203 
204  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
205  NVIC_SetPriorityGrouping(M2SXXX_ETH_IRQ_PRIORITY_GROUPING);
206 
207  //Configure Ethernet interrupt priority
208  NVIC_SetPriority(EthernetMAC_IRQn, NVIC_EncodePriority(M2SXXX_ETH_IRQ_PRIORITY_GROUPING,
210 
211  //Enable transmission and reception
212  MAC->CFG1 |= CFG1_TX_EN | CFG1_RX_EN;
213  //Enable the DMA transfer of received packets
214  MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
215 
216  //Accept any packets from the upper layer
217  osSetEvent(&interface->nicTxEvent);
218 
219  //Successful initialization
220  return NO_ERROR;
221 }
222 
223 
224 //SF2-STARTER-KIT-ES-2 evaluation board?
225 #if defined(USE_SF2_STARTER_KIT_ES_2)
226 
227 /**
228  * @brief GPIO configuration
229  * @param[in] interface Underlying network interface
230  **/
231 
232 void m2sxxxEthInitGpio(NetInterface *interface)
233 {
234  //Select MII interface mode
235  SYSREG->MAC_CR = MAC_CR_ETH_PHY_MODE_MII;
236 }
237 
238 #endif
239 
240 
241 /**
242  * @brief Initialize DMA descriptor lists
243  * @param[in] interface Underlying network interface
244  **/
245 
247 {
248  uint_t i;
249 
250  //Initialize TX DMA descriptor list
251  for(i = 0; i < M2SXXX_ETH_TX_BUFFER_COUNT; i++)
252  {
253  //Transmit buffer address
254  txDmaDesc[i].addr = (uint32_t) txBuffer[i];
255  //The descriptor is initially owned by the user
256  txDmaDesc[i].size = DMA_DESC_EMPTY_FLAG;
257  //Next descriptor address
258  txDmaDesc[i].next = (uint32_t) &txDmaDesc[i + 1];
259  }
260 
261  //The last descriptor is chained to the first entry
262  txDmaDesc[i - 1].next = (uint32_t) &txDmaDesc[0];
263  //Point to the very first descriptor
264  txCurDmaDesc = &txDmaDesc[0];
265 
266  //Initialize RX DMA descriptor list
267  for(i = 0; i < M2SXXX_ETH_RX_BUFFER_COUNT; i++)
268  {
269  //Receive buffer address
270  rxDmaDesc[i].addr = (uint32_t) rxBuffer[i];
271  //The descriptor is initially owned by the DMA
272  rxDmaDesc[i].size = DMA_DESC_EMPTY_FLAG;
273  //Next descriptor address
274  rxDmaDesc[i].next = (uint32_t) &rxDmaDesc[i + 1];
275  }
276 
277  //The last descriptor is chained to the first entry
278  rxDmaDesc[i - 1].next = (uint32_t) &rxDmaDesc[0];
279  //Point to the very first descriptor
280  rxCurDmaDesc = &rxDmaDesc[0];
281 
282  //Start location of the TX descriptor list
283  MAC->DMA_TX_DESC = (uint32_t) txDmaDesc;
284  //Start location of the RX descriptor list
285  MAC->DMA_RX_DESC = (uint32_t) rxDmaDesc;
286 }
287 
288 
289 /**
290  * @brief M2Sxxx Ethernet MAC timer handler
291  *
292  * This routine is periodically called by the TCP/IP stack to
293  * handle periodic operations such as polling the link state
294  *
295  * @param[in] interface Underlying network interface
296  **/
297 
298 void m2sxxxEthTick(NetInterface *interface)
299 {
300  //Handle periodic operations
301  interface->phyDriver->tick(interface);
302 }
303 
304 
305 /**
306  * @brief Enable interrupts
307  * @param[in] interface Underlying network interface
308  **/
309 
311 {
312  //Enable Ethernet MAC interrupts
313  NVIC_EnableIRQ(EthernetMAC_IRQn);
314  //Enable Ethernet PHY interrupts
315  interface->phyDriver->enableIrq(interface);
316 }
317 
318 
319 /**
320  * @brief Disable interrupts
321  * @param[in] interface Underlying network interface
322  **/
323 
325 {
326  //Disable Ethernet MAC interrupts
327  NVIC_DisableIRQ(EthernetMAC_IRQn);
328  //Disable Ethernet PHY interrupts
329  interface->phyDriver->disableIrq(interface);
330 }
331 
332 
333 /**
334  * @brief M2Sxxx Ethernet MAC interrupt service routine
335  **/
336 
338 {
339  bool_t flag;
340  uint32_t status;
341 
342  //Interrupt service routine prologue
343  osEnterIsr();
344 
345  //This flag will be set if a higher priority task must be woken
346  flag = FALSE;
347 
348  //Read interrupt status register
349  status = MAC->DMA_IRQ;
350 
351  //A packet has been transmitted?
352  if(status & DMA_IRQ_TX_PKT_SENT)
353  {
354  //Clear TX interrupt flag
355  MAC->DMA_TX_STATUS = DMA_TX_STATUS_TX_PKT_SENT;
356 
357  //Check whether the TX buffer is available for writing
358  if(txCurDmaDesc->size & DMA_DESC_EMPTY_FLAG)
359  {
360  //Notify the TCP/IP stack that the transmitter is ready to send
361  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
362  }
363  }
364 
365  //A packet has been received?
366  if(status & DMA_IRQ_RX_PKT_RECEIVED)
367  {
368  //Disable RX interrupt
369  MAC->DMA_IRQ_MASK &= ~DMA_IRQ_MASK_RX_PKT_RECEIVED;
370 
371  //Set event flag
372  nicDriverInterface->nicEvent = TRUE;
373  //Notify the TCP/IP stack of the event
374  flag |= osSetEventFromIsr(&netEvent);
375  }
376 
377  //Interrupt service routine epilogue
378  osExitIsr(flag);
379 }
380 
381 
382 /**
383  * @brief M2Sxxx Ethernet MAC event handler
384  * @param[in] interface Underlying network interface
385  **/
386 
388 {
389  //Packet received?
390  if(MAC->DMA_RX_STATUS & DMA_RX_STATUS_RX_PKT_RECEIVED)
391  {
392  //Process all the pending packets
393  while(MAC->DMA_RX_STATUS & DMA_RX_STATUS_RX_PKT_RECEIVED)
394  {
395  //Clear RX interrupt flag
396  MAC->DMA_RX_STATUS = DMA_RX_STATUS_RX_PKT_RECEIVED;
397  //Read incoming packet
398  m2sxxxEthReceivePacket(interface);
399  }
400  }
401 
402  //Re-enable Ethernet interrupts
404 }
405 
406 
407 /**
408  * @brief Send a packet
409  * @param[in] interface Underlying network interface
410  * @param[in] buffer Multi-part buffer containing the data to send
411  * @param[in] offset Offset to the first data byte
412  * @return Error code
413  **/
414 
416  const NetBuffer *buffer, size_t offset)
417 {
418  size_t length;
419 
420  //Retrieve the length of the packet
421  length = netBufferGetLength(buffer) - offset;
422 
423  //Check the frame length
425  {
426  //The transmitter can accept another packet
427  osSetEvent(&interface->nicTxEvent);
428  //Report an error
429  return ERROR_INVALID_LENGTH;
430  }
431 
432  //Make sure the current buffer is available for writing
433  if(!(txCurDmaDesc->size & DMA_DESC_EMPTY_FLAG))
434  return ERROR_FAILURE;
435 
436  //Copy user data to the transmit buffer
437  netBufferRead((uint8_t *) txCurDmaDesc->addr, buffer, offset, length);
438 
439  //Set the packet length and give the ownership of the descriptor to the DMA
440  txCurDmaDesc->size = length & DMA_DESC_SIZE_MASK;
441 
442  //Check whether DMA transfers are suspended
443  if(!(MAC->DMA_TX_CTRL & DMA_TX_CTRL_TX_EN))
444  {
445  //Set the start position in the ring buffer
446  MAC->DMA_TX_DESC = (uint32_t) txCurDmaDesc;
447  }
448 
449  //Instruct the DMA controller to transfer the packet
450  MAC->DMA_TX_CTRL = DMA_TX_CTRL_TX_EN;
451 
452  //Point to the next descriptor in the list
453  txCurDmaDesc = (M2sxxxTxDmaDesc *) txCurDmaDesc->next;
454 
455  //Check whether the next buffer is available for writing
456  if(txCurDmaDesc->size & DMA_DESC_EMPTY_FLAG)
457  {
458  //The transmitter can accept another packet
459  osSetEvent(&interface->nicTxEvent);
460  }
461 
462  //Data successfully written
463  return NO_ERROR;
464 }
465 
466 
467 /**
468  * @brief Receive a packet
469  * @param[in] interface Underlying network interface
470  * @return Error code
471  **/
472 
474 {
475  error_t error;
476  size_t n;
477 
478  //The current buffer is available for reading?
479  if(!(rxCurDmaDesc->size & DMA_DESC_EMPTY_FLAG))
480  {
481  //Retrieve the length of the frame
482  n = rxCurDmaDesc->size & DMA_DESC_SIZE_MASK;
483  //Limit the number of data to read
485 
486  //Pass the packet to the upper layer
487  nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->addr, n);
488 
489  //Give the ownership of the descriptor back to the DMA
490  rxCurDmaDesc->size = DMA_DESC_EMPTY_FLAG;
491 
492  //Check whether DMA transfers are suspended
493  if(!(MAC->DMA_RX_CTRL & DMA_RX_CTRL_RX_EN))
494  {
495  //Set the start position in the ring buffer
496  MAC->DMA_RX_DESC = (uint32_t) rxCurDmaDesc;
497  }
498 
499  //Enable the DMA transfer of received packets
500  MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
501  //Point to the next descriptor in the list
502  rxCurDmaDesc = (M2sxxxRxDmaDesc *) rxCurDmaDesc->next;
503 
504  //Valid packet received
505  error = NO_ERROR;
506  }
507  else
508  {
509  //Check whether DMA transfers are suspended
510  if(!(MAC->DMA_RX_CTRL & DMA_RX_CTRL_RX_EN))
511  {
512  //Set the start position in the ring buffer
513  MAC->DMA_RX_DESC = (uint32_t) rxCurDmaDesc;
514  }
515 
516  //Enable the DMA transfer of received packets
517  MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
518 
519  //No more data in the receive buffer
520  error = ERROR_BUFFER_EMPTY;
521  }
522 
523  //Return status code
524  return error;
525 }
526 
527 
528 /**
529  * @brief Configure MAC address filtering
530  * @param[in] interface Underlying network interface
531  * @return Error code
532  **/
533 
535 {
536  //Ethernet MAC does not implement multicast filtering
537  return NO_ERROR;
538 }
539 
540 
541 /**
542  * @brief Adjust MAC configuration parameters for proper operation
543  * @param[in] interface Underlying network interface
544  * @return Error code
545  **/
546 
548 {
549  uint32_t temp;
550 
551  //10BASE-T or 100BASE-TX operation mode?
552  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
553  {
554  //The link operates at 100 Mbps
555  temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED;
556  SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_100MBPS;
557 
558  //Configure the RMII module with the current operating speed
559  MAC->INTERFACE_CTRL |= INTERFACE_CTRL_SPEED;
560 
561  //Use nibble mode
562  temp = MAC->CFG2 & ~CFG2_INTERFACE_MODE;
563  MAC->CFG2 = temp | CFG2_INTERFACE_MODE_NIBBLE;
564  }
565  else
566  {
567  //The link operates at 10 Mbps
568  if((SYSREG->MAC_CR & MAC_CR_ETH_PHY_MODE) == MAC_CR_ETH_PHY_MODE_MII)
569  {
570  temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED;
571  SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_100MBPS;
572  }
573  else
574  {
575  temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED;
576  SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_10MBPS;
577  }
578 
579  //Configure the RMII module with the current operating speed
580  MAC->INTERFACE_CTRL &= ~INTERFACE_CTRL_SPEED;
581 
582  //Use nibble mode
583  temp = MAC->CFG2 & ~CFG2_INTERFACE_MODE;
584  MAC->CFG2 = temp | CFG2_INTERFACE_MODE_NIBBLE;
585  }
586 
587  //Half-duplex or full-duplex mode?
588  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
589  {
590  //Configure MAC to operate in full-duplex mode
591  MAC->CFG2 |= CFG2_FULL_DUPLEX;
592  MAC->FIFO_CFG5 &= ~FIFO_CFG5_CFGHDPLX;
593  }
594  else
595  {
596  //Configure MAC to operate in half-duplex mode
597  MAC->CFG2 &= ~CFG2_FULL_DUPLEX;
598  MAC->FIFO_CFG5 |= FIFO_CFG5_CFGHDPLX;
599  }
600 
601  //Successful processing
602  return NO_ERROR;
603 }
604 
605 
606 /**
607  * @brief Write PHY register
608  * @param[in] opcode Access type (2 bits)
609  * @param[in] phyAddr PHY address (5 bits)
610  * @param[in] regAddr Register address (5 bits)
611  * @param[in] data Register value
612  **/
613 
614 void m2sxxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
615  uint8_t regAddr, uint16_t data)
616 {
617  //Valid opcode?
618  if(opcode == SMI_OPCODE_WRITE)
619  {
620  //Set PHY address and register address
621  MAC->MII_ADDRESS = (phyAddr << MII_ADDRESS_PHY_ADDR_POS) | regAddr;
622  //Start a write operation
623  MAC->MII_CTRL = data;
624 
625  //Wait for the write to complete
626  while(MAC->MII_INDICATORS & MII_INDICATORS_BUSY)
627  {
628  }
629  }
630  else
631  {
632  //The MAC peripheral only supports standard Clause 22 opcodes
633  }
634 }
635 
636 
637 /**
638  * @brief Read PHY register
639  * @param[in] opcode Access type (2 bits)
640  * @param[in] phyAddr PHY address (5 bits)
641  * @param[in] regAddr Register address (5 bits)
642  * @return Register value
643  **/
644 
645 uint16_t m2sxxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
646  uint8_t regAddr)
647 {
648  uint16_t data;
649 
650  //Valid opcode?
651  if(opcode == SMI_OPCODE_READ)
652  {
653  //Set PHY address and register address
654  MAC->MII_ADDRESS = (phyAddr << MII_ADDRESS_PHY_ADDR_POS) | regAddr;
655  //Start a read operation
656  MAC->MII_COMMAND = MII_COMMAND_READ;
657 
658  //Wait for the read to complete
659  while(MAC->MII_INDICATORS & MII_INDICATORS_BUSY)
660  {
661  }
662 
663  //Clear command register
664  MAC->MII_COMMAND = 0;
665  //Get register value
666  data = MAC->MII_STATUS;
667  }
668  else
669  {
670  //The MAC peripheral only supports standard Clause 22 opcodes
671  data = 0;
672  }
673 
674  //Return the value of the PHY register
675  return data;
676 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define DMA_IRQ_MASK_RX_PKT_RECEIVED
uint8_t length
Definition: dtls_misc.h:149
#define CFG2_PREAMBLE_7
uint8_t opcode
Definition: dns_common.h:172
#define MII_ADDRESS_PHY_ADDR_POS
#define DMA_IRQ_TX_PKT_SENT
int bool_t
Definition: compiler_port.h:49
#define FIFO_CFG5_CFGHDPLX
#define MAC_CR_ETH_LINE_SPEED
#define CFG2_LENGTH_FIELD_CHECK
#define M2SXXX_ETH_IRQ_GROUP_PRIORITY
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
#define MII_CONFIG_CLKSEL_DIV28
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define CFG2_CRC_EN
Transmit DMA descriptor.
#define M2SXXX_ETH_TX_BUFFER_SIZE
#define FIFO_CFG1_DEFAULT_VALUE
#define CFG1_TX_EN
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define TRUE
Definition: os_port.h:50
void EthernetMAC_IRQHandler(void)
M2Sxxx Ethernet MAC interrupt service routine.
#define FIFO_CFG5_TRUNCATED
error_t m2sxxxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define MAC_CR_ETH_LINE_SPEED_100MBPS
#define CFG1_RX_EN
void m2sxxxEthTick(NetInterface *interface)
M2Sxxx Ethernet MAC timer handler.
#define DMA_TX_CTRL_TX_EN
#define M2SXXX_ETH_RX_BUFFER_SIZE
#define MAC_CR_ETH_PHY_MODE
#define INTERFACE_CTRL_RESET
#define DMA_RX_STATUS_RX_PKT_RECEIVED
#define osExitIsr(flag)
SmartFusion2 (M2Sxxx) Ethernet MAC controller.
error_t m2sxxxEthInit(NetInterface *interface)
M2Sxxx Ethernet MAC initialization.
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define FIFO_CFG5_RECEIVE_ERROR
#define M2SXXX_ETH_IRQ_PRIORITY_GROUPING
error_t m2sxxxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define FALSE
Definition: os_port.h:46
#define CFG2_INTERFACE_MODE
#define EDAC_CR_MAC_EDAC_RX_EN
#define FIFO_CFG4_RECEIVE_ERROR
#define CFG2_INTERFACE_MODE_NIBBLE
#define CFG1_RESET_RX_FUNCTION
error_t
Error codes.
Definition: error.h:42
#define FIFO_CFG0_FTFENREQ
void m2sxxxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define CFG1_RESET_RX_MAC_CTRL
#define FIFO_CFG0_HSTRSTWT
void m2sxxxEthInitGpio(NetInterface *interface)
#define FIFO_CFG4_TRUNCATED
error_t m2sxxxEthReceivePacket(NetInterface *interface)
Receive a packet.
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
void m2sxxxEthEventHandler(NetInterface *interface)
M2Sxxx Ethernet MAC event handler.
#define txBuffer
#define DMA_IRQ_MASK_TX_PKT_SENT
#define FIFO_CFG0_HSTRSTST
#define MAC_CR_ETH_PHY_MODE_MII
#define NetInterface
Definition: net.h:36
#define FIFO_CFG2_DEFAULT_VALUE
#define FIFO_CFG5_HSTFLTRFRMDC
#define FIFO_CFG5_HSTDRPLT64
@ ERROR_INVALID_LENGTH
Definition: error.h:109
#define FIFO_CFG5_RECEPTION_OK
#define MII_INDICATORS_BUSY
const NicDriver m2sxxxEthDriver
M2Sxxx Ethernet MAC driver.
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
OsEvent netEvent
Definition: net.c:77
#define FIFO_CFG0_WTMENREQ
#define FIFO_CFG0_HSTRSTSR
#define CFG1_SOFT_RESET
#define SMI_OPCODE_READ
Definition: nic.h:63
#define DMA_RX_CTRL_RX_EN
error_t m2sxxxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define TRACE_INFO(...)
Definition: debug.h:94
#define EDAC_CR_MAC_EDAC_TX_EN
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define DMA_DESC_EMPTY_FLAG
#define MIN(a, b)
Definition: os_port.h:62
#define FIFO_CFG3_DEFAULT_VALUE
#define rxBuffer
#define FIFO_CFG0_FRFENREQ
#define MAC_CR_ETH_LINE_SPEED_10MBPS
#define M2SXXX_ETH_IRQ_SUB_PRIORITY
#define CFG1_RESET_TX_MAC_CTRL
uint16_t regAddr
#define DMA_TX_STATUS_TX_PKT_SENT
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
#define MII_COMMAND_READ
#define osEnterIsr()
#define CFG2_PAD_CRC_EN
#define DMA_IRQ_RX_PKT_RECEIVED
#define FIFO_CFG0_SRFENREQ
#define rxDmaDesc
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define FIFO_CFG0_HSTRSTFR
void m2sxxxEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define CFG1_RESET_TX_FUNCTION
#define txDmaDesc
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
unsigned int uint_t
Definition: compiler_port.h:45
void m2sxxxEthEnableIrq(NetInterface *interface)
Enable interrupts.
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
#define CFG2_FULL_DUPLEX
#define DMA_DESC_SIZE_MASK
Receive DMA descriptor.
#define FIFO_CFG0_STFENREQ
uint16_t m2sxxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define INTERFACE_CTRL_SPEED
#define M2SXXX_ETH_TX_BUFFER_COUNT
void m2sxxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define FIFO_CFG0_HSTRSTFT
#define M2SXXX_ETH_RX_BUFFER_COUNT
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79
#define FIFO_CFG5_INVALID_CRC
#define FIFO_CFG4_INVALID_CRC