m2sxxx_eth_driver.c
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1 /**
2  * @file m2sxxx_eth_driver.c
3  * @brief SmartFusion2 (M2Sxxx) Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "m2sxxx.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 4
49 //Receive buffer
50 #pragma data_alignment = 4
52 //Transmit DMA descriptors
53 #pragma data_alignment = 4
55 //Receive DMA descriptors
56 #pragma data_alignment = 4
58 
59 //Keil MDK-ARM or GCC compiler?
60 #else
61 
62 //Transmit buffer
64  __attribute__((aligned(4)));
65 //Receive buffer
67  __attribute__((aligned(4)));
68 //Transmit DMA descriptors
70  __attribute__((aligned(4)));
71 //Receive DMA descriptors
73  __attribute__((aligned(4)));
74 
75 #endif
76 
77 //Pointer to the current TX DMA descriptor
78 static M2sxxxTxDmaDesc *txCurDmaDesc;
79 //Pointer to the current RX DMA descriptor
80 static M2sxxxRxDmaDesc *rxCurDmaDesc;
81 
82 
83 /**
84  * @brief M2Sxxx Ethernet MAC driver
85  **/
86 
88 {
90  ETH_MTU,
101  TRUE,
102  TRUE,
103  TRUE,
104  FALSE
105 };
106 
107 
108 /**
109  * @brief M2Sxxx Ethernet MAC initialization
110  * @param[in] interface Underlying network interface
111  * @return Error code
112  **/
113 
115 {
116  error_t error;
117 
118  //Debug message
119  TRACE_INFO("Initializing M2Sxxx Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Disable EDAC feature
125  SYSREG->EDAC_CR &= ~(EDAC_CR_MAC_EDAC_RX_EN | EDAC_CR_MAC_EDAC_TX_EN);
126 
127  //Reset the MAC module
130 
131  //Reset the interface module
132  MAC->INTERFACE_CTRL = INTERFACE_CTRL_RESET;
133 
134  //Reset FIFOs
135  MAC->FIFO_CFG0 = FIFO_CFG0_HSTRSTFT | FIFO_CFG0_HSTRSTST |
137 
138  //Take the MAC module out of reset
139  MAC->CFG1 = 0;
140  //Take the interface module out of reset
141  MAC->INTERFACE_CTRL = 0;
142  //Take the FIFOs out of reset
143  MAC->FIFO_CFG0 = 0;
144 
145  //Select interface mode (MII, RMII, GMII or TBI)
146  m2sxxxEthInitGpio(interface);
147 
148  //Select the proper divider for the MDC clock
149  MAC->MII_CONFIG = MII_CONFIG_CLKSEL_DIV28;
150 
151  //Valid Ethernet PHY or switch driver?
152  if(interface->phyDriver != NULL)
153  {
154  //Ethernet PHY initialization
155  error = interface->phyDriver->init(interface);
156  }
157  else if(interface->switchDriver != NULL)
158  {
159  //Ethernet switch initialization
160  error = interface->switchDriver->init(interface);
161  }
162  else
163  {
164  //The interface is not properly configured
165  error = ERROR_FAILURE;
166  }
167 
168  //Any error to report?
169  if(error)
170  {
171  return error;
172  }
173 
174  //Set the upper 16 bits of the MAC address
175  MAC->STATION_ADDRESS2 = (interface->macAddr.b[0] << 16) |
176  (interface->macAddr.b[1] << 24);
177 
178  //Set the lower 32 bits of the MAC address
179  MAC->STATION_ADDRESS1 = interface->macAddr.b[2] |
180  (interface->macAddr.b[3] << 8) |
181  (interface->macAddr.b[4] << 16) |
182  (interface->macAddr.b[5] << 24);
183 
184  //Maximum frame length to be accepted
185  MAC->MAX_FRAME_LENGTH = M2SXXX_ETH_RX_BUFFER_SIZE;
186 
187  //Disable flow control
188  MAC->CFG1 = 0;
189 
190  //All short frames will be zero-padded to 60 bytes and a valid CRC
191  //is then appended
194 
195  //Enable TX and RX FIFOs
196  MAC->FIFO_CFG0 = FIFO_CFG0_FTFENREQ | FIFO_CFG0_STFENREQ |
198 
199  //Use default FIFO configuration
200  MAC->FIFO_CFG1 = FIFO_CFG1_DEFAULT_VALUE;
201  MAC->FIFO_CFG2 = FIFO_CFG2_DEFAULT_VALUE;
202  MAC->FIFO_CFG3 = FIFO_CFG3_DEFAULT_VALUE;
203 
204  //Drop frames less than 64 bytes
205  MAC->FIFO_CFG5 = FIFO_CFG5_HSTDRPLT64 | FIFO_CFG5_HSTFLTRFRMDC;
206 
207  //Specify the statistics vectors that will be checked
208  MAC->FIFO_CFG5 &= ~(FIFO_CFG5_TRUNCATED | FIFO_CFG5_RECEPTION_OK |
210 
211  //Configure frame filtering
212  MAC->FIFO_CFG4 = FIFO_CFG4_TRUNCATED | FIFO_CFG4_INVALID_CRC |
214 
215  //Initialize DMA descriptor lists
216  m2sxxxEthInitDmaDesc(interface);
217 
218  //Enable the desired Ethernet interrupts
220 
221  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
222  NVIC_SetPriorityGrouping(M2SXXX_ETH_IRQ_PRIORITY_GROUPING);
223 
224  //Configure Ethernet interrupt priority
225  NVIC_SetPriority(EthernetMAC_IRQn, NVIC_EncodePriority(M2SXXX_ETH_IRQ_PRIORITY_GROUPING,
227 
228  //Enable transmission and reception
229  MAC->CFG1 |= CFG1_TX_EN | CFG1_RX_EN;
230  //Enable the DMA transfer of received packets
231  MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
232 
233  //Accept any packets from the upper layer
234  osSetEvent(&interface->nicTxEvent);
235 
236  //Successful initialization
237  return NO_ERROR;
238 }
239 
240 
241 //SF2-STARTER-KIT-ES-2 evaluation board?
242 #if defined(USE_SF2_STARTER_KIT_ES_2)
243 
244 /**
245  * @brief GPIO configuration
246  * @param[in] interface Underlying network interface
247  **/
248 
249 void m2sxxxEthInitGpio(NetInterface *interface)
250 {
251  //Select MII interface mode
252  SYSREG->MAC_CR = MAC_CR_ETH_PHY_MODE_MII;
253 }
254 
255 #endif
256 
257 
258 /**
259  * @brief Initialize DMA descriptor lists
260  * @param[in] interface Underlying network interface
261  **/
262 
264 {
265  uint_t i;
266 
267  //Initialize TX DMA descriptor list
268  for(i = 0; i < M2SXXX_ETH_TX_BUFFER_COUNT; i++)
269  {
270  //Transmit buffer address
271  txDmaDesc[i].addr = (uint32_t) txBuffer[i];
272  //The descriptor is initially owned by the user
273  txDmaDesc[i].size = DMA_DESC_EMPTY_FLAG;
274  //Next descriptor address
275  txDmaDesc[i].next = (uint32_t) &txDmaDesc[i + 1];
276  }
277 
278  //The last descriptor is chained to the first entry
279  txDmaDesc[i - 1].next = (uint32_t) &txDmaDesc[0];
280  //Point to the very first descriptor
281  txCurDmaDesc = &txDmaDesc[0];
282 
283  //Initialize RX DMA descriptor list
284  for(i = 0; i < M2SXXX_ETH_RX_BUFFER_COUNT; i++)
285  {
286  //Receive buffer address
287  rxDmaDesc[i].addr = (uint32_t) rxBuffer[i];
288  //The descriptor is initially owned by the DMA
289  rxDmaDesc[i].size = DMA_DESC_EMPTY_FLAG;
290  //Next descriptor address
291  rxDmaDesc[i].next = (uint32_t) &rxDmaDesc[i + 1];
292  }
293 
294  //The last descriptor is chained to the first entry
295  rxDmaDesc[i - 1].next = (uint32_t) &rxDmaDesc[0];
296  //Point to the very first descriptor
297  rxCurDmaDesc = &rxDmaDesc[0];
298 
299  //Start location of the TX descriptor list
300  MAC->DMA_TX_DESC = (uint32_t) txDmaDesc;
301  //Start location of the RX descriptor list
302  MAC->DMA_RX_DESC = (uint32_t) rxDmaDesc;
303 }
304 
305 
306 /**
307  * @brief M2Sxxx Ethernet MAC timer handler
308  *
309  * This routine is periodically called by the TCP/IP stack to handle periodic
310  * operations such as polling the link state
311  *
312  * @param[in] interface Underlying network interface
313  **/
314 
315 void m2sxxxEthTick(NetInterface *interface)
316 {
317  //Valid Ethernet PHY or switch driver?
318  if(interface->phyDriver != NULL)
319  {
320  //Handle periodic operations
321  interface->phyDriver->tick(interface);
322  }
323  else if(interface->switchDriver != NULL)
324  {
325  //Handle periodic operations
326  interface->switchDriver->tick(interface);
327  }
328  else
329  {
330  //Just for sanity
331  }
332 }
333 
334 
335 /**
336  * @brief Enable interrupts
337  * @param[in] interface Underlying network interface
338  **/
339 
341 {
342  //Enable Ethernet MAC interrupts
343  NVIC_EnableIRQ(EthernetMAC_IRQn);
344 
345  //Valid Ethernet PHY or switch driver?
346  if(interface->phyDriver != NULL)
347  {
348  //Enable Ethernet PHY interrupts
349  interface->phyDriver->enableIrq(interface);
350  }
351  else if(interface->switchDriver != NULL)
352  {
353  //Enable Ethernet switch interrupts
354  interface->switchDriver->enableIrq(interface);
355  }
356  else
357  {
358  //Just for sanity
359  }
360 }
361 
362 
363 /**
364  * @brief Disable interrupts
365  * @param[in] interface Underlying network interface
366  **/
367 
369 {
370  //Disable Ethernet MAC interrupts
371  NVIC_DisableIRQ(EthernetMAC_IRQn);
372 
373  //Valid Ethernet PHY or switch driver?
374  if(interface->phyDriver != NULL)
375  {
376  //Disable Ethernet PHY interrupts
377  interface->phyDriver->disableIrq(interface);
378  }
379  else if(interface->switchDriver != NULL)
380  {
381  //Disable Ethernet switch interrupts
382  interface->switchDriver->disableIrq(interface);
383  }
384  else
385  {
386  //Just for sanity
387  }
388 }
389 
390 
391 /**
392  * @brief M2Sxxx Ethernet MAC interrupt service routine
393  **/
394 
396 {
397  bool_t flag;
398  uint32_t status;
399 
400  //Interrupt service routine prologue
401  osEnterIsr();
402 
403  //This flag will be set if a higher priority task must be woken
404  flag = FALSE;
405 
406  //Read interrupt status register
407  status = MAC->DMA_IRQ;
408 
409  //Packet transmitted?
410  if((status & DMA_IRQ_TX_PKT_SENT) != 0)
411  {
412  //Clear TX interrupt flag
413  MAC->DMA_TX_STATUS = DMA_TX_STATUS_TX_PKT_SENT;
414 
415  //Check whether the TX buffer is available for writing
416  if((txCurDmaDesc->size & DMA_DESC_EMPTY_FLAG) != 0)
417  {
418  //Notify the TCP/IP stack that the transmitter is ready to send
419  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
420  }
421  }
422 
423  //Packet received?
424  if((status & DMA_IRQ_RX_PKT_RECEIVED) != 0)
425  {
426  //Disable RX interrupt
427  MAC->DMA_IRQ_MASK &= ~DMA_IRQ_MASK_RX_PKT_RECEIVED;
428 
429  //Set event flag
430  nicDriverInterface->nicEvent = TRUE;
431  //Notify the TCP/IP stack of the event
432  flag |= osSetEventFromIsr(&netEvent);
433  }
434 
435  //Interrupt service routine epilogue
436  osExitIsr(flag);
437 }
438 
439 
440 /**
441  * @brief M2Sxxx Ethernet MAC event handler
442  * @param[in] interface Underlying network interface
443  **/
444 
446 {
447  //Packet received?
448  if((MAC->DMA_RX_STATUS & DMA_RX_STATUS_RX_PKT_RECEIVED) != 0)
449  {
450  //Process all the pending packets
451  while((MAC->DMA_RX_STATUS & DMA_RX_STATUS_RX_PKT_RECEIVED) != 0)
452  {
453  //Clear RX interrupt flag
454  MAC->DMA_RX_STATUS = DMA_RX_STATUS_RX_PKT_RECEIVED;
455  //Read incoming packet
456  m2sxxxEthReceivePacket(interface);
457  }
458  }
459 
460  //Re-enable Ethernet interrupts
462 }
463 
464 
465 /**
466  * @brief Send a packet
467  * @param[in] interface Underlying network interface
468  * @param[in] buffer Multi-part buffer containing the data to send
469  * @param[in] offset Offset to the first data byte
470  * @param[in] ancillary Additional options passed to the stack along with
471  * the packet
472  * @return Error code
473  **/
474 
476  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
477 {
478  size_t length;
479 
480  //Retrieve the length of the packet
481  length = netBufferGetLength(buffer) - offset;
482 
483  //Check the frame length
485  {
486  //The transmitter can accept another packet
487  osSetEvent(&interface->nicTxEvent);
488  //Report an error
489  return ERROR_INVALID_LENGTH;
490  }
491 
492  //Make sure the current buffer is available for writing
493  if((txCurDmaDesc->size & DMA_DESC_EMPTY_FLAG) == 0)
494  {
495  return ERROR_FAILURE;
496  }
497 
498  //Copy user data to the transmit buffer
499  netBufferRead((uint8_t *) txCurDmaDesc->addr, buffer, offset, length);
500 
501  //Set the packet length and give the ownership of the descriptor to the DMA
502  txCurDmaDesc->size = length & DMA_DESC_SIZE_MASK;
503 
504  //Check whether DMA transfers are suspended
505  if((MAC->DMA_TX_CTRL & DMA_TX_CTRL_TX_EN) == 0)
506  {
507  //Set the start position in the ring buffer
508  MAC->DMA_TX_DESC = (uint32_t) txCurDmaDesc;
509  }
510 
511  //Instruct the DMA controller to transfer the packet
512  MAC->DMA_TX_CTRL = DMA_TX_CTRL_TX_EN;
513 
514  //Point to the next descriptor in the list
515  txCurDmaDesc = (M2sxxxTxDmaDesc *) txCurDmaDesc->next;
516 
517  //Check whether the next buffer is available for writing
518  if((txCurDmaDesc->size & DMA_DESC_EMPTY_FLAG) != 0)
519  {
520  //The transmitter can accept another packet
521  osSetEvent(&interface->nicTxEvent);
522  }
523 
524  //Data successfully written
525  return NO_ERROR;
526 }
527 
528 
529 /**
530  * @brief Receive a packet
531  * @param[in] interface Underlying network interface
532  * @return Error code
533  **/
534 
536 {
537  error_t error;
538  size_t n;
539  NetRxAncillary ancillary;
540 
541  //The current buffer is available for reading?
542  if((rxCurDmaDesc->size & DMA_DESC_EMPTY_FLAG) == 0)
543  {
544  //Retrieve the length of the frame
545  n = rxCurDmaDesc->size & DMA_DESC_SIZE_MASK;
546  //Limit the number of data to read
548 
549  //Additional options can be passed to the stack along with the packet
550  ancillary = NET_DEFAULT_RX_ANCILLARY;
551 
552  //Pass the packet to the upper layer
553  nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->addr, n, &ancillary);
554 
555  //Give the ownership of the descriptor back to the DMA
556  rxCurDmaDesc->size = DMA_DESC_EMPTY_FLAG;
557 
558  //Check whether DMA transfers are suspended
559  if((MAC->DMA_RX_CTRL & DMA_RX_CTRL_RX_EN) == 0)
560  {
561  //Set the start position in the ring buffer
562  MAC->DMA_RX_DESC = (uint32_t) rxCurDmaDesc;
563  }
564 
565  //Enable the DMA transfer of received packets
566  MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
567  //Point to the next descriptor in the list
568  rxCurDmaDesc = (M2sxxxRxDmaDesc *) rxCurDmaDesc->next;
569 
570  //Valid packet received
571  error = NO_ERROR;
572  }
573  else
574  {
575  //Check whether DMA transfers are suspended
576  if((MAC->DMA_RX_CTRL & DMA_RX_CTRL_RX_EN) == 0)
577  {
578  //Set the start position in the ring buffer
579  MAC->DMA_RX_DESC = (uint32_t) rxCurDmaDesc;
580  }
581 
582  //Enable the DMA transfer of received packets
583  MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
584 
585  //No more data in the receive buffer
586  error = ERROR_BUFFER_EMPTY;
587  }
588 
589  //Return status code
590  return error;
591 }
592 
593 
594 /**
595  * @brief Configure MAC address filtering
596  * @param[in] interface Underlying network interface
597  * @return Error code
598  **/
599 
601 {
602  //Ethernet MAC does not implement multicast filtering
603  return NO_ERROR;
604 }
605 
606 
607 /**
608  * @brief Adjust MAC configuration parameters for proper operation
609  * @param[in] interface Underlying network interface
610  * @return Error code
611  **/
612 
614 {
615  uint32_t temp;
616 
617  //10BASE-T or 100BASE-TX operation mode?
618  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
619  {
620  //The link operates at 100 Mbps
621  temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED;
622  SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_100MBPS;
623 
624  //Configure the RMII module with the current operating speed
625  MAC->INTERFACE_CTRL |= INTERFACE_CTRL_SPEED;
626 
627  //Use nibble mode
628  temp = MAC->CFG2 & ~CFG2_INTERFACE_MODE;
629  MAC->CFG2 = temp | CFG2_INTERFACE_MODE_NIBBLE;
630  }
631  else
632  {
633  //The link operates at 10 Mbps
634  if((SYSREG->MAC_CR & MAC_CR_ETH_PHY_MODE) == MAC_CR_ETH_PHY_MODE_MII)
635  {
636  temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED;
637  SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_100MBPS;
638  }
639  else
640  {
641  temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED;
642  SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_10MBPS;
643  }
644 
645  //Configure the RMII module with the current operating speed
646  MAC->INTERFACE_CTRL &= ~INTERFACE_CTRL_SPEED;
647 
648  //Use nibble mode
649  temp = MAC->CFG2 & ~CFG2_INTERFACE_MODE;
650  MAC->CFG2 = temp | CFG2_INTERFACE_MODE_NIBBLE;
651  }
652 
653  //Half-duplex or full-duplex mode?
654  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
655  {
656  //Configure MAC to operate in full-duplex mode
657  MAC->CFG2 |= CFG2_FULL_DUPLEX;
658  MAC->FIFO_CFG5 &= ~FIFO_CFG5_CFGHDPLX;
659  }
660  else
661  {
662  //Configure MAC to operate in half-duplex mode
663  MAC->CFG2 &= ~CFG2_FULL_DUPLEX;
664  MAC->FIFO_CFG5 |= FIFO_CFG5_CFGHDPLX;
665  }
666 
667  //Successful processing
668  return NO_ERROR;
669 }
670 
671 
672 /**
673  * @brief Write PHY register
674  * @param[in] opcode Access type (2 bits)
675  * @param[in] phyAddr PHY address (5 bits)
676  * @param[in] regAddr Register address (5 bits)
677  * @param[in] data Register value
678  **/
679 
680 void m2sxxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
681  uint8_t regAddr, uint16_t data)
682 {
683  //Valid opcode?
684  if(opcode == SMI_OPCODE_WRITE)
685  {
686  //Set PHY address and register address
687  MAC->MII_ADDRESS = (phyAddr << MII_ADDRESS_PHY_ADDR_POS) | regAddr;
688  //Start a write operation
689  MAC->MII_CTRL = data;
690 
691  //Wait for the write to complete
692  while((MAC->MII_INDICATORS & MII_INDICATORS_BUSY) != 0)
693  {
694  }
695  }
696  else
697  {
698  //The MAC peripheral only supports standard Clause 22 opcodes
699  }
700 }
701 
702 
703 /**
704  * @brief Read PHY register
705  * @param[in] opcode Access type (2 bits)
706  * @param[in] phyAddr PHY address (5 bits)
707  * @param[in] regAddr Register address (5 bits)
708  * @return Register value
709  **/
710 
711 uint16_t m2sxxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
712  uint8_t regAddr)
713 {
714  uint16_t data;
715 
716  //Valid opcode?
717  if(opcode == SMI_OPCODE_READ)
718  {
719  //Set PHY address and register address
720  MAC->MII_ADDRESS = (phyAddr << MII_ADDRESS_PHY_ADDR_POS) | regAddr;
721  //Start a read operation
722  MAC->MII_COMMAND = MII_COMMAND_READ;
723 
724  //Wait for the read to complete
725  while((MAC->MII_INDICATORS & MII_INDICATORS_BUSY) != 0)
726  {
727  }
728 
729  //Clear command register
730  MAC->MII_COMMAND = 0;
731  //Get register value
732  data = MAC->MII_STATUS;
733  }
734  else
735  {
736  //The MAC peripheral only supports standard Clause 22 opcodes
737  data = 0;
738  }
739 
740  //Return the value of the PHY register
741  return data;
742 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint8_t length
Definition: coap_common.h:190
#define DMA_IRQ_MASK_RX_PKT_RECEIVED
#define CFG2_PREAMBLE_7
uint8_t opcode
Definition: dns_common.h:172
#define MII_ADDRESS_PHY_ADDR_POS
#define DMA_IRQ_TX_PKT_SENT
int bool_t
Definition: compiler_port.h:49
#define FIFO_CFG5_CFGHDPLX
#define netEvent
Definition: net_legacy.h:267
#define MAC_CR_ETH_LINE_SPEED
#define CFG2_LENGTH_FIELD_CHECK
#define M2SXXX_ETH_IRQ_GROUP_PRIORITY
uint8_t data[]
Definition: ethernet.h:209
#define MII_CONFIG_CLKSEL_DIV28
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define CFG2_CRC_EN
Transmit DMA descriptor.
#define M2SXXX_ETH_TX_BUFFER_SIZE
#define FIFO_CFG1_DEFAULT_VALUE
#define CFG1_TX_EN
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define TRUE
Definition: os_port.h:50
void EthernetMAC_IRQHandler(void)
M2Sxxx Ethernet MAC interrupt service routine.
#define FIFO_CFG5_TRUNCATED
error_t m2sxxxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t m2sxxxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
#define MAC_CR_ETH_LINE_SPEED_100MBPS
#define CFG1_RX_EN
void m2sxxxEthTick(NetInterface *interface)
M2Sxxx Ethernet MAC timer handler.
#define DMA_TX_CTRL_TX_EN
#define M2SXXX_ETH_RX_BUFFER_SIZE
#define MAC_CR_ETH_PHY_MODE
#define INTERFACE_CTRL_RESET
#define DMA_RX_STATUS_RX_PKT_RECEIVED
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define osExitIsr(flag)
SmartFusion2 (M2Sxxx) Ethernet MAC driver.
error_t m2sxxxEthInit(NetInterface *interface)
M2Sxxx Ethernet MAC initialization.
#define SMI_OPCODE_WRITE
Definition: nic.h:65
#define FIFO_CFG5_RECEIVE_ERROR
#define M2SXXX_ETH_IRQ_PRIORITY_GROUPING
error_t m2sxxxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define FALSE
Definition: os_port.h:46
#define CFG2_INTERFACE_MODE
#define EDAC_CR_MAC_EDAC_RX_EN
#define FIFO_CFG4_RECEIVE_ERROR
#define CFG2_INTERFACE_MODE_NIBBLE
#define CFG1_RESET_RX_FUNCTION
error_t
Error codes.
Definition: error.h:42
#define FIFO_CFG0_FTFENREQ
void m2sxxxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define CFG1_RESET_RX_MAC_CTRL
#define FIFO_CFG0_HSTRSTWT
void m2sxxxEthInitGpio(NetInterface *interface)
#define FIFO_CFG4_TRUNCATED
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
error_t m2sxxxEthReceivePacket(NetInterface *interface)
Receive a packet.
Generic error code.
Definition: error.h:45
void m2sxxxEthEventHandler(NetInterface *interface)
M2Sxxx Ethernet MAC event handler.
#define txBuffer
#define DMA_IRQ_MASK_TX_PKT_SENT
#define NetRxAncillary
Definition: net_misc.h:40
#define FIFO_CFG0_HSTRSTST
#define MAC_CR_ETH_PHY_MODE_MII
#define NetInterface
Definition: net.h:36
#define FIFO_CFG2_DEFAULT_VALUE
#define FIFO_CFG5_HSTFLTRFRMDC
#define FIFO_CFG5_HSTDRPLT64
#define FIFO_CFG5_RECEPTION_OK
#define MII_INDICATORS_BUSY
const NicDriver m2sxxxEthDriver
M2Sxxx Ethernet MAC driver.
#define NetTxAncillary
Definition: net_misc.h:36
#define FIFO_CFG0_WTMENREQ
#define FIFO_CFG0_HSTRSTSR
#define CFG1_SOFT_RESET
#define SMI_OPCODE_READ
Definition: nic.h:66
#define DMA_RX_CTRL_RX_EN
#define TRACE_INFO(...)
Definition: debug.h:95
#define EDAC_CR_MAC_EDAC_TX_EN
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define DMA_DESC_EMPTY_FLAG
#define MIN(a, b)
Definition: os_port.h:62
#define FIFO_CFG3_DEFAULT_VALUE
#define rxBuffer
#define FIFO_CFG0_FRFENREQ
#define MAC_CR_ETH_LINE_SPEED_10MBPS
#define M2SXXX_ETH_IRQ_SUB_PRIORITY
#define CFG1_RESET_TX_MAC_CTRL
uint16_t regAddr
#define DMA_TX_STATUS_TX_PKT_SENT
#define ETH_MTU
Definition: ethernet.h:105
uint8_t n
#define MII_COMMAND_READ
#define osEnterIsr()
#define CFG2_PAD_CRC_EN
#define DMA_IRQ_RX_PKT_RECEIVED
#define FIFO_CFG0_SRFENREQ
#define rxDmaDesc
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define FIFO_CFG0_HSTRSTFR
void m2sxxxEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define CFG1_RESET_TX_FUNCTION
#define txDmaDesc
unsigned int uint_t
Definition: compiler_port.h:45
void m2sxxxEthEnableIrq(NetInterface *interface)
Enable interrupts.
TCP/IP stack core.
NIC driver.
Definition: nic.h:257
#define CFG2_FULL_DUPLEX
#define DMA_DESC_SIZE_MASK
Receive DMA descriptor.
#define FIFO_CFG0_STFENREQ
uint16_t m2sxxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define INTERFACE_CTRL_SPEED
#define M2SXXX_ETH_TX_BUFFER_COUNT
void m2sxxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define FIFO_CFG0_HSTRSTFT
#define M2SXXX_ETH_RX_BUFFER_COUNT
Ethernet interface.
Definition: nic.h:82
#define FIFO_CFG5_INVALID_CRC
#define FIFO_CFG4_INVALID_CRC