m2sxxx_eth_driver.c
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1 /**
2  * @file m2sxxx_eth_driver.c
3  * @brief SmartFusion2 (M2Sxxx) Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "m2sxxx.h"
34 #include "core/net.h"
36 #include "debug.h"
37 
38 //Underlying network interface
39 static NetInterface *nicDriverInterface;
40 
41 //IAR EWARM compiler?
42 #if defined(__ICCARM__)
43 
44 //Transmit buffer
45 #pragma data_alignment = 4
47 //Receive buffer
48 #pragma data_alignment = 4
50 //Transmit DMA descriptors
51 #pragma data_alignment = 4
53 //Receive DMA descriptors
54 #pragma data_alignment = 4
56 
57 //Keil MDK-ARM or GCC compiler?
58 #else
59 
60 //Transmit buffer
62  __attribute__((aligned(4)));
63 //Receive buffer
65  __attribute__((aligned(4)));
66 //Transmit DMA descriptors
68  __attribute__((aligned(4)));
69 //Receive DMA descriptors
71  __attribute__((aligned(4)));
72 
73 #endif
74 
75 //Pointer to the current TX DMA descriptor
76 static M2sxxxTxDmaDesc *txCurDmaDesc;
77 //Pointer to the current RX DMA descriptor
78 static M2sxxxRxDmaDesc *rxCurDmaDesc;
79 
80 
81 /**
82  * @brief M2Sxxx Ethernet MAC driver
83  **/
84 
86 {
88  ETH_MTU,
99  TRUE,
100  TRUE,
101  TRUE,
102  FALSE
103 };
104 
105 
106 /**
107  * @brief M2Sxxx Ethernet MAC initialization
108  * @param[in] interface Underlying network interface
109  * @return Error code
110  **/
111 
113 {
114  error_t error;
115 
116  //Debug message
117  TRACE_INFO("Initializing M2Sxxx Ethernet MAC...\r\n");
118 
119  //Save underlying network interface
120  nicDriverInterface = interface;
121 
122  //Disable EDAC feature
123  SYSREG->EDAC_CR &= ~(EDAC_CR_MAC_EDAC_RX_EN | EDAC_CR_MAC_EDAC_TX_EN);
124 
125  //Reset the MAC module
128 
129  //Reset the interface module
130  MAC->INTERFACE_CTRL = INTERFACE_CTRL_RESET;
131 
132  //Reset FIFOs
133  MAC->FIFO_CFG0 = FIFO_CFG0_HSTRSTFT | FIFO_CFG0_HSTRSTST |
135 
136  //Take the MAC module out of reset
137  MAC->CFG1 = 0;
138  //Take the interface module out of reset
139  MAC->INTERFACE_CTRL = 0;
140  //Take the FIFOs out of reset
141  MAC->FIFO_CFG0 = 0;
142 
143  //Select interface mode (MII, RMII, GMII or TBI)
144  m2sxxxEthInitGpio(interface);
145 
146  //Select the proper divider for the MDC clock
147  MAC->MII_CONFIG = MII_CONFIG_CLKSEL_DIV28;
148 
149  //PHY transceiver initialization
150  error = interface->phyDriver->init(interface);
151  //Failed to initialize PHY transceiver?
152  if(error)
153  return error;
154 
155  //Set the upper 16 bits of the MAC address
156  MAC->STATION_ADDRESS2 = (interface->macAddr.b[0] << 16) |
157  (interface->macAddr.b[1] << 24);
158 
159  //Set the lower 32 bits of the MAC address
160  MAC->STATION_ADDRESS1 = interface->macAddr.b[2] |
161  (interface->macAddr.b[3] << 8) |
162  (interface->macAddr.b[4] << 16) |
163  (interface->macAddr.b[5] << 24);
164 
165  //Maximum frame length to be accepted
166  MAC->MAX_FRAME_LENGTH = 1518;
167 
168  //Disable flow control
169  MAC->CFG1 = 0;
170 
171  //All short frames will be zero-padded to 60 bytes and a valid CRC
172  //is then appended
175 
176  //Enable TX and RX FIFOs
177  MAC->FIFO_CFG0 = FIFO_CFG0_FTFENREQ | FIFO_CFG0_STFENREQ |
179 
180  //Use default FIFO configuration
181  MAC->FIFO_CFG1 = FIFO_CFG1_DEFAULT_VALUE;
182  MAC->FIFO_CFG2 = FIFO_CFG2_DEFAULT_VALUE;
183  MAC->FIFO_CFG3 = FIFO_CFG3_DEFAULT_VALUE;
184 
185  //Drop frames less than 64 bytes
186  MAC->FIFO_CFG5 = FIFO_CFG5_HSTDRPLT64 | FIFO_CFG5_HSTFLTRFRMDC;
187 
188  //Specify the statistics vectors that will be checked
189  MAC->FIFO_CFG5 &= ~(FIFO_CFG5_TRUNCATED | FIFO_CFG5_RECEPTION_OK |
191 
192  //Configure frame filtering
193  MAC->FIFO_CFG4 = FIFO_CFG4_TRUNCATED | FIFO_CFG4_INVALID_CRC |
195 
196  //Initialize DMA descriptor lists
197  m2sxxxEthInitDmaDesc(interface);
198 
199  //Enable the desired Ethernet interrupts
201 
202  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
203  NVIC_SetPriorityGrouping(M2SXXX_ETH_IRQ_PRIORITY_GROUPING);
204 
205  //Configure Ethernet interrupt priority
206  NVIC_SetPriority(EthernetMAC_IRQn, NVIC_EncodePriority(M2SXXX_ETH_IRQ_PRIORITY_GROUPING,
208 
209  //Enable transmission and reception
210  MAC->CFG1 |= CFG1_TX_EN | CFG1_RX_EN;
211  //Enable the DMA transfer of received packets
212  MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
213 
214  //Accept any packets from the upper layer
215  osSetEvent(&interface->nicTxEvent);
216 
217  //Successful initialization
218  return NO_ERROR;
219 }
220 
221 
222 //SF2-STARTER-KIT-ES-2 evaluation board?
223 #if defined(USE_SF2_STARTER_KIT_ES_2)
224 
225 /**
226  * @brief GPIO configuration
227  * @param[in] interface Underlying network interface
228  **/
229 
230 void m2sxxxEthInitGpio(NetInterface *interface)
231 {
232  //Select MII interface mode
233  SYSREG->MAC_CR = MAC_CR_ETH_PHY_MODE_MII;
234 }
235 
236 #endif
237 
238 
239 /**
240  * @brief Initialize DMA descriptor lists
241  * @param[in] interface Underlying network interface
242  **/
243 
245 {
246  uint_t i;
247 
248  //Initialize TX DMA descriptor list
249  for(i = 0; i < M2SXXX_ETH_TX_BUFFER_COUNT; i++)
250  {
251  //Transmit buffer address
252  txDmaDesc[i].addr = (uint32_t) txBuffer[i];
253  //The descriptor is initially owned by the user
254  txDmaDesc[i].size = DMA_DESC_EMPTY_FLAG;
255  //Next descriptor address
256  txDmaDesc[i].next = (uint32_t) &txDmaDesc[i + 1];
257  }
258 
259  //The last descriptor is chained to the first entry
260  txDmaDesc[i - 1].next = (uint32_t) &txDmaDesc[0];
261  //Point to the very first descriptor
262  txCurDmaDesc = &txDmaDesc[0];
263 
264  //Initialize RX DMA descriptor list
265  for(i = 0; i < M2SXXX_ETH_RX_BUFFER_COUNT; i++)
266  {
267  //Receive buffer address
268  rxDmaDesc[i].addr = (uint32_t) rxBuffer[i];
269  //The descriptor is initially owned by the DMA
270  rxDmaDesc[i].size = DMA_DESC_EMPTY_FLAG;
271  //Next descriptor address
272  rxDmaDesc[i].next = (uint32_t) &rxDmaDesc[i + 1];
273  }
274 
275  //The last descriptor is chained to the first entry
276  rxDmaDesc[i - 1].next = (uint32_t) &rxDmaDesc[0];
277  //Point to the very first descriptor
278  rxCurDmaDesc = &rxDmaDesc[0];
279 
280  //Start location of the TX descriptor list
281  MAC->DMA_TX_DESC = (uint32_t) txDmaDesc;
282  //Start location of the RX descriptor list
283  MAC->DMA_RX_DESC = (uint32_t) rxDmaDesc;
284 }
285 
286 
287 /**
288  * @brief M2Sxxx Ethernet MAC timer handler
289  *
290  * This routine is periodically called by the TCP/IP stack to
291  * handle periodic operations such as polling the link state
292  *
293  * @param[in] interface Underlying network interface
294  **/
295 
296 void m2sxxxEthTick(NetInterface *interface)
297 {
298  //Handle periodic operations
299  interface->phyDriver->tick(interface);
300 }
301 
302 
303 /**
304  * @brief Enable interrupts
305  * @param[in] interface Underlying network interface
306  **/
307 
309 {
310  //Enable Ethernet MAC interrupts
311  NVIC_EnableIRQ(EthernetMAC_IRQn);
312  //Enable Ethernet PHY interrupts
313  interface->phyDriver->enableIrq(interface);
314 }
315 
316 
317 /**
318  * @brief Disable interrupts
319  * @param[in] interface Underlying network interface
320  **/
321 
323 {
324  //Disable Ethernet MAC interrupts
325  NVIC_DisableIRQ(EthernetMAC_IRQn);
326  //Disable Ethernet PHY interrupts
327  interface->phyDriver->disableIrq(interface);
328 }
329 
330 
331 /**
332  * @brief M2Sxxx Ethernet MAC interrupt service routine
333  **/
334 
336 {
337  bool_t flag;
338  uint32_t status;
339 
340  //Enter interrupt service routine
341  osEnterIsr();
342 
343  //This flag will be set if a higher priority task must be woken
344  flag = FALSE;
345 
346  //Read interrupt status register
347  status = MAC->DMA_IRQ;
348 
349  //A packet has been transmitted?
350  if(status & DMA_IRQ_TX_PKT_SENT)
351  {
352  //Clear TX interrupt flag
353  MAC->DMA_TX_STATUS = DMA_TX_STATUS_TX_PKT_SENT;
354 
355  //Check whether the TX buffer is available for writing
356  if(txCurDmaDesc->size & DMA_DESC_EMPTY_FLAG)
357  {
358  //Notify the TCP/IP stack that the transmitter is ready to send
359  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
360  }
361  }
362 
363  //A packet has been received?
364  if(status & DMA_IRQ_RX_PKT_RECEIVED)
365  {
366  //Disable RX interrupt
367  MAC->DMA_IRQ_MASK &= ~DMA_IRQ_MASK_RX_PKT_RECEIVED;
368 
369  //Set event flag
370  nicDriverInterface->nicEvent = TRUE;
371  //Notify the TCP/IP stack of the event
372  flag |= osSetEventFromIsr(&netEvent);
373  }
374 
375  //Leave interrupt service routine
376  osExitIsr(flag);
377 }
378 
379 
380 /**
381  * @brief M2Sxxx Ethernet MAC event handler
382  * @param[in] interface Underlying network interface
383  **/
384 
386 {
387  //Packet received?
388  if(MAC->DMA_RX_STATUS & DMA_RX_STATUS_RX_PKT_RECEIVED)
389  {
390  //Process all the pending packets
391  while(MAC->DMA_RX_STATUS & DMA_RX_STATUS_RX_PKT_RECEIVED)
392  {
393  //Clear RX interrupt flag
394  MAC->DMA_RX_STATUS = DMA_RX_STATUS_RX_PKT_RECEIVED;
395  //Read incoming packet
396  m2sxxxEthReceivePacket(interface);
397  }
398  }
399 
400  //Re-enable Ethernet interrupts
402 }
403 
404 
405 /**
406  * @brief Send a packet
407  * @param[in] interface Underlying network interface
408  * @param[in] buffer Multi-part buffer containing the data to send
409  * @param[in] offset Offset to the first data byte
410  * @return Error code
411  **/
412 
414  const NetBuffer *buffer, size_t offset)
415 {
416  size_t length;
417 
418  //Retrieve the length of the packet
419  length = netBufferGetLength(buffer) - offset;
420 
421  //Check the frame length
423  {
424  //The transmitter can accept another packet
425  osSetEvent(&interface->nicTxEvent);
426  //Report an error
427  return ERROR_INVALID_LENGTH;
428  }
429 
430  //Make sure the current buffer is available for writing
431  if(!(txCurDmaDesc->size & DMA_DESC_EMPTY_FLAG))
432  return ERROR_FAILURE;
433 
434  //Copy user data to the transmit buffer
435  netBufferRead((uint8_t *) txCurDmaDesc->addr, buffer, offset, length);
436 
437  //Set the packet length and give the ownership of the descriptor to the DMA
438  txCurDmaDesc->size = length & DMA_DESC_SIZE_MASK;
439 
440  //Check whether DMA transfers are suspended
441  if(!(MAC->DMA_TX_CTRL & DMA_TX_CTRL_TX_EN))
442  {
443  //Set the start position in the ring buffer
444  MAC->DMA_TX_DESC = (uint32_t) txCurDmaDesc;
445  }
446 
447  //Instruct the DMA controller to transfer the packet
448  MAC->DMA_TX_CTRL = DMA_TX_CTRL_TX_EN;
449 
450  //Point to the next descriptor in the list
451  txCurDmaDesc = (M2sxxxTxDmaDesc *) txCurDmaDesc->next;
452 
453  //Check whether the next buffer is available for writing
454  if(txCurDmaDesc->size & DMA_DESC_EMPTY_FLAG)
455  {
456  //The transmitter can accept another packet
457  osSetEvent(&interface->nicTxEvent);
458  }
459 
460  //Data successfully written
461  return NO_ERROR;
462 }
463 
464 
465 /**
466  * @brief Receive a packet
467  * @param[in] interface Underlying network interface
468  * @return Error code
469  **/
470 
472 {
473  error_t error;
474  size_t n;
475 
476  //The current buffer is available for reading?
477  if(!(rxCurDmaDesc->size & DMA_DESC_EMPTY_FLAG))
478  {
479  //Retrieve the length of the frame
480  n = rxCurDmaDesc->size & DMA_DESC_SIZE_MASK;
481  //Limit the number of data to read
483 
484  //Pass the packet to the upper layer
485  nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->addr, n);
486 
487  //Give the ownership of the descriptor back to the DMA
488  rxCurDmaDesc->size = DMA_DESC_EMPTY_FLAG;
489 
490  //Check whether DMA transfers are suspended
491  if(!(MAC->DMA_RX_CTRL & DMA_RX_CTRL_RX_EN))
492  {
493  //Set the start position in the ring buffer
494  MAC->DMA_RX_DESC = (uint32_t) rxCurDmaDesc;
495  }
496 
497  //Enable the DMA transfer of received packets
498  MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
499  //Point to the next descriptor in the list
500  rxCurDmaDesc = (M2sxxxRxDmaDesc *) rxCurDmaDesc->next;
501 
502  //Valid packet received
503  error = NO_ERROR;
504  }
505  else
506  {
507  //Check whether DMA transfers are suspended
508  if(!(MAC->DMA_RX_CTRL & DMA_RX_CTRL_RX_EN))
509  {
510  //Set the start position in the ring buffer
511  MAC->DMA_RX_DESC = (uint32_t) rxCurDmaDesc;
512  }
513 
514  //Enable the DMA transfer of received packets
515  MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
516 
517  //No more data in the receive buffer
518  error = ERROR_BUFFER_EMPTY;
519  }
520 
521  //Return status code
522  return error;
523 }
524 
525 
526 /**
527  * @brief Configure MAC address filtering
528  * @param[in] interface Underlying network interface
529  * @return Error code
530  **/
531 
533 {
534  //Ethernet MAC does not implement multicast filtering
535  return NO_ERROR;
536 }
537 
538 
539 /**
540  * @brief Adjust MAC configuration parameters for proper operation
541  * @param[in] interface Underlying network interface
542  * @return Error code
543  **/
544 
546 {
547  uint32_t temp;
548 
549  //10BASE-T or 100BASE-TX operation mode?
550  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
551  {
552  //The link operates at 100 Mbps
553  temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED;
554  SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_100MBPS;
555 
556  //Configure the RMII module with the current operating speed
557  MAC->INTERFACE_CTRL |= INTERFACE_CTRL_SPEED;
558 
559  //Use nibble mode
560  temp = MAC->CFG2 & ~CFG2_INTERFACE_MODE;
561  MAC->CFG2 = temp | CFG2_INTERFACE_MODE_NIBBLE;
562  }
563  else
564  {
565  //The link operates at 10 Mbps
566  if((SYSREG->MAC_CR & MAC_CR_ETH_PHY_MODE) == MAC_CR_ETH_PHY_MODE_MII)
567  {
568  temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED;
569  SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_100MBPS;
570  }
571  else
572  {
573  temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED;
574  SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_10MBPS;
575  }
576 
577  //Configure the RMII module with the current operating speed
578  MAC->INTERFACE_CTRL &= ~INTERFACE_CTRL_SPEED;
579 
580  //Use nibble mode
581  temp = MAC->CFG2 & ~CFG2_INTERFACE_MODE;
582  MAC->CFG2 = temp | CFG2_INTERFACE_MODE_NIBBLE;
583  }
584 
585  //Half-duplex or full-duplex mode?
586  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
587  {
588  //Configure MAC to operate in full-duplex mode
589  MAC->CFG2 |= CFG2_FULL_DUPLEX;
590  MAC->FIFO_CFG5 &= ~FIFO_CFG5_CFGHDPLX;
591  }
592  else
593  {
594  //Configure MAC to operate in half-duplex mode
595  MAC->CFG2 &= ~CFG2_FULL_DUPLEX;
596  MAC->FIFO_CFG5 |= FIFO_CFG5_CFGHDPLX;
597  }
598 
599  //Successful processing
600  return NO_ERROR;
601 }
602 
603 
604 /**
605  * @brief Write PHY register
606  * @param[in] phyAddr PHY address
607  * @param[in] regAddr Register address
608  * @param[in] data Register value
609  **/
610 
611 void m2sxxxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
612 {
613  //Set PHY address and register address
614  MAC->MII_ADDRESS = (phyAddr << MII_ADDRESS_PHY_ADDR_POS) | regAddr;
615  //Start a write operation
616  MAC->MII_CTRL = data;
617 
618  //Wait for the write to complete
619  while(MAC->MII_INDICATORS & MII_INDICATORS_BUSY);
620 }
621 
622 
623 /**
624  * @brief Read PHY register
625  * @param[in] phyAddr PHY address
626  * @param[in] regAddr Register address
627  * @return Register value
628  **/
629 
630 uint16_t m2sxxxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
631 {
632  //Set PHY address and register address
633  MAC->MII_ADDRESS = (phyAddr << MII_ADDRESS_PHY_ADDR_POS) | regAddr;
634  //Start a read operation
635  MAC->MII_COMMAND = MII_COMMAND_READ;
636 
637  //Wait for the read to complete
638  while(MAC->MII_INDICATORS & MII_INDICATORS_BUSY);
639 
640  //Clear command register
641  MAC->MII_COMMAND = 0;
642  //Return PHY register contents
643  return MAC->MII_STATUS;
644 }
#define M2SXXX_ETH_RX_BUFFER_COUNT
#define FIFO_CFG5_INVALID_CRC
#define DMA_IRQ_TX_PKT_SENT
#define MII_ADDRESS_PHY_ADDR_POS
#define FIFO_CFG4_INVALID_CRC
#define txDmaDesc
#define MAC_CR_ETH_LINE_SPEED
#define DMA_IRQ_MASK_RX_PKT_RECEIVED
#define CFG2_PREAMBLE_7
SmartFusion2 (M2Sxxx) Ethernet MAC controller.
#define M2SXXX_ETH_TX_BUFFER_SIZE
#define FIFO_CFG1_DEFAULT_VALUE
#define CFG2_CRC_EN
#define FIFO_CFG5_CFGHDPLX
#define CFG2_LENGTH_FIELD_CHECK
#define M2SXXX_ETH_IRQ_GROUP_PRIORITY
#define CFG1_TX_EN
TCP/IP stack core.
#define MII_CONFIG_CLKSEL_DIV28
Debugging facilities.
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define FIFO_CFG5_TRUNCATED
Generic error code.
Definition: error.h:43
#define CFG1_RX_EN
#define rxDmaDesc
void m2sxxxEthTick(NetInterface *interface)
M2Sxxx Ethernet MAC timer handler.
void EthernetMAC_IRQHandler(void)
M2Sxxx Ethernet MAC interrupt service routine.
#define txBuffer
error_t m2sxxxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define M2SXXX_ETH_RX_BUFFER_SIZE
#define MAC_CR_ETH_LINE_SPEED_100MBPS
#define DMA_TX_CTRL_TX_EN
#define INTERFACE_CTRL_RESET
#define MAC_CR_ETH_PHY_MODE
#define FIFO_CFG5_RECEIVE_ERROR
error_t m2sxxxEthInit(NetInterface *interface)
M2Sxxx Ethernet MAC initialization.
#define DMA_RX_STATUS_RX_PKT_RECEIVED
#define M2SXXX_ETH_IRQ_PRIORITY_GROUPING
error_t m2sxxxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define TRUE
Definition: os_port.h:48
#define FIFO_CFG0_FTFENREQ
#define EDAC_CR_MAC_EDAC_RX_EN
#define FIFO_CFG4_RECEIVE_ERROR
#define CFG2_INTERFACE_MODE
#define CFG2_INTERFACE_MODE_NIBBLE
#define CFG1_RESET_RX_MAC_CTRL
#define CFG1_RESET_RX_FUNCTION
#define FIFO_CFG4_TRUNCATED
void m2sxxxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
uint16_t m2sxxxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define FIFO_CFG0_HSTRSTWT
#define FIFO_CFG5_HSTFLTRFRMDC
#define FIFO_CFG2_DEFAULT_VALUE
void m2sxxxEthInitGpio(NetInterface *interface)
error_t m2sxxxEthReceivePacket(NetInterface *interface)
Receive a packet.
#define FIFO_CFG5_RECEPTION_OK
#define MII_INDICATORS_BUSY
const NicDriver m2sxxxEthDriver
M2Sxxx Ethernet MAC driver.
void m2sxxxEthEventHandler(NetInterface *interface)
M2Sxxx Ethernet MAC event handler.
Receive DMA descriptor.
#define DMA_IRQ_MASK_TX_PKT_SENT
#define MAC_CR_ETH_PHY_MODE_MII
#define FIFO_CFG0_HSTRSTST
#define FIFO_CFG0_WTMENREQ
#define CFG1_SOFT_RESET
#define FIFO_CFG0_HSTRSTSR
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define FIFO_CFG5_HSTDRPLT64
error_t m2sxxxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define DMA_RX_CTRL_RX_EN
NIC driver.
Definition: nic.h:161
#define DMA_DESC_EMPTY_FLAG
#define FIFO_CFG3_DEFAULT_VALUE
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
#define EDAC_CR_MAC_EDAC_TX_EN
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define FIFO_CFG0_FRFENREQ
#define M2SXXX_ETH_IRQ_SUB_PRIORITY
#define MAC_CR_ETH_LINE_SPEED_10MBPS
#define CFG1_RESET_TX_MAC_CTRL
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
Transmit DMA descriptor.
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define MII_COMMAND_READ
unsigned int uint_t
Definition: compiler_port.h:43
#define DMA_TX_STATUS_TX_PKT_SENT
#define CFG2_PAD_CRC_EN
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
#define FIFO_CFG0_SRFENREQ
#define DMA_IRQ_RX_PKT_RECEIVED
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void m2sxxxEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define CFG1_RESET_TX_FUNCTION
#define osExitIsr(flag)
#define FIFO_CFG0_HSTRSTFR
void m2sxxxEthEnableIrq(NetInterface *interface)
Enable interrupts.
#define osEnterIsr()
#define DMA_DESC_SIZE_MASK
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
void m2sxxxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define M2SXXX_ETH_TX_BUFFER_COUNT
#define FALSE
Definition: os_port.h:44
#define CFG2_FULL_DUPLEX
int bool_t
Definition: compiler_port.h:47
#define FIFO_CFG0_HSTRSTFT
#define FIFO_CFG0_STFENREQ
#define INTERFACE_CTRL_SPEED