omapl138_eth_driver.h
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1 /**
2  * @file omapl138_eth_driver.h
3  * @brief OMAP-L138 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _OMAPL138_ETH_DRIVER_H
30 #define _OMAPL138_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef OMAPL138_ETH_TX_BUFFER_COUNT
37  #define OMAPL138_ETH_TX_BUFFER_COUNT 8
38 #elif (OMAPL138_ETH_TX_BUFFER_COUNT < 1)
39  #error OMAPL138_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef OMAPL138_ETH_TX_BUFFER_SIZE
44  #define OMAPL138_ETH_TX_BUFFER_SIZE 1536
45 #elif (OMAPL138_ETH_TX_BUFFER_SIZE != 1536)
46  #error OMAPL138_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef OMAPL138_ETH_RX_BUFFER_COUNT
51  #define OMAPL138_ETH_RX_BUFFER_COUNT 8
52 #elif (OMAPL138_ETH_RX_BUFFER_COUNT < 1)
53  #error OMAPL138_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef OMAPL138_ETH_RX_BUFFER_SIZE
58  #define OMAPL138_ETH_RX_BUFFER_SIZE 1536
59 #elif (OMAPL138_ETH_RX_BUFFER_SIZE != 1536)
60  #error OMAPL138_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Channel number for the TX interrupt
64 #ifndef OMAPL138_ETH_TX_IRQ_CHANNEL
65  #define OMAPL138_ETH_TX_IRQ_CHANNEL 3
66 #elif (OMAPL138_ETH_TX_IRQ_CHANNEL < 0 || OMAPL138_ETH_TX_IRQ_CHANNEL > 31)
67  #error OMAPL138_ETH_TX_IRQ_CHANNEL parameter is not valid
68 #endif
69 
70 //Channel number for the RX interrupt
71 #ifndef OMAPL138_ETH_RX_IRQ_CHANNEL
72  #define OMAPL138_ETH_RX_IRQ_CHANNEL 3
73 #elif (OMAPL138_ETH_RX_IRQ_CHANNEL < 0 || OMAPL138_ETH_RX_IRQ_CHANNEL > 31)
74  #error OMAPL138_ETH_RX_IRQ_CHANNEL parameter is not valid
75 #endif
76 
77 //EMAC cores
78 #define EMAC_CORE0 0
79 #define EMAC_CORE1 1
80 #define EMAC_CORE2 2
81 
82 //EMAC channels
83 #define EMAC_CH0 0
84 #define EMAC_CH1 1
85 #define EMAC_CH2 2
86 #define EMAC_CH3 3
87 #define EMAC_CH4 4
88 #define EMAC_CH5 5
89 #define EMAC_CH6 6
90 #define EMAC_CH7 7
91 
92 //SYSCFG0 registers
93 #define SYSCFG0_PINMUX_R(n) HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(n))
94 #define SYSCFG0_CFGCHIP3_R HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3)
95 
96 //EMAC registers
97 #define EMAC_TXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXREVID)
98 #define EMAC_TXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCONTROL)
99 #define EMAC_TXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXTEARDOWN)
100 #define EMAC_RXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXREVID)
101 #define EMAC_RXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCONTROL)
102 #define EMAC_RXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXTEARDOWN)
103 #define EMAC_TXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATRAW)
104 #define EMAC_TXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATMASKED)
105 #define EMAC_TXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKSET)
106 #define EMAC_TXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKCLEAR)
107 #define EMAC_MACINVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINVECTOR)
108 #define EMAC_MACEOIVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACEOIVECTOR)
109 #define EMAC_RXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATRAW)
110 #define EMAC_RXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATMASKED)
111 #define EMAC_RXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKSET)
112 #define EMAC_RXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKCLEAR)
113 #define EMAC_MACINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATRAW)
114 #define EMAC_MACINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATMASKED)
115 #define EMAC_MACINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKSET)
116 #define EMAC_MACINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKCLEAR)
117 #define EMAC_RXMBPENABLE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMBPENABLE)
118 #define EMAC_RXUNICASTSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTSET)
119 #define EMAC_RXUNICASTCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTCLEAR)
120 #define EMAC_RXMAXLEN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMAXLEN)
121 #define EMAC_RXBUFFEROFFSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBUFFEROFFSET)
122 #define EMAC_RXFILTERLOWTHRESH_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERLOWTHRESH)
123 #define EMAC_RXFLOWTHRESH_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFLOWTHRESH(n))
124 #define EMAC_RXFREEBUFFER_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFREEBUFFER(n))
125 #define EMAC_MACCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONTROL)
126 #define EMAC_MACSTATUS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSTATUS)
127 #define EMAC_EMCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_EMCONTROL)
128 #define EMAC_FIFOCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FIFOCONTROL)
129 #define EMAC_MACCONFIG_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONFIG)
130 #define EMAC_SOFTRESET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_SOFTRESET)
131 #define EMAC_MACSRCADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRLO)
132 #define EMAC_MACSRCADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRHI)
133 #define EMAC_MACHASH1_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH1)
134 #define EMAC_MACHASH2_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH2)
135 #define EMAC_BOFFTEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_BOFFTEST)
136 #define EMAC_TPACETEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TPACETEST)
137 #define EMAC_RXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSE)
138 #define EMAC_TXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSE)
139 #define EMAC_RXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXGOODFRAMES)
140 #define EMAC_RXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBCASTFRAMES)
141 #define EMAC_RXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMCASTFRAMES)
142 #define EMAC_RXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSEFRAMES)
143 #define EMAC_RXCRCERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCRCERRORS)
144 #define EMAC_RXALIGNCODEERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMACEMAC_RXOVERSIZED)
145 #define EMAC_RXJABBER_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXJABBER)
146 #define EMAC_RXUNDERSIZED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNDERSIZED)
147 #define EMAC_RXFRAGMENTS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFRAGMENTS)
148 #define EMAC_RXFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERED)
149 #define EMAC_RXQOSFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXQOSFILTERED)
150 #define EMAC_RXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXOCTETS)
151 #define EMAC_TXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXGOODFRAMES)
152 #define EMAC_TXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXBCASTFRAMES)
153 #define EMAC_TXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMCASTFRAMES)
154 #define EMAC_TXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSEFRAMES)
155 #define EMAC_TXDEFERRED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXDEFERRED)
156 #define EMAC_TXCOLLISION_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCOLLISION)
157 #define EMAC_TXSINGLECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXSINGLECOLL)
158 #define EMAC_TXMULTICOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMULTICOLL)
159 #define EMAC_TXEXCESSIVECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXEXCESSIVECOLL)
160 #define EMAC_TXLATECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXLATECOLL)
161 #define EMAC_TXUNDERRUN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXUNDERRUN)
162 #define EMAC_TXCARRIERSENSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCARRIERSENSE)
163 #define EMAC_TXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXOCTETS)
164 #define EMAC_FRAME64_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME64)
165 #define EMAC_FRAME65T127_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME65T127)
166 #define EMAC_FRAME128T255_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME128T255)
167 #define EMAC_FRAME256T511_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME256T511)
168 #define EMAC_FRAME512T1023_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME512T1023)
169 #define EMAC_FRAME1024TUP_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME1024TUP)
170 #define EMAC_NETOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_NETOCTETS)
171 #define EMAC_RXSOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXSOFOVERRUNS)
172 #define EMAC_RXMOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMOFOVERRUNS)
173 #define EMAC_RXDMAOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXDMAOVERRUNS)
174 #define EMAC_MACADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRLO)
175 #define EMAC_MACADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRHI)
176 #define EMAC_MACINDEX_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINDEX)
177 #define EMAC_TXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXHDP(n))
178 #define EMAC_RXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXHDP(n))
179 #define EMAC_TXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCP(n))
180 #define EMAC_RXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCP(n))
181 
182 //EMAC control registers
183 #define EMAC_CTRL_REVID_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_REVID)
184 #define EMAC_CTRL_SOFTRESET_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_SOFTRESET)
185 #define EMAC_CTRL_INTCONTRO_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_INTCONTROL)
186 #define EMAC_CTRL_C0RXTHRESHEN_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHEN)
187 #define EMAC_CTRL_CnRXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXEN(n))
188 #define EMAC_CTRL_CnTXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnTXEN(n))
189 #define EMAC_CTRL_CnMISCEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnMISCEN(n))
190 #define EMAC_CTRL_CnRXTHRESHEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXTHRESHEN(n))
191 #define EMAC_CTRL_C0RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHSTAT)
192 #define EMAC_CTRL_C0RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXSTAT)
193 #define EMAC_CTRL_C0TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXSTAT)
194 #define EMAC_CTRL_C0MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0MISCSTAT)
195 #define EMAC_CTRL_C1RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT)
196 #define EMAC_CTRL_C1RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT)
197 #define EMAC_CTRL_C1TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXSTAT)
198 #define EMAC_CTRL_C1MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1MISCSTAT)
199 #define EMAC_CTRL_C2RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXTHRESHSTAT)
200 #define EMAC_CTRL_C2RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXSTAT)
201 #define EMAC_CTRL_C2TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXSTAT)
202 #define EMAC_CTRL_C2MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2MISCSTAT)
203 #define EMAC_CTRL_C0RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXIMAX)
204 #define EMAC_CTRL_C0TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXIMAX)
205 #define EMAC_CTRL_C1RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXIMAX)
206 #define EMAC_CTRL_C1TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXIMAX)
207 #define EMAC_CTRL_C2RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXIMAX)
208 #define EMAC_CTRL_C2TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXIMAX)
209 
210 //MDIO registers
211 #define MDIO_REVID_R HWREG(SOC_MDIO_0_REGS + MDIO_REVID)
212 #define MDIO_CONTROL_R HWREG(SOC_MDIO_0_REGS + MDIO_CONTROL)
213 #define MDIO_ALIVE_R HWREG(SOC_MDIO_0_REGS + MDIO_ALIVE)
214 #define MDIO_LINK_R HWREG(SOC_MDIO_0_REGS + MDIO_LINK)
215 #define MDIO_LINKINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTRAW)
216 #define MDIO_LINKINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTMASKED)
217 #define MDIO_USERINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTRAW)
218 #define MDIO_USERINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKED)
219 #define MDIO_USERINTMASKSET_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKSET)
220 #define MDIO_USERINTMASKCLEAR_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKCLEAR)
221 #define MDIO_USERACCESS0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS0)
222 #define MDIO_USERPHYSEL0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL0)
223 #define MDIO_USERACCESS1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS1)
224 #define MDIO_USERPHYSEL1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL1)
225 
226 //MACEOIVECTOR register
227 #define EMAC_MACEOIVECTOR_C0RXTHRESH 0x00000000
228 #define EMAC_MACEOIVECTOR_C0RX 0x00000001
229 #define EMAC_MACEOIVECTOR_C0TX 0x00000002
230 #define EMAC_MACEOIVECTOR_C0MISC 0x00000003
231 #define EMAC_MACEOIVECTOR_C1RXTHRESH 0x00000004
232 #define EMAC_MACEOIVECTOR_C1RX 0x00000005
233 #define EMAC_MACEOIVECTOR_C1TX 0x00000006
234 #define EMAC_MACEOIVECTOR_C1MISC 0x00000007
235 #define EMAC_MACEOIVECTOR_C2RXTHRESH 0x00000008
236 #define EMAC_MACEOIVECTOR_C2RX 0x00000009
237 #define EMAC_MACEOIVECTOR_C2TX 0x0000000A
238 #define EMAC_MACEOIVECTOR_C2MISC 0x0000000B
239 
240 //TX buffer descriptor flags
241 #define EMAC_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
242 #define EMAC_TX_WORD1_BUFFER_POINTER 0xFFFFFFFF
243 #define EMAC_TX_WORD2_BUFFER_OFFSET 0xFFFF0000
244 #define EMAC_TX_WORD2_BUFFER_LENGTH 0x0000FFFF
245 #define EMAC_TX_WORD3_SOP 0x80000000
246 #define EMAC_TX_WORD3_EOP 0x40000000
247 #define EMAC_TX_WORD3_OWNER 0x20000000
248 #define EMAC_TX_WORD3_EOQ 0x10000000
249 #define EMAC_TX_WORD3_TDOWNCMPLT 0x08000000
250 #define EMAC_TX_WORD3_PASSCRC 0x04000000
251 #define EMAC_TX_WORD3_PACKET_LENGTH 0x0000FFFF
252 
253 //RX buffer descriptor flags
254 #define EMAC_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
255 #define EMAC_RX_WORD1_BUFFER_POINTER 0xFFFFFFFF
256 #define EMAC_RX_WORD2_BUFFER_OFFSET 0x07FF0000
257 #define EMAC_RX_WORD2_BUFFER_LENGTH 0x000007FF
258 #define EMAC_RX_WORD3_SOP 0x80000000
259 #define EMAC_RX_WORD3_EOP 0x40000000
260 #define EMAC_RX_WORD3_OWNER 0x20000000
261 #define EMAC_RX_WORD3_EOQ 0x10000000
262 #define EMAC_RX_WORD3_TDOWNCMPLT 0x08000000
263 #define EMAC_RX_WORD3_PASSCRC 0x04000000
264 #define EMAC_RX_WORD3_ERROR_MASK 0x03FF0000
265 #define EMAC_RX_WORD3_JABBER 0x02000000
266 #define EMAC_RX_WORD3_OVERSIZE 0x01000000
267 #define EMAC_RX_WORD3_FRAGMENT 0x00800000
268 #define EMAC_RX_WORD3_UNDERSIZED 0x00400000
269 #define EMAC_RX_WORD3_CONTROL 0x00200000
270 #define EMAC_RX_WORD3_OVERRUN 0x00100000
271 #define EMAC_RX_WORD3_CODEERROR 0x00080000
272 #define EMAC_RX_WORD3_ALIGNERROR 0x00040000
273 #define EMAC_RX_WORD3_CRCERROR 0x00020000
274 #define EMAC_RX_WORD3_NOMATCH 0x00010000
275 #define EMAC_RX_WORD3_PACKET_LENGTH 0x0000FFFF
276 
277 //C++ guard
278 #ifdef __cplusplus
279  extern "C" {
280 #endif
281 
282 
283 /**
284  * @brief TX buffer descriptor
285  **/
286 
287 typedef struct _Omapl138TxBufferDesc
288 {
289  uint32_t word0;
290  uint32_t word1;
291  uint32_t word2;
292  uint32_t word3;
296 
297 
298 /**
299  * @brief RX buffer descriptor
300  **/
301 
302 typedef struct _Omapl138RxBufferDesc
303 {
304  uint32_t word0;
305  uint32_t word1;
306  uint32_t word2;
307  uint32_t word3;
311 
312 
313 //AM335x Ethernet MAC driver
314 extern const NicDriver omapl138EthDriver;
315 
316 //AM335x Ethernet MAC related functions
318 void omapl138EthInitGpio(NetInterface *interface);
319 void omapl138EthInitBufferDesc(NetInterface *interface);
320 
321 void omapl138EthTick(NetInterface *interface);
322 
323 void omapl138EthEnableIrq(NetInterface *interface);
324 void omapl138EthDisableIrq(NetInterface *interface);
325 void omapl138EthTxIrqHandler(void);
326 void omapl138EthRxIrqHandler(void);
327 void omapl138EthEventHandler(NetInterface *interface);
328 
330  const NetBuffer *buffer, size_t offset);
331 
333 
336 
337 void omapl138EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
338 uint16_t omapl138EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
339 
340 //C++ guard
341 #ifdef __cplusplus
342  }
343 #endif
344 
345 #endif
error_t omapl138EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void omapl138EthDisableIrq(NetInterface *interface)
Disable interrupts.
struct _Omapl138TxBufferDesc * prev
TX buffer descriptor.
RX buffer descriptor.
struct _Omapl138TxBufferDesc Omapl138TxBufferDesc
TX buffer descriptor.
void omapl138EthTxIrqHandler(void)
Ethernet MAC transmit interrupt.
error_t omapl138EthReceivePacket(NetInterface *interface)
Receive a packet.
void omapl138EthInitGpio(NetInterface *interface)
void omapl138EthEventHandler(NetInterface *interface)
OMAP-L138 Ethernet MAC event handler.
void omapl138EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t omapl138EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void omapl138EthRxIrqHandler(void)
Ethernet MAC receive interrupt.
void omapl138EthEnableIrq(NetInterface *interface)
Enable interrupts.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
const NicDriver omapl138EthDriver
OMAP-L138 Ethernet MAC driver.
uint16_t regAddr
error_t omapl138EthInit(NetInterface *interface)
OMAP-L138 Ethernet MAC initialization.
error_t
Error codes.
Definition: error.h:40
uint16_t omapl138EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t omapl138EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
struct _Omapl138TxBufferDesc * next
void omapl138EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptor lists.
struct _Omapl138RxBufferDesc Omapl138RxBufferDesc
RX buffer descriptor.
struct _Omapl138RxBufferDesc * prev
void omapl138EthTick(NetInterface *interface)
OMAP-L138 Ethernet MAC timer handler.
Network interface controller abstraction layer.
struct _Omapl138RxBufferDesc * next