omapl138_eth_driver.h
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1 /**
2  * @file omapl138_eth_driver.h
3  * @brief OMAP-L138 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _OMAPL138_ETH_DRIVER_H
32 #define _OMAPL138_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef OMAPL138_ETH_TX_BUFFER_COUNT
39  #define OMAPL138_ETH_TX_BUFFER_COUNT 8
40 #elif (OMAPL138_ETH_TX_BUFFER_COUNT < 1)
41  #error OMAPL138_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef OMAPL138_ETH_TX_BUFFER_SIZE
46  #define OMAPL138_ETH_TX_BUFFER_SIZE 1536
47 #elif (OMAPL138_ETH_TX_BUFFER_SIZE != 1536)
48  #error OMAPL138_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef OMAPL138_ETH_RX_BUFFER_COUNT
53  #define OMAPL138_ETH_RX_BUFFER_COUNT 8
54 #elif (OMAPL138_ETH_RX_BUFFER_COUNT < 1)
55  #error OMAPL138_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef OMAPL138_ETH_RX_BUFFER_SIZE
60  #define OMAPL138_ETH_RX_BUFFER_SIZE 1536
61 #elif (OMAPL138_ETH_RX_BUFFER_SIZE != 1536)
62  #error OMAPL138_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Channel number for the TX interrupt
66 #ifndef OMAPL138_ETH_TX_IRQ_CHANNEL
67  #define OMAPL138_ETH_TX_IRQ_CHANNEL 3
68 #elif (OMAPL138_ETH_TX_IRQ_CHANNEL < 0 || OMAPL138_ETH_TX_IRQ_CHANNEL > 31)
69  #error OMAPL138_ETH_TX_IRQ_CHANNEL parameter is not valid
70 #endif
71 
72 //Channel number for the RX interrupt
73 #ifndef OMAPL138_ETH_RX_IRQ_CHANNEL
74  #define OMAPL138_ETH_RX_IRQ_CHANNEL 3
75 #elif (OMAPL138_ETH_RX_IRQ_CHANNEL < 0 || OMAPL138_ETH_RX_IRQ_CHANNEL > 31)
76  #error OMAPL138_ETH_RX_IRQ_CHANNEL parameter is not valid
77 #endif
78 
79 //EMAC cores
80 #define EMAC_CORE0 0
81 #define EMAC_CORE1 1
82 #define EMAC_CORE2 2
83 
84 //EMAC channels
85 #define EMAC_CH0 0
86 #define EMAC_CH1 1
87 #define EMAC_CH2 2
88 #define EMAC_CH3 3
89 #define EMAC_CH4 4
90 #define EMAC_CH5 5
91 #define EMAC_CH6 6
92 #define EMAC_CH7 7
93 
94 //SYSCFG0 registers
95 #define SYSCFG0_PINMUX_R(n) HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(n))
96 #define SYSCFG0_CFGCHIP3_R HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3)
97 
98 //EMAC registers
99 #define EMAC_TXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXREVID)
100 #define EMAC_TXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCONTROL)
101 #define EMAC_TXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXTEARDOWN)
102 #define EMAC_RXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXREVID)
103 #define EMAC_RXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCONTROL)
104 #define EMAC_RXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXTEARDOWN)
105 #define EMAC_TXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATRAW)
106 #define EMAC_TXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATMASKED)
107 #define EMAC_TXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKSET)
108 #define EMAC_TXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKCLEAR)
109 #define EMAC_MACINVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINVECTOR)
110 #define EMAC_MACEOIVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACEOIVECTOR)
111 #define EMAC_RXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATRAW)
112 #define EMAC_RXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATMASKED)
113 #define EMAC_RXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKSET)
114 #define EMAC_RXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKCLEAR)
115 #define EMAC_MACINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATRAW)
116 #define EMAC_MACINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATMASKED)
117 #define EMAC_MACINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKSET)
118 #define EMAC_MACINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKCLEAR)
119 #define EMAC_RXMBPENABLE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMBPENABLE)
120 #define EMAC_RXUNICASTSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTSET)
121 #define EMAC_RXUNICASTCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTCLEAR)
122 #define EMAC_RXMAXLEN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMAXLEN)
123 #define EMAC_RXBUFFEROFFSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBUFFEROFFSET)
124 #define EMAC_RXFILTERLOWTHRESH_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERLOWTHRESH)
125 #define EMAC_RXFLOWTHRESH_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFLOWTHRESH(n))
126 #define EMAC_RXFREEBUFFER_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFREEBUFFER(n))
127 #define EMAC_MACCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONTROL)
128 #define EMAC_MACSTATUS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSTATUS)
129 #define EMAC_EMCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_EMCONTROL)
130 #define EMAC_FIFOCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FIFOCONTROL)
131 #define EMAC_MACCONFIG_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONFIG)
132 #define EMAC_SOFTRESET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_SOFTRESET)
133 #define EMAC_MACSRCADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRLO)
134 #define EMAC_MACSRCADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRHI)
135 #define EMAC_MACHASH1_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH1)
136 #define EMAC_MACHASH2_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH2)
137 #define EMAC_BOFFTEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_BOFFTEST)
138 #define EMAC_TPACETEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TPACETEST)
139 #define EMAC_RXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSE)
140 #define EMAC_TXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSE)
141 #define EMAC_RXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXGOODFRAMES)
142 #define EMAC_RXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBCASTFRAMES)
143 #define EMAC_RXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMCASTFRAMES)
144 #define EMAC_RXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSEFRAMES)
145 #define EMAC_RXCRCERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCRCERRORS)
146 #define EMAC_RXALIGNCODEERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMACEMAC_RXOVERSIZED)
147 #define EMAC_RXJABBER_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXJABBER)
148 #define EMAC_RXUNDERSIZED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNDERSIZED)
149 #define EMAC_RXFRAGMENTS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFRAGMENTS)
150 #define EMAC_RXFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERED)
151 #define EMAC_RXQOSFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXQOSFILTERED)
152 #define EMAC_RXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXOCTETS)
153 #define EMAC_TXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXGOODFRAMES)
154 #define EMAC_TXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXBCASTFRAMES)
155 #define EMAC_TXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMCASTFRAMES)
156 #define EMAC_TXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSEFRAMES)
157 #define EMAC_TXDEFERRED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXDEFERRED)
158 #define EMAC_TXCOLLISION_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCOLLISION)
159 #define EMAC_TXSINGLECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXSINGLECOLL)
160 #define EMAC_TXMULTICOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMULTICOLL)
161 #define EMAC_TXEXCESSIVECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXEXCESSIVECOLL)
162 #define EMAC_TXLATECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXLATECOLL)
163 #define EMAC_TXUNDERRUN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXUNDERRUN)
164 #define EMAC_TXCARRIERSENSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCARRIERSENSE)
165 #define EMAC_TXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXOCTETS)
166 #define EMAC_FRAME64_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME64)
167 #define EMAC_FRAME65T127_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME65T127)
168 #define EMAC_FRAME128T255_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME128T255)
169 #define EMAC_FRAME256T511_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME256T511)
170 #define EMAC_FRAME512T1023_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME512T1023)
171 #define EMAC_FRAME1024TUP_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME1024TUP)
172 #define EMAC_NETOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_NETOCTETS)
173 #define EMAC_RXSOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXSOFOVERRUNS)
174 #define EMAC_RXMOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMOFOVERRUNS)
175 #define EMAC_RXDMAOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXDMAOVERRUNS)
176 #define EMAC_MACADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRLO)
177 #define EMAC_MACADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRHI)
178 #define EMAC_MACINDEX_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINDEX)
179 #define EMAC_TXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXHDP(n))
180 #define EMAC_RXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXHDP(n))
181 #define EMAC_TXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCP(n))
182 #define EMAC_RXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCP(n))
183 
184 //EMAC control registers
185 #define EMAC_CTRL_REVID_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_REVID)
186 #define EMAC_CTRL_SOFTRESET_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_SOFTRESET)
187 #define EMAC_CTRL_INTCONTRO_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_INTCONTROL)
188 #define EMAC_CTRL_C0RXTHRESHEN_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHEN)
189 #define EMAC_CTRL_CnRXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXEN(n))
190 #define EMAC_CTRL_CnTXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnTXEN(n))
191 #define EMAC_CTRL_CnMISCEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnMISCEN(n))
192 #define EMAC_CTRL_CnRXTHRESHEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXTHRESHEN(n))
193 #define EMAC_CTRL_C0RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHSTAT)
194 #define EMAC_CTRL_C0RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXSTAT)
195 #define EMAC_CTRL_C0TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXSTAT)
196 #define EMAC_CTRL_C0MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0MISCSTAT)
197 #define EMAC_CTRL_C1RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT)
198 #define EMAC_CTRL_C1RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT)
199 #define EMAC_CTRL_C1TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXSTAT)
200 #define EMAC_CTRL_C1MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1MISCSTAT)
201 #define EMAC_CTRL_C2RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXTHRESHSTAT)
202 #define EMAC_CTRL_C2RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXSTAT)
203 #define EMAC_CTRL_C2TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXSTAT)
204 #define EMAC_CTRL_C2MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2MISCSTAT)
205 #define EMAC_CTRL_C0RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXIMAX)
206 #define EMAC_CTRL_C0TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXIMAX)
207 #define EMAC_CTRL_C1RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXIMAX)
208 #define EMAC_CTRL_C1TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXIMAX)
209 #define EMAC_CTRL_C2RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXIMAX)
210 #define EMAC_CTRL_C2TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXIMAX)
211 
212 //MDIO registers
213 #define MDIO_REVID_R HWREG(SOC_MDIO_0_REGS + MDIO_REVID)
214 #define MDIO_CONTROL_R HWREG(SOC_MDIO_0_REGS + MDIO_CONTROL)
215 #define MDIO_ALIVE_R HWREG(SOC_MDIO_0_REGS + MDIO_ALIVE)
216 #define MDIO_LINK_R HWREG(SOC_MDIO_0_REGS + MDIO_LINK)
217 #define MDIO_LINKINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTRAW)
218 #define MDIO_LINKINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTMASKED)
219 #define MDIO_USERINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTRAW)
220 #define MDIO_USERINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKED)
221 #define MDIO_USERINTMASKSET_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKSET)
222 #define MDIO_USERINTMASKCLEAR_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKCLEAR)
223 #define MDIO_USERACCESS0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS0)
224 #define MDIO_USERPHYSEL0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL0)
225 #define MDIO_USERACCESS1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS1)
226 #define MDIO_USERPHYSEL1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL1)
227 
228 //MACEOIVECTOR register
229 #define EMAC_MACEOIVECTOR_C0RXTHRESH 0x00000000
230 #define EMAC_MACEOIVECTOR_C0RX 0x00000001
231 #define EMAC_MACEOIVECTOR_C0TX 0x00000002
232 #define EMAC_MACEOIVECTOR_C0MISC 0x00000003
233 #define EMAC_MACEOIVECTOR_C1RXTHRESH 0x00000004
234 #define EMAC_MACEOIVECTOR_C1RX 0x00000005
235 #define EMAC_MACEOIVECTOR_C1TX 0x00000006
236 #define EMAC_MACEOIVECTOR_C1MISC 0x00000007
237 #define EMAC_MACEOIVECTOR_C2RXTHRESH 0x00000008
238 #define EMAC_MACEOIVECTOR_C2RX 0x00000009
239 #define EMAC_MACEOIVECTOR_C2TX 0x0000000A
240 #define EMAC_MACEOIVECTOR_C2MISC 0x0000000B
241 
242 //TX buffer descriptor flags
243 #define EMAC_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
244 #define EMAC_TX_WORD1_BUFFER_POINTER 0xFFFFFFFF
245 #define EMAC_TX_WORD2_BUFFER_OFFSET 0xFFFF0000
246 #define EMAC_TX_WORD2_BUFFER_LENGTH 0x0000FFFF
247 #define EMAC_TX_WORD3_SOP 0x80000000
248 #define EMAC_TX_WORD3_EOP 0x40000000
249 #define EMAC_TX_WORD3_OWNER 0x20000000
250 #define EMAC_TX_WORD3_EOQ 0x10000000
251 #define EMAC_TX_WORD3_TDOWNCMPLT 0x08000000
252 #define EMAC_TX_WORD3_PASSCRC 0x04000000
253 #define EMAC_TX_WORD3_PACKET_LENGTH 0x0000FFFF
254 
255 //RX buffer descriptor flags
256 #define EMAC_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
257 #define EMAC_RX_WORD1_BUFFER_POINTER 0xFFFFFFFF
258 #define EMAC_RX_WORD2_BUFFER_OFFSET 0x07FF0000
259 #define EMAC_RX_WORD2_BUFFER_LENGTH 0x000007FF
260 #define EMAC_RX_WORD3_SOP 0x80000000
261 #define EMAC_RX_WORD3_EOP 0x40000000
262 #define EMAC_RX_WORD3_OWNER 0x20000000
263 #define EMAC_RX_WORD3_EOQ 0x10000000
264 #define EMAC_RX_WORD3_TDOWNCMPLT 0x08000000
265 #define EMAC_RX_WORD3_PASSCRC 0x04000000
266 #define EMAC_RX_WORD3_ERROR_MASK 0x03FF0000
267 #define EMAC_RX_WORD3_JABBER 0x02000000
268 #define EMAC_RX_WORD3_OVERSIZE 0x01000000
269 #define EMAC_RX_WORD3_FRAGMENT 0x00800000
270 #define EMAC_RX_WORD3_UNDERSIZED 0x00400000
271 #define EMAC_RX_WORD3_CONTROL 0x00200000
272 #define EMAC_RX_WORD3_OVERRUN 0x00100000
273 #define EMAC_RX_WORD3_CODEERROR 0x00080000
274 #define EMAC_RX_WORD3_ALIGNERROR 0x00040000
275 #define EMAC_RX_WORD3_CRCERROR 0x00020000
276 #define EMAC_RX_WORD3_NOMATCH 0x00010000
277 #define EMAC_RX_WORD3_PACKET_LENGTH 0x0000FFFF
278 
279 //C++ guard
280 #ifdef __cplusplus
281 extern "C" {
282 #endif
283 
284 
285 /**
286  * @brief TX buffer descriptor
287  **/
288 
289 typedef struct _Omapl138TxBufferDesc
290 {
291  uint32_t word0;
292  uint32_t word1;
293  uint32_t word2;
294  uint32_t word3;
298 
299 
300 /**
301  * @brief RX buffer descriptor
302  **/
303 
304 typedef struct _Omapl138RxBufferDesc
305 {
306  uint32_t word0;
307  uint32_t word1;
308  uint32_t word2;
309  uint32_t word3;
313 
314 
315 //AM335x Ethernet MAC driver
316 extern const NicDriver omapl138EthDriver;
317 
318 //AM335x Ethernet MAC related functions
320 void omapl138EthInitGpio(NetInterface *interface);
321 void omapl138EthInitBufferDesc(NetInterface *interface);
322 
323 void omapl138EthTick(NetInterface *interface);
324 
325 void omapl138EthEnableIrq(NetInterface *interface);
326 void omapl138EthDisableIrq(NetInterface *interface);
327 void omapl138EthTxIrqHandler(void);
328 void omapl138EthRxIrqHandler(void);
329 void omapl138EthEventHandler(NetInterface *interface);
330 
332  const NetBuffer *buffer, size_t offset);
333 
335 
338 
339 void omapl138EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
340  uint8_t regAddr, uint16_t data);
341 
342 uint16_t omapl138EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
343  uint8_t regAddr);
344 
345 //C++ guard
346 #ifdef __cplusplus
347 }
348 #endif
349 
350 #endif
const NicDriver omapl138EthDriver
OMAP-L138 Ethernet MAC driver.
struct _Omapl138TxBufferDesc Omapl138TxBufferDesc
TX buffer descriptor.
uint8_t opcode
Definition: dns_common.h:172
RX buffer descriptor.
error_t omapl138EthInit(NetInterface *interface)
OMAP-L138 Ethernet MAC initialization.
void omapl138EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void omapl138EthTick(NetInterface *interface)
OMAP-L138 Ethernet MAC timer handler.
error_t omapl138EthReceivePacket(NetInterface *interface)
Receive a packet.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
void omapl138EthEventHandler(NetInterface *interface)
OMAP-L138 Ethernet MAC event handler.
error_t omapl138EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void omapl138EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t
Error codes.
Definition: error.h:42
void omapl138EthRxIrqHandler(void)
Ethernet MAC receive interrupt.
void omapl138EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptor lists.
#define NetInterface
Definition: net.h:36
void omapl138EthInitGpio(NetInterface *interface)
struct _Omapl138TxBufferDesc * prev
uint16_t regAddr
void omapl138EthEnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t omapl138EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Network interface controller abstraction layer.
error_t omapl138EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void omapl138EthTxIrqHandler(void)
Ethernet MAC transmit interrupt.
struct _Omapl138TxBufferDesc * next
uint8_t data[]
Definition: dtls_misc.h:176
struct _Omapl138RxBufferDesc * prev
NIC driver.
Definition: nic.h:179
struct _Omapl138RxBufferDesc * next
TX buffer descriptor.
struct _Omapl138RxBufferDesc Omapl138RxBufferDesc
RX buffer descriptor.
error_t omapl138EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.