32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "soc_omapl138.h"
37 #include "hw_syscfg0_omapl138.h"
39 #include "hw_emac_ctrl.h"
42 #include "interrupt.h"
49 #define MDIO_INPUT_CLK 75000000
51 #define MDIO_OUTPUT_CLK 1000000
57 #if defined(__ICCARM__)
60 #pragma data_alignment = 4
61 #pragma location = OMAPL138_ETH_RAM_SECTION
64 #pragma data_alignment = 4
65 #pragma location = OMAPL138_ETH_RAM_SECTION
68 #pragma data_alignment = 4
69 #pragma location = OMAPL138_ETH_RAM_CPPI_SECTION
72 #pragma data_alignment = 4
73 #pragma location = OMAPL138_ETH_RAM_CPPI_SECTION
138 TRACE_INFO(
"Initializing OMAP-L138 Ethernet MAC...\r\n");
141 nicDriverInterface = interface;
144 PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_EMAC,
145 PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
169 MDIO_CONTROL_FAULTENB | (temp & MDIO_CONTROL_CLKDIV);
172 if(interface->phyDriver != NULL)
175 error = interface->phyDriver->init(interface);
177 else if(interface->switchDriver != NULL)
180 error = interface->switchDriver->init(interface);
214 (interface->macAddr.b[1] << 8) |
215 (interface->macAddr.b[2] << 16) |
216 (interface->macAddr.b[3] << 24);
220 (interface->macAddr.b[5] << 8);
227 (interface->macAddr.b[1] << 8) |
228 (interface->macAddr.b[2] << 16) |
229 (interface->macAddr.b[3] << 24);
232 temp = interface->macAddr.b[4] |
233 (interface->macAddr.b[5] << 8);
237 (
EMAC_CH0 << EMAC_MACADDRLO_CHANNEL_SHIFT) | temp;
267 (
EMAC_CH0 << EMAC_RXMBPENABLE_RXBROADCH_SHIFT);
271 (
EMAC_CH0 << EMAC_RXMBPENABLE_RXMULTCH_SHIFT);
323 #if defined(USE_TMDSLCDK138)
327 PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_GPIO,
328 PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
332 SYSCFG_PINMUX2_PINMUX2_27_24 | SYSCFG_PINMUX2_PINMUX2_23_20 |
333 SYSCFG_PINMUX2_PINMUX2_19_16 | SYSCFG_PINMUX2_PINMUX2_15_12 |
334 SYSCFG_PINMUX2_PINMUX2_11_8 | SYSCFG_PINMUX2_PINMUX2_7_4);
337 (SYSCFG_PINMUX2_PINMUX2_31_28_MII_TXD0 << SYSCFG_PINMUX2_PINMUX2_31_28_SHIFT) |
338 (SYSCFG_PINMUX2_PINMUX2_27_24_MII_TXD1 << SYSCFG_PINMUX2_PINMUX2_27_24_SHIFT) |
339 (SYSCFG_PINMUX2_PINMUX2_23_20_MII_TXD2 << SYSCFG_PINMUX2_PINMUX2_23_20_SHIFT) |
340 (SYSCFG_PINMUX2_PINMUX2_19_16_MII_TXD3 << SYSCFG_PINMUX2_PINMUX2_19_16_SHIFT) |
341 (SYSCFG_PINMUX2_PINMUX2_15_12_MII_COL << SYSCFG_PINMUX2_PINMUX2_15_12_SHIFT) |
342 (SYSCFG_PINMUX2_PINMUX2_11_8_MII_TXCLK << SYSCFG_PINMUX2_PINMUX2_11_8_SHIFT) |
343 (SYSCFG_PINMUX2_PINMUX2_7_4_MII_TXEN << SYSCFG_PINMUX2_PINMUX2_7_4_SHIFT);
347 SYSCFG_PINMUX3_PINMUX3_27_24 | SYSCFG_PINMUX3_PINMUX3_23_20 |
348 SYSCFG_PINMUX3_PINMUX3_19_16 | SYSCFG_PINMUX3_PINMUX3_15_12 |
349 SYSCFG_PINMUX3_PINMUX3_11_8 | SYSCFG_PINMUX3_PINMUX3_7_4 |
350 SYSCFG_PINMUX3_PINMUX3_3_0);
353 (SYSCFG_PINMUX3_PINMUX3_31_28_MII_RXD0 << SYSCFG_PINMUX3_PINMUX3_31_28_SHIFT) |
354 (SYSCFG_PINMUX3_PINMUX3_27_24_MII_RXD1 << SYSCFG_PINMUX3_PINMUX3_27_24_SHIFT) |
355 (SYSCFG_PINMUX3_PINMUX3_23_20_MII_RXD2 << SYSCFG_PINMUX3_PINMUX3_23_20_SHIFT) |
356 (SYSCFG_PINMUX3_PINMUX3_19_16_MII_RXD3 << SYSCFG_PINMUX3_PINMUX3_19_16_SHIFT) |
357 (SYSCFG_PINMUX3_PINMUX3_15_12_MII_CRS << SYSCFG_PINMUX3_PINMUX3_15_12_SHIFT) |
358 (SYSCFG_PINMUX3_PINMUX3_11_8_MII_RXER << SYSCFG_PINMUX3_PINMUX3_11_8_SHIFT) |
359 (SYSCFG_PINMUX3_PINMUX3_7_4_MII_RXDV << SYSCFG_PINMUX3_PINMUX3_7_4_SHIFT) |
360 (SYSCFG_PINMUX3_PINMUX3_3_0_MII_RXCLK << SYSCFG_PINMUX3_PINMUX3_3_0_SHIFT);
364 SYSCFG_PINMUX4_PINMUX4_7_4);
367 (SYSCFG_PINMUX4_PINMUX4_7_4_MDIO_D << SYSCFG_PINMUX4_PINMUX4_7_4_SHIFT) |
368 (SYSCFG_PINMUX4_PINMUX4_3_0_MDIO_CLK << SYSCFG_PINMUX4_PINMUX4_3_0_SHIFT);
396 txBufferDesc[i].
word0 = (uint32_t) NULL;
400 txBufferDesc[i].
word2 = 0;
402 txBufferDesc[i].
word3 = 0;
405 txBufferDesc[i].
next = &txBufferDesc[nextIndex];
406 txBufferDesc[i].
prev = &txBufferDesc[prevIndex];
410 txCurBufferDesc = &txBufferDesc[0];
425 rxBufferDesc[i].
word0 = (uint32_t) &rxBufferDesc[nextIndex];
434 rxBufferDesc[i].
next = &rxBufferDesc[nextIndex];
435 rxBufferDesc[i].
prev = &rxBufferDesc[prevIndex];
439 rxCurBufferDesc = &rxBufferDesc[0];
442 rxCurBufferDesc->
prev->
word0 = (uint32_t) NULL;
458 if(interface->phyDriver != NULL)
461 interface->phyDriver->tick(interface);
463 else if(interface->switchDriver != NULL)
466 interface->switchDriver->tick(interface);
495 IntSystemEnable(SYS_INT_C0_TX);
496 IntSystemEnable(SYS_INT_C0_RX);
499 if(interface->phyDriver != NULL)
502 interface->phyDriver->enableIrq(interface);
504 else if(interface->switchDriver != NULL)
507 interface->switchDriver->enableIrq(interface);
524 IntSystemDisable(SYS_INT_C0_TX);
525 IntSystemDisable(SYS_INT_C0_RX);
528 if(interface->phyDriver != NULL)
531 interface->phyDriver->disableIrq(interface);
533 else if(interface->switchDriver != NULL)
536 interface->switchDriver->disableIrq(interface);
563 IntSystemStatusClear(SYS_INT_C0_TX);
626 IntSystemStatusClear(SYS_INT_C0_RX);
638 nicDriverInterface->nicEvent =
TRUE;
709 txCurBufferDesc->
word0 = (uint32_t) NULL;
722 txCurBufferDesc->
prev->
word0 = (uint32_t) txCurBufferDesc;
741 txCurBufferDesc = txCurBufferDesc->
next;
802 rxCurBufferDesc->
word0 = (uint32_t) NULL;
809 rxCurBufferDesc->
prev->
word0 = (uint32_t) rxCurBufferDesc;
828 rxCurBufferDesc = rxCurBufferDesc->
next;
864 uint32_t hashTable[2];
879 entry = &interface->macAddrFilter[i];
888 k = (
p[0] >> 2) ^ (
p[0] << 4);
889 k ^= (
p[1] >> 4) ^ (
p[1] << 2);
890 k ^= (
p[2] >> 6) ^
p[2];
891 k ^= (
p[3] >> 2) ^ (
p[3] << 4);
892 k ^= (
p[4] >> 4) ^ (
p[4] << 2);
893 k ^= (
p[5] >> 6) ^
p[5];
899 hashTable[k / 32] |= (1 << (k % 32));
932 config |= EMAC_MACCONTROL_RMIISPEED;
936 config &= ~EMAC_MACCONTROL_RMIISPEED;
942 config |= EMAC_MACCONTROL_FULLDUPLEX;
946 config &= ~EMAC_MACCONTROL_FULLDUPLEX;
974 temp = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE;
976 temp |= (phyAddr << MDIO_USERACCESS0_PHYADR_SHIFT) & MDIO_USERACCESS0_PHYADR;
978 temp |= (
regAddr << MDIO_USERACCESS0_REGADR_SHIFT) & MDIO_USERACCESS0_REGADR;
980 temp |=
data & MDIO_USERACCESS0_DATA;
1014 temp = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_READ;
1016 temp |= (phyAddr << MDIO_USERACCESS0_PHYADR_SHIFT) & MDIO_USERACCESS0_PHYADR;
1018 temp |= (
regAddr << MDIO_USERACCESS0_REGADR_SHIFT) & MDIO_USERACCESS0_REGADR;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
void omapl138EthTick(NetInterface *interface)
OMAP-L138 Ethernet MAC timer handler.
error_t omapl138EthInit(NetInterface *interface)
OMAP-L138 Ethernet MAC initialization.
void omapl138EthEnableIrq(NetInterface *interface)
Enable interrupts.
void omapl138EthEventHandler(NetInterface *interface)
OMAP-L138 Ethernet MAC event handler.
error_t omapl138EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void omapl138EthRxIrqHandler(void)
Ethernet MAC receive interrupt.
void omapl138EthTxIrqHandler(void)
Ethernet MAC transmit interrupt.
uint16_t omapl138EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void omapl138EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t omapl138EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t omapl138EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void omapl138EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptor lists.
void omapl138EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
const NicDriver omapl138EthDriver
OMAP-L138 Ethernet MAC driver.
__weak_func void omapl138EthInitGpio(NetInterface *interface)
GPIO configuration.
error_t omapl138EthReceivePacket(NetInterface *interface)
Receive a packet.
OMAP-L138 Ethernet MAC driver.
#define EMAC_CTRL_C0RXSTAT_R
#define OMAPL138_ETH_TX_IRQ_CHANNEL
#define EMAC_TX_WORD3_EOQ
#define EMAC_MACEOIVECTOR_C0TX
#define EMAC_RX_WORD3_SOP
#define EMAC_TX_WORD2_BUFFER_LENGTH
#define OMAPL138_ETH_RAM_CPPI_SECTION
#define EMAC_RX_WORD3_PACKET_LENGTH
#define EMAC_RXMBPENABLE_R
#define OMAPL138_ETH_RAM_SECTION
#define EMAC_RX_WORD3_OWNER
#define EMAC_TX_WORD3_OWNER
#define EMAC_RXINTMASKSET_R
#define OMAPL138_ETH_RX_IRQ_CHANNEL
#define MDIO_USERACCESS0_R
#define OMAPL138_ETH_RX_BUFFER_COUNT
#define OMAPL138_ETH_TX_BUFFER_SIZE
#define EMAC_RXBUFFEROFFSET_R
#define EMAC_TXINTMASKSET_R
#define EMAC_RXUNICASTSET_R
#define EMAC_CTRL_CnRXEN_R(n)
#define EMAC_TX_WORD3_EOP
#define EMAC_RX_WORD3_ERROR_MASK
#define EMAC_CTRL_CnTXEN_R(n)
#define EMAC_TXINTMASKCLEAR_R
#define EMAC_RX_WORD3_EOP
#define OMAPL138_ETH_RX_BUFFER_SIZE
#define EMAC_MACSRCADDRHI_R
#define SYSCFG0_CFGCHIP3_R
#define EMAC_TX_WORD3_PACKET_LENGTH
#define EMAC_MACEOIVECTOR_C0RX
#define EMAC_CTRL_C0TXSTAT_R
#define SYSCFG0_PINMUX_R(n)
#define EMAC_RXINTMASKCLEAR_R
#define EMAC_RXUNICASTCLEAR_R
#define EMAC_MACEOIVECTOR_R
#define EMAC_CTRL_SOFTRESET_R
#define EMAC_RX_WORD3_EOQ
#define EMAC_TX_WORD3_SOP
#define EMAC_MACSRCADDRLO_R
#define OMAPL138_ETH_TX_BUFFER_COUNT
#define EMAC_MACCONTROL_R
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
struct _Omapl138RxBufferDesc * prev
struct _Omapl138RxBufferDesc * next
struct _Omapl138TxBufferDesc * prev
struct _Omapl138TxBufferDesc * next
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.