ra6_eth_driver.h
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1 /**
2  * @file ra6_eth_driver.h
3  * @brief Renesas RA6M2 / RA6M3 / RA6M4 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _RA6_ETH_DRIVER_H
32 #define _RA6_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef RA6_ETH_TX_BUFFER_COUNT
39  #define RA6_ETH_TX_BUFFER_COUNT 3
40 #elif (RA6_ETH_TX_BUFFER_COUNT < 1)
41  #error RA6_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef RA6_ETH_TX_BUFFER_SIZE
46  #define RA6_ETH_TX_BUFFER_SIZE 1536
47 #elif (RA6_ETH_TX_BUFFER_SIZE != 1536)
48  #error RA6_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef RA6_ETH_RX_BUFFER_COUNT
53  #define RA6_ETH_RX_BUFFER_COUNT 6
54 #elif (RA6_ETH_RX_BUFFER_COUNT < 1)
55  #error RA6_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef RA6_ETH_RX_BUFFER_SIZE
60  #define RA6_ETH_RX_BUFFER_SIZE 1536
61 #elif (RA6_ETH_RX_BUFFER_SIZE != 1536)
62  #error RA6_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef RA6_ETH_IRQ_PRIORITY_GROUPING
67  #define RA6_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (RA6_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error RA6_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef RA6_ETH_IRQ_GROUP_PRIORITY
74  #define RA6_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (RA6_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error RA6_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef RA6_ETH_IRQ_SUB_PRIORITY
81  #define RA6_ETH_IRQ_SUB_PRIORITY 0
82 #elif (RA6_ETH_IRQ_SUB_PRIORITY < 0)
83  #error RA6_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //Name of the section where to place DMA buffers
87 #ifndef RA6_ETH_RAM_SECTION
88  #define RA6_ETH_RAM_SECTION ".ns_buffer"
89 #endif
90 
91 //Ethernet DMA controller
92 #ifndef R_ETHERC_EDMAC
93  #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
94 #endif
95 
96 //MSTPCRB15 bitfield
97 #ifndef R_MSTP_MSTPCRB_MSTPB15_Msk
98  #define R_MSTP_MSTPCRB_MSTPB15_Msk (R_MSTP_MSTPCRB_MSTPB_Msk << 15)
99 #endif
100 
101 //Transmit DMA descriptor flags
102 #define EDMAC_TD0_TACT 0x80000000
103 #define EDMAC_TD0_TDLE 0x40000000
104 #define EDMAC_TD0_TFP_SOF 0x20000000
105 #define EDMAC_TD0_TFP_EOF 0x10000000
106 #define EDMAC_TD0_TFE 0x08000000
107 #define EDMAC_TD0_TWBI 0x04000000
108 #define EDMAC_TD0_TFS_MASK 0x0000010F
109 #define EDMAC_TD0_TFS_TABT 0x00000100
110 #define EDMAC_TD0_TFS_CND 0x00000008
111 #define EDMAC_TD0_TFS_DLC 0x00000004
112 #define EDMAC_TD0_TFS_CD 0x00000002
113 #define EDMAC_TD0_TFS_TRO 0x00000001
114 #define EDMAC_TD1_TBL 0xFFFF0000
115 #define EDMAC_TD2_TBA 0xFFFFFFFF
116 
117 //Receive DMA descriptor flags
118 #define EDMAC_RD0_RACT 0x80000000
119 #define EDMAC_RD0_RDLE 0x40000000
120 #define EDMAC_RD0_RFP_SOF 0x20000000
121 #define EDMAC_RD0_RFP_EOF 0x10000000
122 #define EDMAC_RD0_RFE 0x08000000
123 #define EDMAC_RD0_RFS_MASK 0x0000039F
124 #define EDMAC_RD0_RFS_RFOF 0x00000200
125 #define EDMAC_RD0_RFS_RABT 0x00000100
126 #define EDMAC_RD0_RFS_RMAF 0x00000080
127 #define EDMAC_RD0_RFS_RRF 0x00000010
128 #define EDMAC_RD0_RFS_RTLF 0x00000008
129 #define EDMAC_RD0_RFS_RTSF 0x00000004
130 #define EDMAC_RD0_RFS_PRE 0x00000002
131 #define EDMAC_RD0_RFS_CERF 0x00000001
132 #define EDMAC_RD1_RBL 0xFFFF0000
133 #define EDMAC_RD1_RFL 0x0000FFFF
134 #define EDMAC_RD2_RBA 0xFFFFFFFF
135 
136 //C++ guard
137 #ifdef __cplusplus
138 extern "C" {
139 #endif
140 
141 
142 /**
143  * @brief Transmit DMA descriptor
144  **/
145 
146 typedef struct
147 {
148  uint32_t td0;
149  uint32_t td1;
150  uint32_t td2;
151  uint32_t padding;
153 
154 
155 /**
156  * @brief Receive DMA descriptor
157  **/
158 
159 typedef struct
160 {
161  uint32_t rd0;
162  uint32_t rd1;
163  uint32_t rd2;
164  uint32_t padding;
166 
167 
168 //RA6 Ethernet MAC driver
169 extern const NicDriver ra6EthDriver;
170 
171 //RA6 Ethernet MAC related functions
172 error_t ra6EthInit(NetInterface *interface);
173 void ra6EthInitGpio(NetInterface *interface);
174 void ra6EthInitDmaDesc(NetInterface *interface);
175 
176 void ra6EthTick(NetInterface *interface);
177 
178 void ra6EthEnableIrq(NetInterface *interface);
179 void ra6EthDisableIrq(NetInterface *interface);
180 void ra6EthEventHandler(NetInterface *interface);
181 
183  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
184 
186 
189 
190 void ra6EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
191  uint8_t regAddr, uint16_t data);
192 
193 uint16_t ra6EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
194  uint8_t regAddr);
195 
196 void ra6EthWriteSmi(uint32_t data, uint_t length);
197 uint32_t ra6EthReadSmi(uint_t length);
198 
199 //C++ guard
200 #ifdef __cplusplus
201 }
202 #endif
203 
204 #endif
unsigned int uint_t
Definition: compiler_port.h:50
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
void ra6EthTick(NetInterface *interface)
RA6 Ethernet MAC timer handler.
void ra6EthInitGpio(NetInterface *interface)
GPIO configuration.
uint16_t ra6EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void ra6EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t ra6EthReceivePacket(NetInterface *interface)
Receive a packet.
uint32_t ra6EthReadSmi(uint_t length)
SMI read operation.
void ra6EthDisableIrq(NetInterface *interface)
Disable interrupts.
void ra6EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
void ra6EthEventHandler(NetInterface *interface)
RA6 Ethernet MAC event handler.
error_t ra6EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void ra6EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void ra6EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t ra6EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
const NicDriver ra6EthDriver
RA6 Ethernet MAC driver.
error_t ra6EthInit(NetInterface *interface)
RA6 Ethernet MAC initialization.
error_t ra6EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Receive DMA descriptor.
Transmit DMA descriptor.
uint8_t length
Definition: tcp.h:368