32 #define TRACE_LEVEL NIC_TRACE_LEVEL
44 #if defined(__ICCARM__)
47 #pragma data_alignment = 32
48 #pragma location = RA6_ETH_RAM_SECTION
51 #pragma data_alignment = 32
52 #pragma location = RA6_ETH_RAM_SECTION
55 #pragma data_alignment = 16
56 #pragma location = RA6_ETH_RAM_SECTION
59 #pragma data_alignment = 16
60 #pragma location = RA6_ETH_RAM_SECTION
123 TRACE_INFO(
"Initializing RA6 Ethernet MAC...\r\n");
126 nicDriverInterface = interface;
129 R_SYSTEM->PRCR = 0xA50B;
133 R_SYSTEM->PRCR = 0xA500;
144 if(interface->phyDriver != NULL)
147 error = interface->phyDriver->init(interface);
149 else if(interface->switchDriver != NULL)
152 error = interface->switchDriver->init(interface);
172 R_ETHERC0->IPGR = 0x14;
175 R_ETHERC0->MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
176 (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
179 R_ETHERC0->MALR = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
183 (0 << R_ETHERC_EDMAC_EDMR_DL_Pos);
190 (15 << R_ETHERC_EDMAC_FDR_RFD_Pos);
197 R_ETHERC_EDMAC_TRIMD_TIS_Msk;
200 R_ETHERC0->ECSIPR = 0;
204 R_ETHERC_EDMAC_EESIPR_FRIP_Msk;
214 R_ETHERC0->ECMR |= R_ETHERC0_ECMR_TE_Msk | R_ETHERC0_ECMR_RE_Msk;
235 #if defined(USE_EK_RA6M3) || defined(USE_EK_RA6M4) || defined(USE_EK_RA6M5)
237 R_SYSTEM->PRCR = 0xA50B;
239 R_SYSTEM->VBTICTLR &= ~R_SYSTEM_VBTICTLR_VCH0INEN_Msk;
241 R_SYSTEM->PRCR = 0xA500;
244 R_PMISC->PWPR &= ~R_PMISC_PWPR_B0WI_Msk;
245 R_PMISC->PWPR |= R_PMISC_PWPR_PFSWE_Msk;
248 R_PMISC->PFENET &= ~R_PMISC_PFENET_PHYMODE0_Msk;
251 R_PFS->PORT[4].PIN[1].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
252 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (1 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
255 R_PFS->PORT[4].PIN[2].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
256 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (1 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
259 R_PFS->PORT[4].PIN[5].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
260 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
263 R_PFS->PORT[4].PIN[6].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
264 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
267 R_PFS->PORT[7].PIN[0].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
268 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
271 R_PFS->PORT[7].PIN[1].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
272 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
275 R_PFS->PORT[7].PIN[2].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
276 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
279 R_PFS->PORT[7].PIN[3].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
280 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
283 R_PFS->PORT[7].PIN[4].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
284 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
287 R_PFS->PORT[7].PIN[5].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
288 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
291 R_PMISC->PWPR &= ~R_PMISC_PWPR_PFSWE_Msk;
292 R_PMISC->PWPR |= R_PMISC_PWPR_B0WI_Msk;
295 #elif defined(USE_M13_RA6M2_EK) || defined(USE_M13_RA6M4_EK) || \
296 defined(USE_M13_RA6M5_EK)
298 R_PMISC->PWPR &= ~R_PMISC_PWPR_B0WI_Msk;
299 R_PMISC->PWPR |= R_PMISC_PWPR_PFSWE_Msk;
302 R_PMISC->PFENET &= ~R_PMISC_PFENET_PHYMODE0_Msk;
305 R_PFS->PORT[4].PIN[5].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
306 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
309 R_PFS->PORT[4].PIN[6].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
310 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
313 R_PFS->PORT[7].PIN[0].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
314 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
317 R_PFS->PORT[7].PIN[1].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
318 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
321 R_PFS->PORT[7].PIN[2].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
322 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
325 R_PFS->PORT[7].PIN[3].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
326 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
329 R_PFS->PORT[7].PIN[4].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
330 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
333 R_PFS->PORT[7].PIN[5].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
334 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
337 R_PFS->PORT[6].PIN[5].PmnPFS = R_PFS_PORT_PIN_PmnPFS_PDR_Msk;
340 R_PMISC->PWPR &= ~R_PMISC_PWPR_PFSWE_Msk;
341 R_PMISC->PWPR |= R_PMISC_PWPR_B0WI_Msk;
344 R_PORT6->PCNTR3 = (1 << 5) << R_PORT0_PCNTR3_PORR_Pos;
346 R_PORT6->PCNTR3 = (1 << 5) << R_PORT0_PCNTR3_POSR_Pos;
350 #elif defined(USE_M13_RA6M3_EK)
352 R_SYSTEM->PRCR = 0xA50B;
354 R_SYSTEM->VBTICTLR &= ~R_SYSTEM_VBTICTLR_VCH0INEN_Msk;
356 R_SYSTEM->PRCR = 0xA500;
359 R_PMISC->PWPR &= ~R_PMISC_PWPR_B0WI_Msk;
360 R_PMISC->PWPR |= R_PMISC_PWPR_PFSWE_Msk;
363 R_PMISC->PFENET &= ~R_PMISC_PFENET_PHYMODE0_Msk;
366 R_PFS->PORT[4].PIN[1].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
367 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (1 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
370 R_PFS->PORT[4].PIN[2].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
371 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (1 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
374 R_PFS->PORT[4].PIN[8].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
375 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
378 R_PFS->PORT[4].PIN[10].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
379 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
382 R_PFS->PORT[4].PIN[11].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
383 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
386 R_PFS->PORT[4].PIN[12].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
387 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
390 R_PFS->PORT[4].PIN[13].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
391 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
394 R_PFS->PORT[4].PIN[14].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
395 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
398 R_PFS->PORT[4].PIN[15].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
399 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
402 R_PMISC->PWPR &= ~R_PMISC_PWPR_PFSWE_Msk;
403 R_PMISC->PWPR |= R_PMISC_PWPR_B0WI_Msk;
472 if(interface->phyDriver != NULL)
475 interface->phyDriver->tick(interface);
477 else if(interface->switchDriver != NULL)
480 interface->switchDriver->tick(interface);
497 NVIC_EnableIRQ(EDMAC0_EINT_IRQn);
500 if(interface->phyDriver != NULL)
503 interface->phyDriver->enableIrq(interface);
505 else if(interface->switchDriver != NULL)
508 interface->switchDriver->enableIrq(interface);
525 NVIC_DisableIRQ(EDMAC0_EINT_IRQn);
528 if(interface->phyDriver != NULL)
531 interface->phyDriver->disableIrq(interface);
533 else if(interface->switchDriver != NULL)
536 interface->switchDriver->disableIrq(interface);
564 if((status & R_ETHERC_EDMAC_EESR_TWB_Msk) != 0)
578 if((status & R_ETHERC_EDMAC_EESR_FR_Msk) != 0)
584 nicDriverInterface->nicEvent =
TRUE;
590 R_ICU->IELSR[EDMAC0_EINT_IRQn] &= ~R_ICU_IELSR_IR_Msk;
782 if(interface->promiscuous)
785 R_ETHERC0->ECMR |= R_ETHERC0_ECMR_PRM_Msk;
790 R_ETHERC0->ECMR &= ~R_ETHERC0_ECMR_PRM_Msk;
793 R_ETHERC0->MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
794 (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
797 R_ETHERC0->MALR = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
800 acceptMulticast =
FALSE;
807 if(interface->macAddrFilter[i].refCount > 0)
810 acceptMulticast =
TRUE;
817 if(acceptMulticast || interface->acceptAllMulticast)
843 mode = R_ETHERC0->ECMR;
848 mode |= R_ETHERC0_ECMR_RTM_Msk;
852 mode &= ~R_ETHERC0_ECMR_RTM_Msk;
858 mode |= R_ETHERC0_ECMR_DM_Msk;
862 mode &= ~R_ETHERC0_ECMR_DM_Msk;
866 R_ETHERC0->ECMR = mode;
950 R_ETHERC0->PIR |= R_ETHERC0_PIR_MMD_Msk;
956 if((
data & 0x80000000) != 0)
958 R_ETHERC0->PIR |= R_ETHERC0_PIR_MDO_Msk;
962 R_ETHERC0->PIR &= ~R_ETHERC0_PIR_MDO_Msk;
967 R_ETHERC0->PIR |= R_ETHERC0_PIR_MDC_Msk;
970 R_ETHERC0->PIR &= ~R_ETHERC0_PIR_MDC_Msk;
989 R_ETHERC0->PIR &= ~R_ETHERC0_PIR_MMD_Msk;
998 R_ETHERC0->PIR |= R_ETHERC0_PIR_MDC_Msk;
1001 R_ETHERC0->PIR &= ~R_ETHERC0_PIR_MDC_Msk;
1005 if((R_ETHERC0->PIR & R_ETHERC0_PIR_MDI_Msk) != 0)
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void ra6EthTick(NetInterface *interface)
RA6 Ethernet MAC timer handler.
uint16_t ra6EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void ra6EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t ra6EthReceivePacket(NetInterface *interface)
Receive a packet.
uint32_t ra6EthReadSmi(uint_t length)
SMI read operation.
void ra6EthDisableIrq(NetInterface *interface)
Disable interrupts.
void ra6EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
void ra6EthEventHandler(NetInterface *interface)
RA6 Ethernet MAC event handler.
error_t ra6EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void EDMAC0_EINT_IRQHandler(void)
RA6 Ethernet MAC interrupt service routine.
void ra6EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void ra6EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t ra6EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
const NicDriver ra6EthDriver
RA6 Ethernet MAC driver.
__weak_func void ra6EthInitGpio(NetInterface *interface)
GPIO configuration.
error_t ra6EthInit(NetInterface *interface)
RA6 Ethernet MAC initialization.
error_t ra6EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Renesas RA6M2 / RA6M3 / RA6M4 Ethernet MAC driver.
#define RA6_ETH_TX_BUFFER_SIZE
#define EDMAC_RD0_RFS_MASK
#define EDMAC_RD0_RFS_RMAF
#define RA6_ETH_IRQ_GROUP_PRIORITY
#define RA6_ETH_RX_BUFFER_COUNT
#define RA6_ETH_TX_BUFFER_COUNT
#define RA6_ETH_RX_BUFFER_SIZE
#define RA6_ETH_IRQ_SUB_PRIORITY
#define RA6_ETH_RAM_SECTION
#define R_MSTP_MSTPCRB_MSTPB15_Msk
#define EDMAC_TD0_TFP_EOF
#define RA6_ETH_IRQ_PRIORITY_GROUPING
#define EDMAC_RD0_RFP_EOF
#define EDMAC_RD0_RFP_SOF
#define EDMAC_TD0_TFP_SOF
Structure describing a buffer that spans multiple chunks.