rx62n_eth_driver.h
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1 /**
2  * @file rx62n_eth_driver.h
3  * @brief Renesas RX62N Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _RX62N_ETH_DRIVER_H
30 #define _RX62N_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef RX62N_ETH_TX_BUFFER_COUNT
37  #define RX62N_ETH_TX_BUFFER_COUNT 3
38 #elif (RX62N_ETH_TX_BUFFER_COUNT < 1)
39  #error RX62N_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef RX62N_ETH_TX_BUFFER_SIZE
44  #define RX62N_ETH_TX_BUFFER_SIZE 1536
45 #elif (RX62N_ETH_TX_BUFFER_SIZE != 1536)
46  #error RX62N_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef RX62N_ETH_RX_BUFFER_COUNT
51  #define RX62N_ETH_RX_BUFFER_COUNT 6
52 #elif (RX62N_ETH_RX_BUFFER_COUNT < 1)
53  #error RX62N_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef RX62N_ETH_RX_BUFFER_SIZE
58  #define RX62N_ETH_RX_BUFFER_SIZE 1536
59 #elif (RX62N_ETH_RX_BUFFER_SIZE != 1536)
60  #error RX62N_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Ethernet interrupt priority
64 #ifndef RX62N_ETH_IRQ_PRIORITY
65  #define RX62N_ETH_IRQ_PRIORITY 2
66 #elif (RX62N_ETH_IRQ_PRIORITY < 0)
67  #error RX62N_ETH_IRQ_PRIORITY parameter is not valid
68 #endif
69 
70 //EESR register
71 #define EDMAC_EESR_TWB 0x40000000
72 #define EDMAC_EESR_TABT 0x04000000
73 #define EDMAC_EESR_RABT 0x02000000
74 #define EDMAC_EESR_RFCOF 0x01000000
75 #define EDMAC_EESR_ADE 0x00800000
76 #define EDMAC_EESR_ECI 0x00400000
77 #define EDMAC_EESR_TC 0x00200000
78 #define EDMAC_EESR_TDE 0x00100000
79 #define EDMAC_EESR_TFUF 0x00080000
80 #define EDMAC_EESR_FR 0x00040000
81 #define EDMAC_EESR_RDE 0x00020000
82 #define EDMAC_EESR_RFOF 0x00010000
83 #define EDMAC_EESR_CND 0x00000800
84 #define EDMAC_EESR_DLC 0x00000400
85 #define EDMAC_EESR_CD 0x00000200
86 #define EDMAC_EESR_TRO 0x00000100
87 #define EDMAC_EESR_RMAF 0x00000080
88 #define EDMAC_EESR_RRF 0x00000010
89 #define EDMAC_EESR_RTLF 0x00000008
90 #define EDMAC_EESR_RTSF 0x00000004
91 #define EDMAC_EESR_PRE 0x00000002
92 #define EDMAC_EESR_CERF 0x00000001
93 
94 //Transmit DMA descriptor flags
95 #define EDMAC_TD0_TACT 0x80000000
96 #define EDMAC_TD0_TDLE 0x40000000
97 #define EDMAC_TD0_TFP_SOF 0x20000000
98 #define EDMAC_TD0_TFP_EOF 0x10000000
99 #define EDMAC_TD0_TFE 0x08000000
100 #define EDMAC_TD0_TWBI 0x04000000
101 #define EDMAC_TD0_TFS_MASK 0x0000010F
102 #define EDMAC_TD0_TFS_TABT 0x00000100
103 #define EDMAC_TD0_TFS_CND 0x00000008
104 #define EDMAC_TD0_TFS_DLC 0x00000004
105 #define EDMAC_TD0_TFS_CD 0x00000002
106 #define EDMAC_TD0_TFS_TRO 0x00000001
107 #define EDMAC_TD1_TBL 0xFFFF0000
108 #define EDMAC_TD2_TBA 0xFFFFFFFF
109 
110 //Receive DMA descriptor flags
111 #define EDMAC_RD0_RACT 0x80000000
112 #define EDMAC_RD0_RDLE 0x40000000
113 #define EDMAC_RD0_RFP_SOF 0x20000000
114 #define EDMAC_RD0_RFP_EOF 0x10000000
115 #define EDMAC_RD0_RFE 0x08000000
116 #define EDMAC_RD0_RFS_MASK 0x0000039F
117 #define EDMAC_RD0_RFS_RFOF 0x00000200
118 #define EDMAC_RD0_RFS_RABT 0x00000100
119 #define EDMAC_RD0_RFS_RMAF 0x00000080
120 #define EDMAC_RD0_RFS_RRF 0x00000010
121 #define EDMAC_RD0_RFS_RTLF 0x00000008
122 #define EDMAC_RD0_RFS_RTSF 0x00000004
123 #define EDMAC_RD0_RFS_PRE 0x00000002
124 #define EDMAC_RD0_RFS_CERF 0x00000001
125 #define EDMAC_RD1_RBL 0xFFFF0000
126 #define EDMAC_RD1_RFL 0x0000FFFF
127 #define EDMAC_RD2_RBA 0xFFFFFFFF
128 
129 //Serial Management Interface
130 #define SMI_SYNC 0xFFFFFFFF
131 #define SMI_START 0x00000001
132 #define SMI_WRITE 0x00000001
133 #define SMI_READ 0x00000002
134 #define SMI_TA 0x00000002
135 
136 //C++ guard
137 #ifdef __cplusplus
138  extern "C" {
139 #endif
140 
141 
142 /**
143  * @brief Transmit DMA descriptor
144  **/
145 
146 typedef struct
147 {
148  uint32_t td0;
149  uint32_t td1;
150  uint32_t td2;
151  uint32_t padding;
153 
154 
155 /**
156  * @brief Receive DMA descriptor
157  **/
158 
159 typedef struct
160 {
161  uint32_t rd0;
162  uint32_t rd1;
163  uint32_t rd2;
164  uint32_t padding;
166 
167 
168 //RX62N Ethernet MAC driver
169 extern const NicDriver rx62nEthDriver;
170 
171 //RX62N Ethernet MAC related functions
172 error_t rx62nEthInit(NetInterface *interface);
173 void rx62nEthInitGpio(NetInterface *interface);
174 void rx62nEthInitDmaDesc(NetInterface *interface);
175 
176 void rx62nEthTick(NetInterface *interface);
177 
178 void rx62nEthEnableIrq(NetInterface *interface);
179 void rx62nEthDisableIrq(NetInterface *interface);
180 void rx62nEthEventHandler(NetInterface *interface);
181 
183  const NetBuffer *buffer, size_t offset);
184 
186 
189 
190 void rx62nEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
191 uint16_t rx62nEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
192 
193 void rx62nEthWriteSmi(uint32_t data, uint_t length);
194 uint32_t rx62nEthReadSmi(uint_t length);
195 
196 //C++ guard
197 #ifdef __cplusplus
198  }
199 #endif
200 
201 #endif
error_t rx62nEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Receive DMA descriptor.
void rx62nEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void rx62nEthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
void rx62nEthEnableIrq(NetInterface *interface)
Enable interrupts.
void rx62nEthTick(NetInterface *interface)
RX62N Ethernet MAC timer handler.
error_t rx62nEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
NIC driver.
Definition: nic.h:161
const NicDriver rx62nEthDriver
RX62N Ethernet MAC driver.
error_t rx62nEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void rx62nEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Transmit DMA descriptor.
uint16_t regAddr
void rx62nEthInitGpio(NetInterface *interface)
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
error_t rx62nEthInit(NetInterface *interface)
RX62N Ethernet MAC initialization.
error_t rx62nEthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t length
Definition: dtls_misc.h:140
void rx62nEthDisableIrq(NetInterface *interface)
Disable interrupts.
Network interface controller abstraction layer.
void rx62nEthEventHandler(NetInterface *interface)
RX62N Ethernet MAC event handler.
uint16_t rx62nEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint32_t rx62nEthReadSmi(uint_t length)
SMI read operation.