rx62n_eth_driver.c
Go to the documentation of this file.
1 /**
2  * @file rx62n_eth_driver.c
3  * @brief Renesas RX62N Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <iorx62n.h>
36 #include <intrinsics.h>
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWRX compiler?
45 #if defined(__ICCRX__)
46 
47 //Transmit buffer
48 #pragma data_alignment = 32
50 //Receive buffer
51 #pragma data_alignment = 32
53 //Transmit DMA descriptors
54 #pragma data_alignment = 32
56 //Receive DMA descriptors
57 #pragma data_alignment = 32
59 
60 //GCC compiler?
61 #else
62 
63 //Transmit buffer
65  __attribute__((aligned(32)));
66 //Receive buffer
68  __attribute__((aligned(32)));
69 //Transmit DMA descriptors
71  __attribute__((aligned(32)));
72 //Receive DMA descriptors
74  __attribute__((aligned(32)));
75 
76 #endif
77 
78 //Current transmit descriptor
79 static uint_t txIndex;
80 //Current receive descriptor
81 static uint_t rxIndex;
82 
83 
84 /**
85  * @brief RX62N Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  TRUE
106 };
107 
108 
109 /**
110  * @brief RX62N Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118 
119  //Debug message
120  TRACE_INFO("Initializing RX62N Ethernet MAC...\r\n");
121 
122  //Save underlying network interface
123  nicDriverInterface = interface;
124 
125  //Cancel EDMAC module stop state
126  MSTP(EDMAC) = 0;
127 
128  //GPIO configuration
129  rx62nEthInitGpio(interface);
130 
131  //Reset EDMAC module
132  EDMAC.EDMR.BIT.SWR = 1;
133  sleep(10);
134 
135  //PHY transceiver initialization
136  error = interface->phyDriver->init(interface);
137  //Failed to initialize PHY transceiver?
138  if(error)
139  return error;
140 
141  //Initialize DMA descriptor lists
142  rx62nEthInitDmaDesc(interface);
143 
144  //Maximum frame length that can be accepted
145  ETHERC.RFLR.LONG = RX62N_ETH_RX_BUFFER_SIZE;
146  //Set default inter packet gap (96-bit time)
147  ETHERC.IPGR.LONG = 0x14;
148 
149  //Set the upper 32 bits of the MAC address
150  ETHERC.MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
151  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
152 
153  //Set the lower 16 bits of the MAC address
154  ETHERC.MALR.BIT.MA = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
155 
156  //Set descriptor length (16 bytes)
157  EDMAC.EDMR.BIT.DL = 0;
158 
159 #ifdef _CPU_BIG_ENDIAN
160  //Select big endian mode
161  EDMAC.EDMR.BIT.DE = 0;
162 #else
163  //Select little endian mode
164  EDMAC.EDMR.BIT.DE = 1;
165 #endif
166 
167  //Use store and forward mode
168  EDMAC.TFTR.BIT.TFT = 0;
169 
170  //Set transmit FIFO size (2048 bytes)
171  EDMAC.FDR.BIT.TFD = 7;
172  //Set receive FIFO size (2048 bytes)
173  EDMAC.FDR.BIT.RFD = 7;
174 
175  //Enable continuous reception of multiple frames
176  EDMAC.RMCR.BIT.RNR = 1;
177 
178  //Accept transmit interrupt notifications
179  EDMAC.TRIMD.BIT.TIM = 0;
180  EDMAC.TRIMD.BIT.TIS = 1;
181 
182  //Disable all EDMAC interrupts
183  EDMAC.EESIPR.LONG = 0;
184  //Enable only the desired EDMAC interrupts
185  EDMAC.EESIPR.BIT.TWBIP = 1;
186  EDMAC.EESIPR.BIT.FRIP = 1;
187 
188  //Configure EDMAC interrupt priority
189  IPR(ETHER, EINT) = RX62N_ETH_IRQ_PRIORITY;
190 
191  //Enable transmission and reception
192  ETHERC.ECMR.BIT.TE = 1;
193  ETHERC.ECMR.BIT.RE = 1;
194 
195  //Instruct the DMA to poll the receive descriptor list
196  EDMAC.EDRRR.BIT.RR = 1;
197 
198  //Accept any packets from the upper layer
199  osSetEvent(&interface->nicTxEvent);
200 
201  //Successful initialization
202  return NO_ERROR;
203 }
204 
205 
206 //RDK RX62N evaluation board?
207 #if defined(USE_RDK_RX62N)
208 
209 /**
210  * @brief GPIO configuration
211  * @param[in] interface Underlying network interface
212  **/
213 
214 void rx62nEthInitGpio(NetInterface *interface)
215 {
216  //Select RMII interface mode
217  IOPORT.PFENET.BIT.PHYMODE = 0;
218 
219  //Enable Ethernet pins
220  IOPORT.PFENET.BIT.EE = 1;
221  //Disable ET_WOL pin
222  IOPORT.PFENET.BIT.ENETE0 = 0;
223  //Enable ET_LINKSTA pin
224  IOPORT.PFENET.BIT.ENETE1 = 1;
225  //Disable ET_EXOUT pin
226  IOPORT.PFENET.BIT.ENETE2 = 0;
227  //Disable ET_TX_ER pin
228  IOPORT.PFENET.BIT.ENETE3 = 0;
229 
230  //Configure ET_MDIO (PA3)
231  PORTA.ICR.BIT.B3 = 1;
232  //Configure ET_LINKSTA (PA5)
233  PORTA.ICR.BIT.B5 = 1;
234  //Configure RMII_RXD1 (PB0)
235  PORTB.ICR.BIT.B0 = 1;
236  //Configure RMII_RXD0 (PB1)
237  PORTB.ICR.BIT.B1 = 1;
238  //Configure REF50CK (PB2)
239  PORTB.ICR.BIT.B2 = 1;
240  //Configure RMII_RX_ER (PB3)
241  PORTB.ICR.BIT.B3 = 1;
242  //Configure RMII_CRS_DV (PB7)
243  PORTB.ICR.BIT.B7 = 1;
244 }
245 
246 #endif
247 
248 
249 /**
250  * @brief Initialize DMA descriptor lists
251  * @param[in] interface Underlying network interface
252  **/
253 
255 {
256  uint_t i;
257 
258  //Initialize TX descriptors
259  for(i = 0; i < RX62N_ETH_TX_BUFFER_COUNT; i++)
260  {
261  //The descriptor is initially owned by the application
262  txDmaDesc[i].td0 = 0;
263  //Transmit buffer length
264  txDmaDesc[i].td1 = 0;
265  //Transmit buffer address
266  txDmaDesc[i].td2 = (uint32_t) txBuffer[i];
267  //Clear padding field
268  txDmaDesc[i].padding = 0;
269  }
270 
271  //Mark the last descriptor entry with the TDLE flag
272  txDmaDesc[i - 1].td0 |= EDMAC_TD0_TDLE;
273  //Initialize TX descriptor index
274  txIndex = 0;
275 
276  //Initialize RX descriptors
277  for(i = 0; i < RX62N_ETH_RX_BUFFER_COUNT; i++)
278  {
279  //The descriptor is initially owned by the DMA
280  rxDmaDesc[i].rd0 = EDMAC_RD0_RACT;
281  //Receive buffer length
283  //Receive buffer address
284  rxDmaDesc[i].rd2 = (uint32_t) rxBuffer[i];
285  //Clear padding field
286  rxDmaDesc[i].padding = 0;
287  }
288 
289  //Mark the last descriptor entry with the RDLE flag
290  rxDmaDesc[i - 1].rd0 |= EDMAC_RD0_RDLE;
291  //Initialize RX descriptor index
292  rxIndex = 0;
293 
294  //Start address of the TX descriptor list
295  EDMAC.TDLAR = txDmaDesc;
296  //Start address of the RX descriptor list
297  EDMAC.RDLAR = rxDmaDesc;
298 }
299 
300 
301 /**
302  * @brief RX62N Ethernet MAC timer handler
303  *
304  * This routine is periodically called by the TCP/IP stack to
305  * handle periodic operations such as polling the link state
306  *
307  * @param[in] interface Underlying network interface
308  **/
309 
310 void rx62nEthTick(NetInterface *interface)
311 {
312  //Handle periodic operations
313  interface->phyDriver->tick(interface);
314 }
315 
316 
317 /**
318  * @brief Enable interrupts
319  * @param[in] interface Underlying network interface
320  **/
321 
323 {
324  //Enable Ethernet MAC interrupts
325  IEN(ETHER, EINT) = 1;
326  //Enable Ethernet PHY interrupts
327  interface->phyDriver->enableIrq(interface);
328 }
329 
330 
331 /**
332  * @brief Disable interrupts
333  * @param[in] interface Underlying network interface
334  **/
335 
337 {
338  //Disable Ethernet MAC interrupts
339  IEN(ETHER, EINT) = 0;
340  //Disable Ethernet PHY interrupts
341  interface->phyDriver->disableIrq(interface);
342 }
343 
344 
345 /**
346  * @brief RX62N Ethernet MAC interrupt service routine
347  **/
348 
349 #pragma vector = VECT_ETHER_EINT
350 __interrupt void rx62nEthIrqHandler(void)
351 {
352  bool_t flag;
353  uint32_t status;
354 
355  //Allow nested interrupts
356  __enable_interrupt();
357 
358  //This flag will be set if a higher priority task must be woken
359  flag = FALSE;
360 
361  //Read interrupt status register
362  status = EDMAC.EESR.LONG;
363 
364  //A packet has been transmitted?
365  if(status & EDMAC_EESR_TWB)
366  {
367  //Clear TWB interrupt flag
368  EDMAC.EESR.LONG = EDMAC_EESR_TWB;
369 
370  //Check whether the TX buffer is available for writing
371  if(!(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT))
372  {
373  //Notify the TCP/IP stack that the transmitter is ready to send
374  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
375  }
376  }
377 
378  //A packet has been received?
379  if(status & EDMAC_EESR_FR)
380  {
381  //Disable FR interrupts
382  EDMAC.EESIPR.BIT.FRIP = 0;
383 
384  //Set event flag
385  nicDriverInterface->nicEvent = TRUE;
386  //Notify the TCP/IP stack of the event
387  flag |= osSetEventFromIsr(&netEvent);
388  }
389 
390  //Interrupt service routine epilogue
391  osExitIsr(flag);
392 }
393 
394 
395 /**
396  * @brief RX62N Ethernet MAC event handler
397  * @param[in] interface Underlying network interface
398  **/
399 
401 {
402  error_t error;
403 
404  //Packet received?
405  if(EDMAC.EESR.LONG & EDMAC_EESR_FR)
406  {
407  //Clear FR interrupt flag
408  EDMAC.EESR.LONG = EDMAC_EESR_FR;
409 
410  //Process all pending packets
411  do
412  {
413  //Read incoming packet
414  error = rx62nEthReceivePacket(interface);
415 
416  //No more data in the receive buffer?
417  } while(error != ERROR_BUFFER_EMPTY);
418  }
419 
420  //Re-enable EDMAC interrupts
421  EDMAC.EESIPR.BIT.TWBIP = 1;
422  EDMAC.EESIPR.BIT.FRIP = 1;
423 }
424 
425 
426 /**
427  * @brief Send a packet
428  * @param[in] interface Underlying network interface
429  * @param[in] buffer Multi-part buffer containing the data to send
430  * @param[in] offset Offset to the first data byte
431  * @return Error code
432  **/
433 
435  const NetBuffer *buffer, size_t offset)
436 {
437  //Retrieve the length of the packet
438  size_t length = netBufferGetLength(buffer) - offset;
439 
440  //Check the frame length
442  {
443  //The transmitter can accept another packet
444  osSetEvent(&interface->nicTxEvent);
445  //Report an error
446  return ERROR_INVALID_LENGTH;
447  }
448 
449  //Make sure the current buffer is available for writing
450  if(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT)
451  return ERROR_FAILURE;
452 
453  //Copy user data to the transmit buffer
454  netBufferRead(txBuffer[txIndex], buffer, offset, length);
455 
456  //Write the number of bytes to send
457  txDmaDesc[txIndex].td1 = (length << 16) & EDMAC_TD1_TBL;
458 
459  //Check current index
460  if(txIndex < (RX62N_ETH_TX_BUFFER_COUNT - 1))
461  {
462  //Give the ownership of the descriptor to the DMA engine
463  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TFP_SOF |
465 
466  //Point to the next descriptor
467  txIndex++;
468  }
469  else
470  {
471  //Give the ownership of the descriptor to the DMA engine
472  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TDLE |
474 
475  //Wrap around
476  txIndex = 0;
477  }
478 
479  //Instruct the DMA to poll the transmit descriptor list
480  EDMAC.EDTRR.BIT.TR = 1;
481 
482  //Check whether the next buffer is available for writing
483  if(!(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT))
484  {
485  //The transmitter can accept another packet
486  osSetEvent(&interface->nicTxEvent);
487  }
488 
489  //Successful write operation
490  return NO_ERROR;
491 }
492 
493 
494 /**
495  * @brief Receive a packet
496  * @param[in] interface Underlying network interface
497  * @return Error code
498  **/
499 
501 {
502  error_t error;
503  size_t n;
504 
505  //The current buffer is available for reading?
506  if(!(rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RACT))
507  {
508  //SOF and EOF flags should be set
509  if((rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_SOF) &&
510  (rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_EOF))
511  {
512  //Make sure no error occurred
513  if(!(rxDmaDesc[rxIndex].rd0 & (EDMAC_RD0_RFS_MASK & ~EDMAC_RD0_RFS_RMAF)))
514  {
515  //Retrieve the length of the frame
516  n = rxDmaDesc[rxIndex].rd1 & EDMAC_RD1_RFL;
517  //Limit the number of data to read
519 
520  //Pass the packet to the upper layer
521  nicProcessPacket(interface, rxBuffer[rxIndex], n);
522 
523  //Valid packet received
524  error = NO_ERROR;
525  }
526  else
527  {
528  //The received packet contains an error
529  error = ERROR_INVALID_PACKET;
530  }
531  }
532  else
533  {
534  //The packet is not valid
535  error = ERROR_INVALID_PACKET;
536  }
537 
538  //Check current index
539  if(rxIndex < (RX62N_ETH_RX_BUFFER_COUNT - 1))
540  {
541  //Give the ownership of the descriptor back to the DMA
542  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT;
543  //Point to the next descriptor
544  rxIndex++;
545  }
546  else
547  {
548  //Give the ownership of the descriptor back to the DMA
549  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT | EDMAC_RD0_RDLE;
550  //Wrap around
551  rxIndex = 0;
552  }
553 
554  //Instruct the DMA to poll the receive descriptor list
555  EDMAC.EDRRR.BIT.RR = 1;
556  }
557  else
558  {
559  //No more data in the receive buffer
560  error = ERROR_BUFFER_EMPTY;
561  }
562 
563  //Return status code
564  return error;
565 }
566 
567 
568 /**
569  * @brief Configure MAC address filtering
570  * @param[in] interface Underlying network interface
571  * @return Error code
572  **/
573 
575 {
576  uint_t i;
577  bool_t acceptMulticast;
578 
579  //Debug message
580  TRACE_DEBUG("Updating MAC filter...\r\n");
581 
582  //Set the upper 32 bits of the MAC address
583  ETHERC.MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
584  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
585 
586  //Set the lower 16 bits of the MAC address
587  ETHERC.MALR.BIT.MA = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
588 
589  //This flag will be set if multicast addresses should be accepted
590  acceptMulticast = FALSE;
591 
592  //The MAC address filter contains the list of MAC addresses to accept
593  //when receiving an Ethernet frame
594  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
595  {
596  //Valid entry?
597  if(interface->macAddrFilter[i].refCount > 0)
598  {
599  //Accept multicast addresses
600  acceptMulticast = TRUE;
601  //We are done
602  break;
603  }
604  }
605 
606  //Enable the reception of multicast frames if necessary
607  if(acceptMulticast)
608  EDMAC.EESR.BIT.RMAF = 1;
609  else
610  EDMAC.EESR.BIT.RMAF = 0;
611 
612  //Successful processing
613  return NO_ERROR;
614 }
615 
616 
617 /**
618  * @brief Adjust MAC configuration parameters for proper operation
619  * @param[in] interface Underlying network interface
620  * @return Error code
621  **/
622 
624 {
625  //10BASE-T or 100BASE-TX operation mode?
626  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
627  ETHERC.ECMR.BIT.RTM = 1;
628  else
629  ETHERC.ECMR.BIT.RTM = 0;
630 
631  //Half-duplex or full-duplex mode?
632  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
633  ETHERC.ECMR.BIT.DM = 1;
634  else
635  ETHERC.ECMR.BIT.DM = 0;
636 
637  //Successful processing
638  return NO_ERROR;
639 }
640 
641 
642 /**
643  * @brief Write PHY register
644  * @param[in] opcode Access type (2 bits)
645  * @param[in] phyAddr PHY address (5 bits)
646  * @param[in] regAddr Register address (5 bits)
647  * @param[in] data Register value
648  **/
649 
650 void rx62nEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
651  uint8_t regAddr, uint16_t data)
652 {
653  //Synchronization pattern
655  //Start of frame
657  //Set up a write operation
659  //Write PHY address
660  rx62nEthWriteSmi(phyAddr, 5);
661  //Write register address
663  //Turnaround
665  //Write register value
666  rx62nEthWriteSmi(data, 16);
667  //Release MDIO
668  rx62nEthReadSmi(1);
669 }
670 
671 
672 /**
673  * @brief Read PHY register
674  * @param[in] opcode Access type (2 bits)
675  * @param[in] phyAddr PHY address (5 bits)
676  * @param[in] regAddr Register address (5 bits)
677  * @return Register value
678  **/
679 
680 uint16_t rx62nEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
681  uint8_t regAddr)
682 {
683  uint16_t data;
684 
685  //Synchronization pattern
687  //Start of frame
689  //Set up a read operation
691  //Write PHY address
692  rx62nEthWriteSmi(phyAddr, 5);
693  //Write register address
695  //Turnaround to avoid contention
696  rx62nEthReadSmi(1);
697  //Read register value
698  data = rx62nEthReadSmi(16);
699  //Force the PHY to release the MDIO pin
700  rx62nEthReadSmi(1);
701 
702  //Return PHY register contents
703  return data;
704 }
705 
706 
707 /**
708  * @brief SMI write operation
709  * @param[in] data Raw data to be written
710  * @param[in] length Number of bits to be written
711  **/
712 
714 {
715  //Skip the most significant bits since they are meaningless
716  data <<= 32 - length;
717 
718  //Configure MDIO as an output
719  ETHERC.PIR.BIT.MMD = 1;
720 
721  //Write the specified number of bits
722  while(length--)
723  {
724  //Write MDIO
725  if(data & 0x80000000)
726  ETHERC.PIR.BIT.MDO = 1;
727  else
728  ETHERC.PIR.BIT.MDO = 0;
729 
730  //Assert MDC
731  usleep(1);
732  ETHERC.PIR.BIT.MDC = 1;
733  //Deassert MDC
734  usleep(1);
735  ETHERC.PIR.BIT.MDC = 0;
736 
737  //Rotate data
738  data <<= 1;
739  }
740 }
741 
742 
743 /**
744  * @brief SMI read operation
745  * @param[in] length Number of bits to be read
746  * @return Data resulting from the MDIO read operation
747  **/
748 
750 {
751  uint32_t data = 0;
752 
753  //Configure MDIO as an input
754  ETHERC.PIR.BIT.MMD = 0;
755 
756  //Read the specified number of bits
757  while(length--)
758  {
759  //Rotate data
760  data <<= 1;
761 
762  //Assert MDC
763  ETHERC.PIR.BIT.MDC = 1;
764  usleep(1);
765  //Deassert MDC
766  ETHERC.PIR.BIT.MDC = 0;
767  usleep(1);
768 
769  //Check MDIO state
770  if(ETHERC.PIR.BIT.MDI)
771  data |= 0x00000001;
772  }
773 
774  //Return the received data
775  return data;
776 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define usleep(delay)
Definition: os_port.h:127
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
error_t rx62nEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
int bool_t
Definition: compiler_port.h:49
#define RX62N_ETH_IRQ_PRIORITY
#define EDMAC_EESR_TWB
#define EDMAC_RD0_RFS_MASK
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
#define EDMAC_RD0_RDLE
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
Renesas RX62N Ethernet MAC controller.
#define EDMAC_RD1_RFL
#define EDMAC_TD0_TACT
error_t rx62nEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define EDMAC_TD0_TFP_SOF
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
#define sleep(delay)
Definition: os_port.h:131
void rx62nEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define RX62N_ETH_RX_BUFFER_COUNT
Transmit DMA descriptor.
#define SMI_TA
Definition: nic.h:64
#define SMI_START
Definition: nic.h:60
#define RX62N_ETH_TX_BUFFER_SIZE
uint16_t rx62nEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define osExitIsr(flag)
#define EDMAC_RD0_RFP_EOF
void rx62nEthInitGpio(NetInterface *interface)
#define FALSE
Definition: os_port.h:46
#define RX62N_ETH_RX_BUFFER_SIZE
error_t
Error codes.
Definition: error.h:42
#define EDMAC_TD0_TFP_EOF
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define txBuffer
@ ERROR_INVALID_PACKET
Definition: error.h:138
#define NetInterface
Definition: net.h:36
void rx62nEthDisableIrq(NetInterface *interface)
Disable interrupts.
@ ERROR_INVALID_LENGTH
Definition: error.h:109
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
OsEvent netEvent
Definition: net.c:77
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
uint32_t rx62nEthReadSmi(uint_t length)
SMI read operation.
#define EDMAC_RD0_RACT
#define rxBuffer
#define EDMAC_RD0_RFS_RMAF
void rx62nEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define EDMAC_RD0_RFP_SOF
#define TRACE_DEBUG(...)
Definition: debug.h:106
Receive DMA descriptor.
uint16_t regAddr
#define EDMAC_RD1_RBL
#define ETH_MTU
Definition: ethernet.h:91
__interrupt void rx62nEthIrqHandler(void)
RX62N Ethernet MAC interrupt service routine.
uint8_t n
#define EDMAC_TD0_TWBI
const NicDriver rx62nEthDriver
RX62N Ethernet MAC driver.
void rx62nEthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t rx62nEthReceivePacket(NetInterface *interface)
Receive a packet.
#define EDMAC_EESR_FR
#define rxDmaDesc
void rx62nEthEventHandler(NetInterface *interface)
RX62N Ethernet MAC event handler.
#define RX62N_ETH_TX_BUFFER_COUNT
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define EDMAC_TD1_TBL
#define txDmaDesc
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:106
error_t rx62nEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define SMI_SYNC
Definition: nic.h:59
unsigned int uint_t
Definition: compiler_port.h:45
void rx62nEthTick(NetInterface *interface)
RX62N Ethernet MAC timer handler.
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
error_t rx62nEthInit(NetInterface *interface)
RX62N Ethernet MAC initialization.
#define EDMAC_TD0_TDLE
void rx62nEthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79