rx62n_eth_driver.c
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1 /**
2  * @file rx62n_eth_driver.c
3  * @brief Renesas RX62N Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <iorx62n.h>
34 #include <intrinsics.h>
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //IAR EWRX compiler?
43 #if defined(__ICCRX__)
44 
45 //Transmit buffer
46 #pragma data_alignment = 32
48 //Receive buffer
49 #pragma data_alignment = 32
51 //Transmit DMA descriptors
52 #pragma data_alignment = 32
54 //Receive DMA descriptors
55 #pragma data_alignment = 32
57 
58 //GCC compiler?
59 #else
60 
61 //Transmit buffer
63  __attribute__((aligned(32)));
64 //Receive buffer
66  __attribute__((aligned(32)));
67 //Transmit DMA descriptors
69  __attribute__((aligned(32)));
70 //Receive DMA descriptors
72  __attribute__((aligned(32)));
73 
74 #endif
75 
76 //Current transmit descriptor
77 static uint_t txIndex;
78 //Current receive descriptor
79 static uint_t rxIndex;
80 
81 
82 /**
83  * @brief RX62N Ethernet MAC driver
84  **/
85 
87 {
89  ETH_MTU,
100  TRUE,
101  TRUE,
102  TRUE,
103  TRUE
104 };
105 
106 
107 /**
108  * @brief RX62N Ethernet MAC initialization
109  * @param[in] interface Underlying network interface
110  * @return Error code
111  **/
112 
114 {
115  error_t error;
116 
117  //Debug message
118  TRACE_INFO("Initializing RX62N Ethernet MAC...\r\n");
119 
120  //Save underlying network interface
121  nicDriverInterface = interface;
122 
123  //Cancel EDMAC module stop state
124  MSTP(EDMAC) = 0;
125 
126  //GPIO configuration
127  rx62nEthInitGpio(interface);
128 
129  //Reset EDMAC module
130  EDMAC.EDMR.BIT.SWR = 1;
131  sleep(10);
132 
133  //PHY transceiver initialization
134  error = interface->phyDriver->init(interface);
135  //Failed to initialize PHY transceiver?
136  if(error)
137  return error;
138 
139  //Initialize DMA descriptor lists
140  rx62nEthInitDmaDesc(interface);
141 
142  //Maximum frame length that can be accepted
143  ETHERC.RFLR.LONG = 1518;
144  //Set default inter packet gap (96-bit time)
145  ETHERC.IPGR.LONG = 0x14;
146 
147  //Set the upper 32 bits of the MAC address
148  ETHERC.MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
149  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
150 
151  //Set the lower 16 bits of the MAC address
152  ETHERC.MALR.BIT.MA = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
153 
154  //Set descriptor length (16 bytes)
155  EDMAC.EDMR.BIT.DL = 0;
156 
157 #ifdef _CPU_BIG_ENDIAN
158  //Select big endian mode
159  EDMAC.EDMR.BIT.DE = 0;
160 #else
161  //Select little endian mode
162  EDMAC.EDMR.BIT.DE = 1;
163 #endif
164 
165  //Use store and forward mode
166  EDMAC.TFTR.BIT.TFT = 0;
167 
168  //Set transmit FIFO size (2048 bytes)
169  EDMAC.FDR.BIT.TFD = 7;
170  //Set receive FIFO size (2048 bytes)
171  EDMAC.FDR.BIT.RFD = 7;
172 
173  //Enable continuous reception of multiple frames
174  EDMAC.RMCR.BIT.RNR = 1;
175 
176  //Accept transmit interrupt notifications
177  EDMAC.TRIMD.BIT.TIM = 0;
178  EDMAC.TRIMD.BIT.TIS = 1;
179 
180  //Disable all EDMAC interrupts
181  EDMAC.EESIPR.LONG = 0;
182  //Enable only the desired EDMAC interrupts
183  EDMAC.EESIPR.BIT.TWBIP = 1;
184  EDMAC.EESIPR.BIT.FRIP = 1;
185 
186  //Configure EDMAC interrupt priority
187  IPR(ETHER, EINT) = RX62N_ETH_IRQ_PRIORITY;
188 
189  //Enable transmission and reception
190  ETHERC.ECMR.BIT.TE = 1;
191  ETHERC.ECMR.BIT.RE = 1;
192 
193  //Instruct the DMA to poll the receive descriptor list
194  EDMAC.EDRRR.BIT.RR = 1;
195 
196  //Accept any packets from the upper layer
197  osSetEvent(&interface->nicTxEvent);
198 
199  //Successful initialization
200  return NO_ERROR;
201 }
202 
203 
204 //RDK RX62N evaluation board?
205 #if defined(USE_RDK_RX62N)
206 
207 /**
208  * @brief GPIO configuration
209  * @param[in] interface Underlying network interface
210  **/
211 
212 void rx62nEthInitGpio(NetInterface *interface)
213 {
214  //Select RMII interface mode
215  IOPORT.PFENET.BIT.PHYMODE = 0;
216 
217  //Enable Ethernet pins
218  IOPORT.PFENET.BIT.EE = 1;
219  //Disable ET_WOL pin
220  IOPORT.PFENET.BIT.ENETE0 = 0;
221  //Enable ET_LINKSTA pin
222  IOPORT.PFENET.BIT.ENETE1 = 1;
223  //Disable ET_EXOUT pin
224  IOPORT.PFENET.BIT.ENETE2 = 0;
225  //Disable ET_TX_ER pin
226  IOPORT.PFENET.BIT.ENETE3 = 0;
227 
228  //Configure ET_MDIO (PA3)
229  PORTA.ICR.BIT.B3 = 1;
230  //Configure ET_LINKSTA (PA5)
231  PORTA.ICR.BIT.B5 = 1;
232  //Configure RMII_RXD1 (PB0)
233  PORTB.ICR.BIT.B0 = 1;
234  //Configure RMII_RXD0 (PB1)
235  PORTB.ICR.BIT.B1 = 1;
236  //Configure REF50CK (PB2)
237  PORTB.ICR.BIT.B2 = 1;
238  //Configure RMII_RX_ER (PB3)
239  PORTB.ICR.BIT.B3 = 1;
240  //Configure RMII_CRS_DV (PB7)
241  PORTB.ICR.BIT.B7 = 1;
242 }
243 
244 #endif
245 
246 
247 /**
248  * @brief Initialize DMA descriptor lists
249  * @param[in] interface Underlying network interface
250  **/
251 
253 {
254  uint_t i;
255 
256  //Initialize TX descriptors
257  for(i = 0; i < RX62N_ETH_TX_BUFFER_COUNT; i++)
258  {
259  //The descriptor is initially owned by the application
260  txDmaDesc[i].td0 = 0;
261  //Transmit buffer length
262  txDmaDesc[i].td1 = 0;
263  //Transmit buffer address
264  txDmaDesc[i].td2 = (uint32_t) txBuffer[i];
265  //Clear padding field
266  txDmaDesc[i].padding = 0;
267  }
268 
269  //Mark the last descriptor entry with the TDLE flag
270  txDmaDesc[i - 1].td0 |= EDMAC_TD0_TDLE;
271  //Initialize TX descriptor index
272  txIndex = 0;
273 
274  //Initialize RX descriptors
275  for(i = 0; i < RX62N_ETH_RX_BUFFER_COUNT; i++)
276  {
277  //The descriptor is initially owned by the DMA
278  rxDmaDesc[i].rd0 = EDMAC_RD0_RACT;
279  //Receive buffer length
281  //Receive buffer address
282  rxDmaDesc[i].rd2 = (uint32_t) rxBuffer[i];
283  //Clear padding field
284  rxDmaDesc[i].padding = 0;
285  }
286 
287  //Mark the last descriptor entry with the RDLE flag
288  rxDmaDesc[i - 1].rd0 |= EDMAC_RD0_RDLE;
289  //Initialize RX descriptor index
290  rxIndex = 0;
291 
292  //Start address of the TX descriptor list
293  EDMAC.TDLAR = txDmaDesc;
294  //Start address of the RX descriptor list
295  EDMAC.RDLAR = rxDmaDesc;
296 }
297 
298 
299 /**
300  * @brief RX62N Ethernet MAC timer handler
301  *
302  * This routine is periodically called by the TCP/IP stack to
303  * handle periodic operations such as polling the link state
304  *
305  * @param[in] interface Underlying network interface
306  **/
307 
308 void rx62nEthTick(NetInterface *interface)
309 {
310  //Handle periodic operations
311  interface->phyDriver->tick(interface);
312 }
313 
314 
315 /**
316  * @brief Enable interrupts
317  * @param[in] interface Underlying network interface
318  **/
319 
321 {
322  //Enable Ethernet MAC interrupts
323  IEN(ETHER, EINT) = 1;
324  //Enable Ethernet PHY interrupts
325  interface->phyDriver->enableIrq(interface);
326 }
327 
328 
329 /**
330  * @brief Disable interrupts
331  * @param[in] interface Underlying network interface
332  **/
333 
335 {
336  //Disable Ethernet MAC interrupts
337  IEN(ETHER, EINT) = 0;
338  //Disable Ethernet PHY interrupts
339  interface->phyDriver->disableIrq(interface);
340 }
341 
342 
343 /**
344  * @brief RX62N Ethernet MAC interrupt service routine
345  **/
346 
347 #pragma vector = VECT_ETHER_EINT
348 __interrupt void rx62nEthIrqHandler(void)
349 {
350  bool_t flag;
351  uint32_t status;
352 
353  //Allow nested interrupts
354  __enable_interrupt();
355 
356  //This flag will be set if a higher priority task must be woken
357  flag = FALSE;
358 
359  //Read interrupt status register
360  status = EDMAC.EESR.LONG;
361 
362  //A packet has been transmitted?
363  if(status & EDMAC_EESR_TWB)
364  {
365  //Clear TWB interrupt flag
366  EDMAC.EESR.LONG = EDMAC_EESR_TWB;
367 
368  //Check whether the TX buffer is available for writing
369  if(!(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT))
370  {
371  //Notify the TCP/IP stack that the transmitter is ready to send
372  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
373  }
374  }
375 
376  //A packet has been received?
377  if(status & EDMAC_EESR_FR)
378  {
379  //Disable FR interrupts
380  EDMAC.EESIPR.BIT.FRIP = 0;
381 
382  //Set event flag
383  nicDriverInterface->nicEvent = TRUE;
384  //Notify the TCP/IP stack of the event
385  flag |= osSetEventFromIsr(&netEvent);
386  }
387 
388  //Leave interrupt service routine
389  osExitIsr(flag);
390 }
391 
392 
393 /**
394  * @brief RX62N Ethernet MAC event handler
395  * @param[in] interface Underlying network interface
396  **/
397 
399 {
400  error_t error;
401 
402  //Packet received?
403  if(EDMAC.EESR.LONG & EDMAC_EESR_FR)
404  {
405  //Clear FR interrupt flag
406  EDMAC.EESR.LONG = EDMAC_EESR_FR;
407 
408  //Process all pending packets
409  do
410  {
411  //Read incoming packet
412  error = rx62nEthReceivePacket(interface);
413 
414  //No more data in the receive buffer?
415  } while(error != ERROR_BUFFER_EMPTY);
416  }
417 
418  //Re-enable EDMAC interrupts
419  EDMAC.EESIPR.BIT.TWBIP = 1;
420  EDMAC.EESIPR.BIT.FRIP = 1;
421 }
422 
423 
424 /**
425  * @brief Send a packet
426  * @param[in] interface Underlying network interface
427  * @param[in] buffer Multi-part buffer containing the data to send
428  * @param[in] offset Offset to the first data byte
429  * @return Error code
430  **/
431 
433  const NetBuffer *buffer, size_t offset)
434 {
435  //Retrieve the length of the packet
436  size_t length = netBufferGetLength(buffer) - offset;
437 
438  //Check the frame length
440  {
441  //The transmitter can accept another packet
442  osSetEvent(&interface->nicTxEvent);
443  //Report an error
444  return ERROR_INVALID_LENGTH;
445  }
446 
447  //Make sure the current buffer is available for writing
448  if(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT)
449  return ERROR_FAILURE;
450 
451  //Copy user data to the transmit buffer
452  netBufferRead(txBuffer[txIndex], buffer, offset, length);
453 
454  //Write the number of bytes to send
455  txDmaDesc[txIndex].td1 = (length << 16) & EDMAC_TD1_TBL;
456 
457  //Check current index
458  if(txIndex < (RX62N_ETH_TX_BUFFER_COUNT - 1))
459  {
460  //Give the ownership of the descriptor to the DMA engine
461  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TFP_SOF |
463 
464  //Point to the next descriptor
465  txIndex++;
466  }
467  else
468  {
469  //Give the ownership of the descriptor to the DMA engine
470  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TDLE |
472 
473  //Wrap around
474  txIndex = 0;
475  }
476 
477  //Instruct the DMA to poll the transmit descriptor list
478  EDMAC.EDTRR.BIT.TR = 1;
479 
480  //Check whether the next buffer is available for writing
481  if(!(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT))
482  {
483  //The transmitter can accept another packet
484  osSetEvent(&interface->nicTxEvent);
485  }
486 
487  //Successful write operation
488  return NO_ERROR;
489 }
490 
491 
492 /**
493  * @brief Receive a packet
494  * @param[in] interface Underlying network interface
495  * @return Error code
496  **/
497 
499 {
500  error_t error;
501  size_t n;
502 
503  //The current buffer is available for reading?
504  if(!(rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RACT))
505  {
506  //SOF and EOF flags should be set
507  if((rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_SOF) &&
508  (rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_EOF))
509  {
510  //Make sure no error occurred
511  if(!(rxDmaDesc[rxIndex].rd0 & (EDMAC_RD0_RFS_MASK & ~EDMAC_RD0_RFS_RMAF)))
512  {
513  //Retrieve the length of the frame
514  n = rxDmaDesc[rxIndex].rd1 & EDMAC_RD1_RFL;
515  //Limit the number of data to read
517 
518  //Pass the packet to the upper layer
519  nicProcessPacket(interface, rxBuffer[rxIndex], n);
520 
521  //Valid packet received
522  error = NO_ERROR;
523  }
524  else
525  {
526  //The received packet contains an error
527  error = ERROR_INVALID_PACKET;
528  }
529  }
530  else
531  {
532  //The packet is not valid
533  error = ERROR_INVALID_PACKET;
534  }
535 
536  //Check current index
537  if(rxIndex < (RX62N_ETH_RX_BUFFER_COUNT - 1))
538  {
539  //Give the ownership of the descriptor back to the DMA
540  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT;
541  //Point to the next descriptor
542  rxIndex++;
543  }
544  else
545  {
546  //Give the ownership of the descriptor back to the DMA
547  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT | EDMAC_RD0_RDLE;
548  //Wrap around
549  rxIndex = 0;
550  }
551 
552  //Instruct the DMA to poll the receive descriptor list
553  EDMAC.EDRRR.BIT.RR = 1;
554  }
555  else
556  {
557  //No more data in the receive buffer
558  error = ERROR_BUFFER_EMPTY;
559  }
560 
561  //Return status code
562  return error;
563 }
564 
565 
566 /**
567  * @brief Configure MAC address filtering
568  * @param[in] interface Underlying network interface
569  * @return Error code
570  **/
571 
573 {
574  uint_t i;
575  bool_t acceptMulticast;
576 
577  //This flag will be set if multicast addresses should be accepted
578  acceptMulticast = FALSE;
579 
580  //The MAC address filter contains the list of MAC addresses to accept
581  //when receiving an Ethernet frame
582  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
583  {
584  //Valid entry?
585  if(interface->macAddrFilter[i].refCount > 0)
586  {
587  //Accept multicast addresses
588  acceptMulticast = TRUE;
589  //We are done
590  break;
591  }
592  }
593 
594  //Enable the reception of multicast frames if necessary
595  if(acceptMulticast)
596  EDMAC.EESR.BIT.RMAF = 1;
597  else
598  EDMAC.EESR.BIT.RMAF = 0;
599 
600  //Successful processing
601  return NO_ERROR;
602 }
603 
604 
605 /**
606  * @brief Adjust MAC configuration parameters for proper operation
607  * @param[in] interface Underlying network interface
608  * @return Error code
609  **/
610 
612 {
613  //10BASE-T or 100BASE-TX operation mode?
614  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
615  ETHERC.ECMR.BIT.RTM = 1;
616  else
617  ETHERC.ECMR.BIT.RTM = 0;
618 
619  //Half-duplex or full-duplex mode?
620  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
621  ETHERC.ECMR.BIT.DM = 1;
622  else
623  ETHERC.ECMR.BIT.DM = 0;
624 
625  //Successful processing
626  return NO_ERROR;
627 }
628 
629 
630 /**
631  * @brief Write PHY register
632  * @param[in] phyAddr PHY address
633  * @param[in] regAddr Register address
634  * @param[in] data Register value
635  **/
636 
637 void rx62nEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
638 {
639  //Synchronization pattern
641  //Start of frame
643  //Set up a write operation
645  //Write PHY address
646  rx62nEthWriteSmi(phyAddr, 5);
647  //Write register address
649  //Turnaround
651  //Write register value
652  rx62nEthWriteSmi(data, 16);
653  //Release MDIO
654  rx62nEthReadSmi(1);
655 }
656 
657 
658 /**
659  * @brief Read PHY register
660  * @param[in] phyAddr PHY address
661  * @param[in] regAddr Register address
662  * @return Register value
663  **/
664 
665 uint16_t rx62nEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
666 {
667  uint16_t data;
668 
669  //Synchronization pattern
671  //Start of frame
673  //Set up a read operation
675  //Write PHY address
676  rx62nEthWriteSmi(phyAddr, 5);
677  //Write register address
679  //Turnaround to avoid contention
680  rx62nEthReadSmi(1);
681  //Read register value
682  data = rx62nEthReadSmi(16);
683  //Force the PHY to release the MDIO pin
684  rx62nEthReadSmi(1);
685 
686  //Return PHY register contents
687  return data;
688 }
689 
690 
691 /**
692  * @brief SMI write operation
693  * @param[in] data Raw data to be written
694  * @param[in] length Number of bits to be written
695  **/
696 
698 {
699  //Skip the most significant bits since they are meaningless
700  data <<= 32 - length;
701 
702  //Configure MDIO as an output
703  ETHERC.PIR.BIT.MMD = 1;
704 
705  //Write the specified number of bits
706  while(length--)
707  {
708  //Write MDIO
709  if(data & 0x80000000)
710  ETHERC.PIR.BIT.MDO = 1;
711  else
712  ETHERC.PIR.BIT.MDO = 0;
713 
714  //Assert MDC
715  usleep(1);
716  ETHERC.PIR.BIT.MDC = 1;
717  //Deassert MDC
718  usleep(1);
719  ETHERC.PIR.BIT.MDC = 0;
720 
721  //Rotate data
722  data <<= 1;
723  }
724 }
725 
726 
727 /**
728  * @brief SMI read operation
729  * @param[in] length Number of bits to be read
730  * @return Data resulting from the MDIO read operation
731  **/
732 
734 {
735  uint32_t data = 0;
736 
737  //Configure MDIO as an input
738  ETHERC.PIR.BIT.MMD = 0;
739 
740  //Read the specified number of bits
741  while(length--)
742  {
743  //Rotate data
744  data <<= 1;
745 
746  //Assert MDC
747  ETHERC.PIR.BIT.MDC = 1;
748  usleep(1);
749  //Deassert MDC
750  ETHERC.PIR.BIT.MDC = 0;
751  usleep(1);
752 
753  //Check MDIO state
754  if(ETHERC.PIR.BIT.MDI)
755  data |= 0x00000001;
756  }
757 
758  //Return the received data
759  return data;
760 }
#define txDmaDesc
Receive DMA descriptor.
#define EDMAC_TD0_TWBI
#define RX62N_ETH_RX_BUFFER_SIZE
TCP/IP stack core.
void rx62nEthTick(NetInterface *interface)
RX62N Ethernet MAC timer handler.
Debugging facilities.
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
Generic error code.
Definition: error.h:43
#define rxDmaDesc
error_t rx62nEthInit(NetInterface *interface)
RX62N Ethernet MAC initialization.
#define txBuffer
Renesas RX62N Ethernet MAC controller.
#define sleep(delay)
Definition: os_port.h:126
#define EDMAC_TD1_TBL
error_t rx62nEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
__interrupt void rx62nEthIrqHandler(void)
RX62N Ethernet MAC interrupt service routine.
#define EDMAC_RD0_RFS_MASK
#define EDMAC_TD0_TFP_SOF
#define EDMAC_RD0_RFP_SOF
#define EDMAC_RD1_RFL
#define EDMAC_RD1_RBL
#define EDMAC_EESR_TWB
#define EDMAC_EESR_FR
#define RX62N_ETH_RX_BUFFER_COUNT
error_t rx62nEthReceivePacket(NetInterface *interface)
Receive a packet.
#define SMI_START
#define EDMAC_TD0_TDLE
#define SMI_SYNC
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define RX62N_ETH_TX_BUFFER_COUNT
#define usleep(delay)
Definition: os_port.h:122
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void rx62nEthEventHandler(NetInterface *interface)
RX62N Ethernet MAC event handler.
Transmit DMA descriptor.
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint16_t rx62nEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void rx62nEthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
error_t rx62nEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define EDMAC_TD0_TFP_EOF
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
void rx62nEthInitGpio(NetInterface *interface)
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void rx62nEthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t
Error codes.
Definition: error.h:40
#define EDMAC_RD0_RDLE
void rx62nEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
unsigned int uint_t
Definition: compiler_port.h:43
#define EDMAC_TD0_TACT
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint32_t rx62nEthReadSmi(uint_t length)
SMI read operation.
error_t rx62nEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define SMI_TA
#define SMI_READ
#define SMI_WRITE
#define osExitIsr(flag)
#define RX62N_ETH_IRQ_PRIORITY
#define EDMAC_RD0_RFS_RMAF
#define EDMAC_RD0_RACT
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define RX62N_ETH_TX_BUFFER_SIZE
#define FALSE
Definition: os_port.h:44
#define EDMAC_RD0_RFP_EOF
int bool_t
Definition: compiler_port.h:47
const NicDriver rx62nEthDriver
RX62N Ethernet MAC driver.
void rx62nEthEnableIrq(NetInterface *interface)
Enable interrupts.
void rx62nEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.