rx62n_eth_driver.c
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1 /**
2  * @file rx62n_eth_driver.c
3  * @brief Renesas RX62N Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.8
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <iorx62n.h>
36 #include <intrinsics.h>
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWRX compiler?
45 #if defined(__ICCRX__)
46 
47 //Transmit buffer
48 #pragma data_alignment = 32
50 //Receive buffer
51 #pragma data_alignment = 32
53 //Transmit DMA descriptors
54 #pragma data_alignment = 32
56 //Receive DMA descriptors
57 #pragma data_alignment = 32
59 
60 //GCC compiler?
61 #else
62 
63 //Transmit buffer
65  __attribute__((aligned(32)));
66 //Receive buffer
68  __attribute__((aligned(32)));
69 //Transmit DMA descriptors
71  __attribute__((aligned(32)));
72 //Receive DMA descriptors
74  __attribute__((aligned(32)));
75 
76 #endif
77 
78 //Current transmit descriptor
79 static uint_t txIndex;
80 //Current receive descriptor
81 static uint_t rxIndex;
82 
83 
84 /**
85  * @brief RX62N Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  TRUE
106 };
107 
108 
109 /**
110  * @brief RX62N Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118 
119  //Debug message
120  TRACE_INFO("Initializing RX62N Ethernet MAC...\r\n");
121 
122  //Save underlying network interface
123  nicDriverInterface = interface;
124 
125  //Cancel EDMAC module stop state
126  MSTP(EDMAC) = 0;
127 
128  //GPIO configuration
129  rx62nEthInitGpio(interface);
130 
131  //Reset EDMAC module
132  EDMAC.EDMR.BIT.SWR = 1;
133  sleep(10);
134 
135  //Valid Ethernet PHY or switch driver?
136  if(interface->phyDriver != NULL)
137  {
138  //Ethernet PHY initialization
139  error = interface->phyDriver->init(interface);
140  }
141  else if(interface->switchDriver != NULL)
142  {
143  //Ethernet switch initialization
144  error = interface->switchDriver->init(interface);
145  }
146  else
147  {
148  //The interface is not properly configured
149  error = ERROR_FAILURE;
150  }
151 
152  //Any error to report?
153  if(error)
154  {
155  return error;
156  }
157 
158  //Initialize DMA descriptor lists
159  rx62nEthInitDmaDesc(interface);
160 
161  //Maximum frame length that can be accepted
162  ETHERC.RFLR.LONG = RX62N_ETH_RX_BUFFER_SIZE;
163  //Set default inter packet gap (96-bit time)
164  ETHERC.IPGR.LONG = 0x14;
165 
166  //Set the upper 32 bits of the MAC address
167  ETHERC.MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
168  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
169 
170  //Set the lower 16 bits of the MAC address
171  ETHERC.MALR.BIT.MA = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
172 
173  //Set descriptor length (16 bytes)
174  EDMAC.EDMR.BIT.DL = 0;
175 
176 #ifdef _CPU_BIG_ENDIAN
177  //Select big endian mode
178  EDMAC.EDMR.BIT.DE = 0;
179 #else
180  //Select little endian mode
181  EDMAC.EDMR.BIT.DE = 1;
182 #endif
183 
184  //Use store and forward mode
185  EDMAC.TFTR.BIT.TFT = 0;
186 
187  //Set transmit FIFO size (2048 bytes)
188  EDMAC.FDR.BIT.TFD = 7;
189  //Set receive FIFO size (2048 bytes)
190  EDMAC.FDR.BIT.RFD = 7;
191 
192  //Enable continuous reception of multiple frames
193  EDMAC.RMCR.BIT.RNR = 1;
194 
195  //Accept transmit interrupt notifications
196  EDMAC.TRIMD.BIT.TIM = 0;
197  EDMAC.TRIMD.BIT.TIS = 1;
198 
199  //Disable all EDMAC interrupts
200  EDMAC.EESIPR.LONG = 0;
201  //Enable only the desired EDMAC interrupts
202  EDMAC.EESIPR.BIT.TWBIP = 1;
203  EDMAC.EESIPR.BIT.FRIP = 1;
204 
205  //Configure EDMAC interrupt priority
206  IPR(ETHER, EINT) = RX62N_ETH_IRQ_PRIORITY;
207 
208  //Enable transmission and reception
209  ETHERC.ECMR.BIT.TE = 1;
210  ETHERC.ECMR.BIT.RE = 1;
211 
212  //Instruct the DMA to poll the receive descriptor list
213  EDMAC.EDRRR.BIT.RR = 1;
214 
215  //Accept any packets from the upper layer
216  osSetEvent(&interface->nicTxEvent);
217 
218  //Successful initialization
219  return NO_ERROR;
220 }
221 
222 
223 //RDK RX62N evaluation board?
224 #if defined(USE_RDK_RX62N)
225 
226 /**
227  * @brief GPIO configuration
228  * @param[in] interface Underlying network interface
229  **/
230 
231 void rx62nEthInitGpio(NetInterface *interface)
232 {
233  //Select RMII interface mode
234  IOPORT.PFENET.BIT.PHYMODE = 0;
235 
236  //Enable Ethernet pins
237  IOPORT.PFENET.BIT.EE = 1;
238  //Disable ET_WOL pin
239  IOPORT.PFENET.BIT.ENETE0 = 0;
240  //Enable ET_LINKSTA pin
241  IOPORT.PFENET.BIT.ENETE1 = 1;
242  //Disable ET_EXOUT pin
243  IOPORT.PFENET.BIT.ENETE2 = 0;
244  //Disable ET_TX_ER pin
245  IOPORT.PFENET.BIT.ENETE3 = 0;
246 
247  //Configure ET_MDIO (PA3)
248  PORTA.ICR.BIT.B3 = 1;
249  //Configure ET_LINKSTA (PA5)
250  PORTA.ICR.BIT.B5 = 1;
251  //Configure RMII_RXD1 (PB0)
252  PORTB.ICR.BIT.B0 = 1;
253  //Configure RMII_RXD0 (PB1)
254  PORTB.ICR.BIT.B1 = 1;
255  //Configure REF50CK (PB2)
256  PORTB.ICR.BIT.B2 = 1;
257  //Configure RMII_RX_ER (PB3)
258  PORTB.ICR.BIT.B3 = 1;
259  //Configure RMII_CRS_DV (PB7)
260  PORTB.ICR.BIT.B7 = 1;
261 }
262 
263 #endif
264 
265 
266 /**
267  * @brief Initialize DMA descriptor lists
268  * @param[in] interface Underlying network interface
269  **/
270 
272 {
273  uint_t i;
274 
275  //Initialize TX descriptors
276  for(i = 0; i < RX62N_ETH_TX_BUFFER_COUNT; i++)
277  {
278  //The descriptor is initially owned by the application
279  txDmaDesc[i].td0 = 0;
280  //Transmit buffer length
281  txDmaDesc[i].td1 = 0;
282  //Transmit buffer address
283  txDmaDesc[i].td2 = (uint32_t) txBuffer[i];
284  //Clear padding field
285  txDmaDesc[i].padding = 0;
286  }
287 
288  //Mark the last descriptor entry with the TDLE flag
289  txDmaDesc[i - 1].td0 |= EDMAC_TD0_TDLE;
290  //Initialize TX descriptor index
291  txIndex = 0;
292 
293  //Initialize RX descriptors
294  for(i = 0; i < RX62N_ETH_RX_BUFFER_COUNT; i++)
295  {
296  //The descriptor is initially owned by the DMA
297  rxDmaDesc[i].rd0 = EDMAC_RD0_RACT;
298  //Receive buffer length
300  //Receive buffer address
301  rxDmaDesc[i].rd2 = (uint32_t) rxBuffer[i];
302  //Clear padding field
303  rxDmaDesc[i].padding = 0;
304  }
305 
306  //Mark the last descriptor entry with the RDLE flag
307  rxDmaDesc[i - 1].rd0 |= EDMAC_RD0_RDLE;
308  //Initialize RX descriptor index
309  rxIndex = 0;
310 
311  //Start address of the TX descriptor list
312  EDMAC.TDLAR = txDmaDesc;
313  //Start address of the RX descriptor list
314  EDMAC.RDLAR = rxDmaDesc;
315 }
316 
317 
318 /**
319  * @brief RX62N Ethernet MAC timer handler
320  *
321  * This routine is periodically called by the TCP/IP stack to handle periodic
322  * operations such as polling the link state
323  *
324  * @param[in] interface Underlying network interface
325  **/
326 
327 void rx62nEthTick(NetInterface *interface)
328 {
329  //Valid Ethernet PHY or switch driver?
330  if(interface->phyDriver != NULL)
331  {
332  //Handle periodic operations
333  interface->phyDriver->tick(interface);
334  }
335  else if(interface->switchDriver != NULL)
336  {
337  //Handle periodic operations
338  interface->switchDriver->tick(interface);
339  }
340  else
341  {
342  //Just for sanity
343  }
344 }
345 
346 
347 /**
348  * @brief Enable interrupts
349  * @param[in] interface Underlying network interface
350  **/
351 
353 {
354  //Enable Ethernet MAC interrupts
355  IEN(ETHER, EINT) = 1;
356 
357  //Valid Ethernet PHY or switch driver?
358  if(interface->phyDriver != NULL)
359  {
360  //Enable Ethernet PHY interrupts
361  interface->phyDriver->enableIrq(interface);
362  }
363  else if(interface->switchDriver != NULL)
364  {
365  //Enable Ethernet switch interrupts
366  interface->switchDriver->enableIrq(interface);
367  }
368  else
369  {
370  //Just for sanity
371  }
372 }
373 
374 
375 /**
376  * @brief Disable interrupts
377  * @param[in] interface Underlying network interface
378  **/
379 
381 {
382  //Disable Ethernet MAC interrupts
383  IEN(ETHER, EINT) = 0;
384 
385  //Valid Ethernet PHY or switch driver?
386  if(interface->phyDriver != NULL)
387  {
388  //Disable Ethernet PHY interrupts
389  interface->phyDriver->disableIrq(interface);
390  }
391  else if(interface->switchDriver != NULL)
392  {
393  //Disable Ethernet switch interrupts
394  interface->switchDriver->disableIrq(interface);
395  }
396  else
397  {
398  //Just for sanity
399  }
400 }
401 
402 
403 /**
404  * @brief RX62N Ethernet MAC interrupt service routine
405  **/
406 
407 #pragma vector = VECT_ETHER_EINT
408 __interrupt void rx62nEthIrqHandler(void)
409 {
410  bool_t flag;
411  uint32_t status;
412 
413  //Allow nested interrupts
414  __enable_interrupt();
415 
416  //This flag will be set if a higher priority task must be woken
417  flag = FALSE;
418 
419  //Read interrupt status register
420  status = EDMAC.EESR.LONG;
421 
422  //Packet transmitted?
423  if((status & EDMAC_EESR_TWB) != 0)
424  {
425  //Clear TWB interrupt flag
426  EDMAC.EESR.LONG = EDMAC_EESR_TWB;
427 
428  //Check whether the TX buffer is available for writing
429  if((txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT) == 0)
430  {
431  //Notify the TCP/IP stack that the transmitter is ready to send
432  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
433  }
434  }
435 
436  //Packet received?
437  if((status & EDMAC_EESR_FR) != 0)
438  {
439  //Disable FR interrupts
440  EDMAC.EESIPR.BIT.FRIP = 0;
441 
442  //Set event flag
443  nicDriverInterface->nicEvent = TRUE;
444  //Notify the TCP/IP stack of the event
445  flag |= osSetEventFromIsr(&netEvent);
446  }
447 
448  //Interrupt service routine epilogue
449  osExitIsr(flag);
450 }
451 
452 
453 /**
454  * @brief RX62N Ethernet MAC event handler
455  * @param[in] interface Underlying network interface
456  **/
457 
459 {
460  error_t error;
461 
462  //Packet received?
463  if((EDMAC.EESR.LONG & EDMAC_EESR_FR) != 0)
464  {
465  //Clear FR interrupt flag
466  EDMAC.EESR.LONG = EDMAC_EESR_FR;
467 
468  //Process all pending packets
469  do
470  {
471  //Read incoming packet
472  error = rx62nEthReceivePacket(interface);
473 
474  //No more data in the receive buffer?
475  } while(error != ERROR_BUFFER_EMPTY);
476  }
477 
478  //Re-enable EDMAC interrupts
479  EDMAC.EESIPR.BIT.TWBIP = 1;
480  EDMAC.EESIPR.BIT.FRIP = 1;
481 }
482 
483 
484 /**
485  * @brief Send a packet
486  * @param[in] interface Underlying network interface
487  * @param[in] buffer Multi-part buffer containing the data to send
488  * @param[in] offset Offset to the first data byte
489  * @param[in] ancillary Additional options passed to the stack along with
490  * the packet
491  * @return Error code
492  **/
493 
495  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
496 {
497  //Retrieve the length of the packet
498  size_t length = netBufferGetLength(buffer) - offset;
499 
500  //Check the frame length
502  {
503  //The transmitter can accept another packet
504  osSetEvent(&interface->nicTxEvent);
505  //Report an error
506  return ERROR_INVALID_LENGTH;
507  }
508 
509  //Make sure the current buffer is available for writing
510  if((txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT) != 0)
511  {
512  return ERROR_FAILURE;
513  }
514 
515  //Copy user data to the transmit buffer
516  netBufferRead(txBuffer[txIndex], buffer, offset, length);
517 
518  //Write the number of bytes to send
519  txDmaDesc[txIndex].td1 = (length << 16) & EDMAC_TD1_TBL;
520 
521  //Check current index
522  if(txIndex < (RX62N_ETH_TX_BUFFER_COUNT - 1))
523  {
524  //Give the ownership of the descriptor to the DMA engine
525  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TFP_SOF |
527 
528  //Point to the next descriptor
529  txIndex++;
530  }
531  else
532  {
533  //Give the ownership of the descriptor to the DMA engine
534  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TDLE |
536 
537  //Wrap around
538  txIndex = 0;
539  }
540 
541  //Instruct the DMA to poll the transmit descriptor list
542  EDMAC.EDTRR.BIT.TR = 1;
543 
544  //Check whether the next buffer is available for writing
545  if((txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT) == 0)
546  {
547  //The transmitter can accept another packet
548  osSetEvent(&interface->nicTxEvent);
549  }
550 
551  //Successful write operation
552  return NO_ERROR;
553 }
554 
555 
556 /**
557  * @brief Receive a packet
558  * @param[in] interface Underlying network interface
559  * @return Error code
560  **/
561 
563 {
564  error_t error;
565  size_t n;
566  NetRxAncillary ancillary;
567 
568  //The current buffer is available for reading?
569  if((rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RACT) == 0)
570  {
571  //SOF and EOF flags should be set
572  if((rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_SOF) != 0 &&
573  (rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_EOF) != 0)
574  {
575  //Make sure no error occurred
576  if(!(rxDmaDesc[rxIndex].rd0 & (EDMAC_RD0_RFS_MASK & ~EDMAC_RD0_RFS_RMAF)))
577  {
578  //Retrieve the length of the frame
579  n = rxDmaDesc[rxIndex].rd1 & EDMAC_RD1_RFL;
580  //Limit the number of data to read
582 
583  //Additional options can be passed to the stack along with the packet
584  ancillary = NET_DEFAULT_RX_ANCILLARY;
585 
586  //Pass the packet to the upper layer
587  nicProcessPacket(interface, rxBuffer[rxIndex], n, &ancillary);
588 
589  //Valid packet received
590  error = NO_ERROR;
591  }
592  else
593  {
594  //The received packet contains an error
595  error = ERROR_INVALID_PACKET;
596  }
597  }
598  else
599  {
600  //The packet is not valid
601  error = ERROR_INVALID_PACKET;
602  }
603 
604  //Check current index
605  if(rxIndex < (RX62N_ETH_RX_BUFFER_COUNT - 1))
606  {
607  //Give the ownership of the descriptor back to the DMA
608  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT;
609  //Point to the next descriptor
610  rxIndex++;
611  }
612  else
613  {
614  //Give the ownership of the descriptor back to the DMA
615  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT | EDMAC_RD0_RDLE;
616  //Wrap around
617  rxIndex = 0;
618  }
619 
620  //Instruct the DMA to poll the receive descriptor list
621  EDMAC.EDRRR.BIT.RR = 1;
622  }
623  else
624  {
625  //No more data in the receive buffer
626  error = ERROR_BUFFER_EMPTY;
627  }
628 
629  //Return status code
630  return error;
631 }
632 
633 
634 /**
635  * @brief Configure MAC address filtering
636  * @param[in] interface Underlying network interface
637  * @return Error code
638  **/
639 
641 {
642  uint_t i;
643  bool_t acceptMulticast;
644 
645  //Debug message
646  TRACE_DEBUG("Updating MAC filter...\r\n");
647 
648  //Set the upper 32 bits of the MAC address
649  ETHERC.MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
650  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
651 
652  //Set the lower 16 bits of the MAC address
653  ETHERC.MALR.BIT.MA = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
654 
655  //This flag will be set if multicast addresses should be accepted
656  acceptMulticast = FALSE;
657 
658  //The MAC address filter contains the list of MAC addresses to accept
659  //when receiving an Ethernet frame
660  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
661  {
662  //Valid entry?
663  if(interface->macAddrFilter[i].refCount > 0)
664  {
665  //Accept multicast addresses
666  acceptMulticast = TRUE;
667  //We are done
668  break;
669  }
670  }
671 
672  //Enable the reception of multicast frames if necessary
673  if(acceptMulticast)
674  {
675  EDMAC.EESR.BIT.RMAF = 1;
676  }
677  else
678  {
679  EDMAC.EESR.BIT.RMAF = 0;
680  }
681 
682  //Successful processing
683  return NO_ERROR;
684 }
685 
686 
687 /**
688  * @brief Adjust MAC configuration parameters for proper operation
689  * @param[in] interface Underlying network interface
690  * @return Error code
691  **/
692 
694 {
695  //10BASE-T or 100BASE-TX operation mode?
696  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
697  {
698  ETHERC.ECMR.BIT.RTM = 1;
699  }
700  else
701  {
702  ETHERC.ECMR.BIT.RTM = 0;
703  }
704 
705  //Half-duplex or full-duplex mode?
706  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
707  {
708  ETHERC.ECMR.BIT.DM = 1;
709  }
710  else
711  {
712  ETHERC.ECMR.BIT.DM = 0;
713  }
714 
715  //Successful processing
716  return NO_ERROR;
717 }
718 
719 
720 /**
721  * @brief Write PHY register
722  * @param[in] opcode Access type (2 bits)
723  * @param[in] phyAddr PHY address (5 bits)
724  * @param[in] regAddr Register address (5 bits)
725  * @param[in] data Register value
726  **/
727 
728 void rx62nEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
729  uint8_t regAddr, uint16_t data)
730 {
731  //Synchronization pattern
733  //Start of frame
735  //Set up a write operation
737  //Write PHY address
738  rx62nEthWriteSmi(phyAddr, 5);
739  //Write register address
741  //Turnaround
743  //Write register value
744  rx62nEthWriteSmi(data, 16);
745  //Release MDIO
746  rx62nEthReadSmi(1);
747 }
748 
749 
750 /**
751  * @brief Read PHY register
752  * @param[in] opcode Access type (2 bits)
753  * @param[in] phyAddr PHY address (5 bits)
754  * @param[in] regAddr Register address (5 bits)
755  * @return Register value
756  **/
757 
758 uint16_t rx62nEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
759  uint8_t regAddr)
760 {
761  uint16_t data;
762 
763  //Synchronization pattern
765  //Start of frame
767  //Set up a read operation
769  //Write PHY address
770  rx62nEthWriteSmi(phyAddr, 5);
771  //Write register address
773  //Turnaround to avoid contention
774  rx62nEthReadSmi(1);
775  //Read register value
776  data = rx62nEthReadSmi(16);
777  //Force the PHY to release the MDIO pin
778  rx62nEthReadSmi(1);
779 
780  //Return PHY register contents
781  return data;
782 }
783 
784 
785 /**
786  * @brief SMI write operation
787  * @param[in] data Raw data to be written
788  * @param[in] length Number of bits to be written
789  **/
790 
792 {
793  //Skip the most significant bits since they are meaningless
794  data <<= 32 - length;
795 
796  //Configure MDIO as an output
797  ETHERC.PIR.BIT.MMD = 1;
798 
799  //Write the specified number of bits
800  while(length--)
801  {
802  //Write MDIO
803  if((data & 0x80000000) != 0)
804  {
805  ETHERC.PIR.BIT.MDO = 1;
806  }
807  else
808  {
809  ETHERC.PIR.BIT.MDO = 0;
810  }
811 
812  //Assert MDC
813  usleep(1);
814  ETHERC.PIR.BIT.MDC = 1;
815  //Deassert MDC
816  usleep(1);
817  ETHERC.PIR.BIT.MDC = 0;
818 
819  //Rotate data
820  data <<= 1;
821  }
822 }
823 
824 
825 /**
826  * @brief SMI read operation
827  * @param[in] length Number of bits to be read
828  * @return Data resulting from the MDIO read operation
829  **/
830 
832 {
833  uint32_t data = 0;
834 
835  //Configure MDIO as an input
836  ETHERC.PIR.BIT.MMD = 0;
837 
838  //Read the specified number of bits
839  while(length--)
840  {
841  //Rotate data
842  data <<= 1;
843 
844  //Assert MDC
845  ETHERC.PIR.BIT.MDC = 1;
846  usleep(1);
847  //Deassert MDC
848  ETHERC.PIR.BIT.MDC = 0;
849  usleep(1);
850 
851  //Check MDIO state
852  if(ETHERC.PIR.BIT.MDI)
853  {
854  data |= 0x01;
855  }
856  }
857 
858  //Return the received data
859  return data;
860 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define EDMAC_RD0_RACT
uint8_t length
Definition: coap_common.h:190
#define usleep(delay)
Definition: os_port.h:247
uint8_t opcode
Definition: dns_common.h:172
error_t rx62nEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
int bool_t
Definition: compiler_port.h:49
#define RX62N_ETH_IRQ_PRIORITY
#define netEvent
Definition: net_legacy.h:267
uint8_t data[]
Definition: ethernet.h:209
error_t rx62nEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
Renesas RX62N Ethernet MAC driver.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:88
#define TRUE
Definition: os_port.h:50
#define sleep(delay)
Definition: os_port.h:251
void rx62nEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define RX62N_ETH_RX_BUFFER_COUNT
Transmit DMA descriptor.
#define SMI_TA
Definition: nic.h:67
#define EDMAC_EESR_FR
#define SMI_START
Definition: nic.h:63
#define RX62N_ETH_TX_BUFFER_SIZE
uint16_t rx62nEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:388
#define EDMAC_RD0_RFP_SOF
#define osExitIsr(flag)
#define EDMAC_TD0_TFP_EOF
void rx62nEthInitGpio(NetInterface *interface)
#define EDMAC_TD0_TFP_SOF
#define EDMAC_RD0_RFP_EOF
#define FALSE
Definition: os_port.h:46
#define RX62N_ETH_RX_BUFFER_SIZE
error_t
Error codes.
Definition: error.h:42
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:96
Generic error code.
Definition: error.h:45
#define EDMAC_RD0_RFS_MASK
#define txBuffer
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
void rx62nEthDisableIrq(NetInterface *interface)
Disable interrupts.
#define NetTxAncillary
Definition: net_misc.h:36
#define EDMAC_TD0_TWBI
#define TRACE_INFO(...)
Definition: debug.h:95
#define EDMAC_RD1_RFL
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
uint32_t rx62nEthReadSmi(uint_t length)
SMI read operation.
#define rxBuffer
void rx62nEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define TRACE_DEBUG(...)
Definition: debug.h:107
Receive DMA descriptor.
#define EDMAC_RD1_RBL
uint16_t regAddr
#define EDMAC_TD0_TACT
#define ETH_MTU
Definition: ethernet.h:105
__interrupt void rx62nEthIrqHandler(void)
RX62N Ethernet MAC interrupt service routine.
uint8_t n
const NicDriver rx62nEthDriver
RX62N Ethernet MAC driver.
void rx62nEthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t rx62nEthReceivePacket(NetInterface *interface)
Receive a packet.
#define EDMAC_RD0_RDLE
#define rxDmaDesc
void rx62nEthEventHandler(NetInterface *interface)
RX62N Ethernet MAC event handler.
#define RX62N_ETH_TX_BUFFER_COUNT
#define EDMAC_TD0_TDLE
#define EDMAC_EESR_TWB
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define txDmaDesc
error_t rx62nEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define EDMAC_RD0_RFS_RMAF
#define SMI_SYNC
Definition: nic.h:62
unsigned int uint_t
Definition: compiler_port.h:45
void rx62nEthTick(NetInterface *interface)
RX62N Ethernet MAC timer handler.
TCP/IP stack core.
NIC driver.
Definition: nic.h:257
error_t rx62nEthInit(NetInterface *interface)
RX62N Ethernet MAC initialization.
void rx62nEthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define EDMAC_TD1_TBL
Ethernet interface.
Definition: nic.h:82