rza1_eth_driver.h
Go to the documentation of this file.
1 /**
2  * @file rza1_eth_driver.h
3  * @brief Renesas RZ/A1 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _RZA1_ETH_DRIVER_H
30 #define _RZA1_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef RZA1_ETH_TX_BUFFER_COUNT
37  #define RZA1_ETH_TX_BUFFER_COUNT 8
38 #elif (RZA1_ETH_TX_BUFFER_COUNT < 1)
39  #error RZA1_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef RZA1_ETH_TX_BUFFER_SIZE
44  #define RZA1_ETH_TX_BUFFER_SIZE 1536
45 #elif (RZA1_ETH_TX_BUFFER_SIZE != 1536)
46  #error RZA1_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef RZA1_ETH_RX_BUFFER_COUNT
51  #define RZA1_ETH_RX_BUFFER_COUNT 8
52 #elif (RZA1_ETH_RX_BUFFER_COUNT < 1)
53  #error RZA1_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef RZA1_ETH_RX_BUFFER_SIZE
58  #define RZA1_ETH_RX_BUFFER_SIZE 1536
59 #elif (RZA1_ETH_RX_BUFFER_SIZE != 1536)
60  #error RZA1_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Ethernet interrupt priority
64 #ifndef RZA1_ETH_IRQ_PRIORITY
65  #define RZA1_ETH_IRQ_PRIORITY 25
66 #elif (RZA1_ETH_IRQ_PRIORITY < 0)
67  #error RZA1_ETH_IRQ_PRIORITY parameter is not valid
68 #endif
69 
70 //ARSTR register
71 #define ETHER_ARSTR_ARST 0x00000001
72 
73 //ECMR0 register
74 #define ETH_ECMR0_TRCCM 0x04000000
75 #define ETH_ECMR0_RCSC 0x00800000
76 #define ETH_ECMR0_DPAD 0x00200000
77 #define ETH_ECMR0_RZPF 0x00100000
78 #define ETH_ECMR0_ZPF 0x00080000
79 #define ETH_ECMR0_PFR 0x00040000
80 #define ETH_ECMR0_RXF 0x00020000
81 #define ETH_ECMR0_TXF 0x00010000
82 #define ETH_ECMR0_MCT 0x00002000
83 #define ETH_ECMR0_RE 0x00000040
84 #define ETH_ECMR0_TE 0x00000020
85 #define ETH_ECMR0_DM 0x00000002
86 #define ETH_ECMR0_PRM 0x00000001
87 
88 //PIR0 register
89 #define ETHER_PIR0_MDI 0x00000008
90 #define ETHER_PIR0_MDO 0x00000004
91 #define ETHER_PIR0_MMD 0x00000002
92 #define ETHER_PIR0_MDC 0x00000001
93 
94 //TSU_ADSBSY register
95 #define ETHER_TSU_ADSBSY_ADSBSY 0x00000001
96 
97 //EDSR0 register
98 #define ETHER_EDSR0_ENT 0x00000002
99 #define ETHER_EDSR0_ENR 0x00000001
100 
101 //EDMR0 register
102 #define ETHER_EDMR0_DE 0x00000040
103 #define ETHER_EDMR0_DL 0x00000030
104 #define ETHER_EDMR0_SWRT 0x00000002
105 #define ETHER_EDMR0_SWRR 0x00000001
106 
107 #define ETHER_EDMR0_DL_16 0x00000000
108 #define ETHER_EDMR0_DL_32 0x00000010
109 #define ETHER_EDMR0_DL_64 0x00000020
110 
111 //EDTRR0 register
112 #define ETHER_EDTRR0_TR 0x00000003
113 
114 //EDRRR0 register
115 #define ETHER_EDRRR0_RR 0x00000001
116 
117 //EESR0 register
118 #define ETHER_EESR0_TWB 0xC0000000
119 #define ETHER_EESR0_TC1 0x20000000
120 #define ETHER_EESR0_TUC 0x10000000
121 #define ETHER_EESR0_ROC 0x08000000
122 #define ETHER_EESR0_TABT 0x04000000
123 #define ETHER_EESR0_RABT 0x02000000
124 #define ETHER_EESR0_RFCOF 0x01000000
125 #define ETHER_EESR0_ECI 0x00400000
126 #define ETHER_EESR0_TC0 0x00200000
127 #define ETHER_EESR0_TDE 0x00100000
128 #define ETHER_EESR0_TFUF 0x00080000
129 #define ETHER_EESR0_FR 0x00040000
130 #define ETHER_EESR0_RDE 0x00020000
131 #define ETHER_EESR0_RFOF 0x00010000
132 #define ETHER_EESR0_RMAF 0x00000080
133 #define ETHER_EESR0_RRF 0x00000010
134 #define ETHER_EESR0_RTLF 0x00000008
135 #define ETHER_EESR0_RTSF 0x00000004
136 #define ETHER_EESR0_PRE 0x00000002
137 #define ETHER_EESR0_CERF 0x00000001
138 
139 //EESIPR0 register
140 #define ETHER_EESIPR0_TWBIP 0xC0000000
141 #define ETHER_EESIPR0_TC1IP 0x20000000
142 #define ETHER_EESIPR0_TUCIP 0x10000000
143 #define ETHER_EESIPR0_ROCIP 0x08000000
144 #define ETHER_EESIPR0_TABTIP 0x04000000
145 #define ETHER_EESIPR0_RABTIP 0x02000000
146 #define ETHER_EESIPR0_RFCOFIP 0x01000000
147 #define ETHER_EESIPR0_ECIIP 0x00400000
148 #define ETHER_EESIPR0_TC0IP 0x00200000
149 #define ETHER_EESIPR0_TDEIP 0x00100000
150 #define ETHER_EESIPR0_TFUFIP 0x00080000
151 #define ETHER_EESIPR0_FRIP 0x00040000
152 #define ETHER_EESIPR0_RDEIP 0x00020000
153 #define ETHER_EESIPR0_RFOFIP 0x00010000
154 #define ETHER_EESIPR0_RMAFIP 0x00000080
155 #define ETHER_EESIPR0_RRFIP 0x00000010
156 #define ETHER_EESIPR0_RTLFIP 0x00000008
157 #define ETHER_EESIPR0_RTSFIP 0x00000004
158 #define ETHER_EESIPR0_PREIP 0x00000002
159 #define ETHER_EESIPR0_CERFIP 0x00000001
160 
161 //TDFFR0 register
162 #define ETHER_TDFFR_TDLF 0x00000001
163 
164 //RDFFR0 register
165 #define ETHER_RDFFR0_RDLF 0x00000001
166 
167 //FDR0 register
168 #define ETHER_FDR0_TFD 0x00000700
169 #define ETHER_FDR0_RFD 0X0000001F
170 
171 #define ETHER_FDR0_TFD_2048 0x00000700
172 #define ETHER_FDR0_RFD_2048 0x00000007
173 
174 //RMCR0 register
175 #define ETHER_RMCR0_RNC 0x00000001
176 
177 //FCFTR register
178 #define ETHER_FCFTR0_RFF 0x001F0000
179 #define ETHER_FCFTR0_RFD 0x000000FF
180 
181 #define ETHER_FCFTR0_RFF_8 0x00070000
182 #define ETHER_FCFTR0_RFD_2048 0x00000007
183 
184 //Transmit DMA descriptor flags
185 #define ETHER_TD0_TACT 0x80000000
186 #define ETHER_TD0_TDLE 0x40000000
187 #define ETHER_TD0_TFP_SOF 0x20000000
188 #define ETHER_TD0_TFP_EOF 0x10000000
189 #define ETHER_TD0_TFE 0x08000000
190 #define ETHER_TD0_TWBI 0x04000000
191 #define ETHER_TD0_TFS_MASK 0x00000300
192 #define ETHER_TD0_TFS_TUC 0x00000200
193 #define ETHER_TD0_TFS_TABT 0x00000100
194 #define ETHER_TD1_TDL 0xFFFF0000
195 #define ETHER_TD2_TBA 0xFFFFFFFF
196 
197 //Receive DMA descriptor flags
198 #define ETHER_RD0_RACT 0x80000000
199 #define ETHER_RD0_RDLE 0x40000000
200 #define ETHER_RD0_RFP_SOF 0x20000000
201 #define ETHER_RD0_RFP_EOF 0x10000000
202 #define ETHER_RD0_RFE 0x08000000
203 #define ETHER_RD0_RCSE 0x04000000
204 #define ETHER_RD0_RFS_MASK 0x02DF0000
205 #define ETHER_RD0_RFS_RFOF 0x02000000
206 #define ETHER_RD0_RFS_RMAF 0x00800000
207 #define ETHER_RD0_RFS_RUAF 0x00400000
208 #define ETHER_RD0_RFS_RRF 0x00100000
209 #define ETHER_RD0_RFS_RTLF 0x00080000
210 #define ETHER_RD0_RFS_RTSF 0x00040000
211 #define ETHER_RD0_RFS_PRE 0x00020000
212 #define ETHER_RD0_RFS_CERF 0x00010000
213 #define ETHER_RD0_RCS 0x0000FFFF
214 #define ETHER_RD1_RBL 0xFFFF0000
215 #define ETHER_RD1_RDL 0x0000FFFF
216 #define ETHER_RD2_RBA 0xFFFFFFFF
217 
218 //Serial Management Interface
219 #define SMI_SYNC 0xFFFFFFFF
220 #define SMI_START 0x00000001
221 #define SMI_WRITE 0x00000001
222 #define SMI_READ 0x00000002
223 #define SMI_TA 0x00000002
224 
225 //C++ guard
226 #ifdef __cplusplus
227  extern "C" {
228 #endif
229 
230 
231 /**
232  * @brief Transmit DMA descriptor
233  **/
234 
235 typedef struct
236 {
237  uint32_t td0;
238  uint32_t td1;
239  uint32_t td2;
240  uint32_t padding;
241 } Rza1TxDmaDesc;
242 
243 
244 /**
245  * @brief Receive DMA descriptor
246  **/
247 
248 typedef struct
249 {
250  uint32_t rd0;
251  uint32_t rd1;
252  uint32_t rd2;
253  uint32_t padding;
254 } Rza1RxDmaDesc;
255 
256 
257 //RZ/A1 Ethernet MAC driver
258 extern const NicDriver rza1EthDriver;
259 
260 //RZ/A1 Ethernet MAC related functions
261 error_t rza1EthInit(NetInterface *interface);
262 void rza1EthInitGpio(NetInterface *interface);
263 void rza1EthInitDmaDesc(NetInterface *interface);
264 
265 void rza1EthTick(NetInterface *interface);
266 
267 void rza1EthEnableIrq(NetInterface *interface);
268 void rza1EthDisableIrq(NetInterface *interface);
269 void rza1EthIrqHandler(uint32_t intSense);
270 void rza1EthEventHandler(NetInterface *interface);
271 
273  const NetBuffer *buffer, size_t offset);
274 
276 
279 
280 void rza1EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
281 uint16_t rza1EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
282 
283 void rza1EthWriteSmi(uint32_t data, uint_t length);
284 uint32_t rza1EthReadSmi(uint_t length);
285 
286 //C++ guard
287 #ifdef __cplusplus
288  }
289 #endif
290 
291 #endif
void rza1EthEnableIrq(NetInterface *interface)
Enable interrupts.
void rza1EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
void rza1EthInitGpio(NetInterface *interface)
void rza1EthIrqHandler(uint32_t intSense)
RZ/A1 Ethernet MAC interrupt service routine.
void rza1EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t rza1EthInit(NetInterface *interface)
RZ/A1 Ethernet MAC initialization.
error_t rza1EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void rza1EthTick(NetInterface *interface)
RZ/A1 Ethernet MAC timer handler.
error_t rza1EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void rza1EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
error_t rza1EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
const NicDriver rza1EthDriver
RZ/A1 Ethernet MAC driver.
uint16_t regAddr
void rza1EthEventHandler(NetInterface *interface)
RZ/A1 Ethernet MAC event handler.
uint32_t rza1EthReadSmi(uint_t length)
SMI read operation.
error_t
Error codes.
Definition: error.h:40
error_t rza1EthReceivePacket(NetInterface *interface)
Receive a packet.
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
Receive DMA descriptor.
uint16_t rza1EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint8_t length
Definition: dtls_misc.h:140
void rza1EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
Network interface controller abstraction layer.
Transmit DMA descriptor.