rza1_eth_driver.h
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1 /**
2  * @file rza1_eth_driver.h
3  * @brief Renesas RZ/A1 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _RZA1_ETH_DRIVER_H
32 #define _RZA1_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef RZA1_ETH_TX_BUFFER_COUNT
39  #define RZA1_ETH_TX_BUFFER_COUNT 8
40 #elif (RZA1_ETH_TX_BUFFER_COUNT < 1)
41  #error RZA1_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef RZA1_ETH_TX_BUFFER_SIZE
46  #define RZA1_ETH_TX_BUFFER_SIZE 1536
47 #elif (RZA1_ETH_TX_BUFFER_SIZE != 1536)
48  #error RZA1_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef RZA1_ETH_RX_BUFFER_COUNT
53  #define RZA1_ETH_RX_BUFFER_COUNT 8
54 #elif (RZA1_ETH_RX_BUFFER_COUNT < 1)
55  #error RZA1_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef RZA1_ETH_RX_BUFFER_SIZE
60  #define RZA1_ETH_RX_BUFFER_SIZE 1536
61 #elif (RZA1_ETH_RX_BUFFER_SIZE != 1536)
62  #error RZA1_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Ethernet interrupt priority
66 #ifndef RZA1_ETH_IRQ_PRIORITY
67  #define RZA1_ETH_IRQ_PRIORITY 25
68 #elif (RZA1_ETH_IRQ_PRIORITY < 0)
69  #error RZA1_ETH_IRQ_PRIORITY parameter is not valid
70 #endif
71 
72 //ARSTR register
73 #define ETHER_ARSTR_ARST 0x00000001
74 
75 //ECMR0 register
76 #define ETH_ECMR0_TRCCM 0x04000000
77 #define ETH_ECMR0_RCSC 0x00800000
78 #define ETH_ECMR0_DPAD 0x00200000
79 #define ETH_ECMR0_RZPF 0x00100000
80 #define ETH_ECMR0_ZPF 0x00080000
81 #define ETH_ECMR0_PFR 0x00040000
82 #define ETH_ECMR0_RXF 0x00020000
83 #define ETH_ECMR0_TXF 0x00010000
84 #define ETH_ECMR0_MCT 0x00002000
85 #define ETH_ECMR0_RE 0x00000040
86 #define ETH_ECMR0_TE 0x00000020
87 #define ETH_ECMR0_DM 0x00000002
88 #define ETH_ECMR0_PRM 0x00000001
89 
90 //PIR0 register
91 #define ETHER_PIR0_MDI 0x00000008
92 #define ETHER_PIR0_MDO 0x00000004
93 #define ETHER_PIR0_MMD 0x00000002
94 #define ETHER_PIR0_MDC 0x00000001
95 
96 //TSU_ADSBSY register
97 #define ETHER_TSU_ADSBSY_ADSBSY 0x00000001
98 
99 //EDSR0 register
100 #define ETHER_EDSR0_ENT 0x00000002
101 #define ETHER_EDSR0_ENR 0x00000001
102 
103 //EDMR0 register
104 #define ETHER_EDMR0_DE 0x00000040
105 #define ETHER_EDMR0_DL 0x00000030
106 #define ETHER_EDMR0_SWRT 0x00000002
107 #define ETHER_EDMR0_SWRR 0x00000001
108 
109 #define ETHER_EDMR0_DL_16 0x00000000
110 #define ETHER_EDMR0_DL_32 0x00000010
111 #define ETHER_EDMR0_DL_64 0x00000020
112 
113 //EDTRR0 register
114 #define ETHER_EDTRR0_TR 0x00000003
115 
116 //EDRRR0 register
117 #define ETHER_EDRRR0_RR 0x00000001
118 
119 //EESR0 register
120 #define ETHER_EESR0_TWB 0xC0000000
121 #define ETHER_EESR0_TC1 0x20000000
122 #define ETHER_EESR0_TUC 0x10000000
123 #define ETHER_EESR0_ROC 0x08000000
124 #define ETHER_EESR0_TABT 0x04000000
125 #define ETHER_EESR0_RABT 0x02000000
126 #define ETHER_EESR0_RFCOF 0x01000000
127 #define ETHER_EESR0_ECI 0x00400000
128 #define ETHER_EESR0_TC0 0x00200000
129 #define ETHER_EESR0_TDE 0x00100000
130 #define ETHER_EESR0_TFUF 0x00080000
131 #define ETHER_EESR0_FR 0x00040000
132 #define ETHER_EESR0_RDE 0x00020000
133 #define ETHER_EESR0_RFOF 0x00010000
134 #define ETHER_EESR0_RMAF 0x00000080
135 #define ETHER_EESR0_RRF 0x00000010
136 #define ETHER_EESR0_RTLF 0x00000008
137 #define ETHER_EESR0_RTSF 0x00000004
138 #define ETHER_EESR0_PRE 0x00000002
139 #define ETHER_EESR0_CERF 0x00000001
140 
141 //EESIPR0 register
142 #define ETHER_EESIPR0_TWBIP 0xC0000000
143 #define ETHER_EESIPR0_TC1IP 0x20000000
144 #define ETHER_EESIPR0_TUCIP 0x10000000
145 #define ETHER_EESIPR0_ROCIP 0x08000000
146 #define ETHER_EESIPR0_TABTIP 0x04000000
147 #define ETHER_EESIPR0_RABTIP 0x02000000
148 #define ETHER_EESIPR0_RFCOFIP 0x01000000
149 #define ETHER_EESIPR0_ECIIP 0x00400000
150 #define ETHER_EESIPR0_TC0IP 0x00200000
151 #define ETHER_EESIPR0_TDEIP 0x00100000
152 #define ETHER_EESIPR0_TFUFIP 0x00080000
153 #define ETHER_EESIPR0_FRIP 0x00040000
154 #define ETHER_EESIPR0_RDEIP 0x00020000
155 #define ETHER_EESIPR0_RFOFIP 0x00010000
156 #define ETHER_EESIPR0_RMAFIP 0x00000080
157 #define ETHER_EESIPR0_RRFIP 0x00000010
158 #define ETHER_EESIPR0_RTLFIP 0x00000008
159 #define ETHER_EESIPR0_RTSFIP 0x00000004
160 #define ETHER_EESIPR0_PREIP 0x00000002
161 #define ETHER_EESIPR0_CERFIP 0x00000001
162 
163 //TDFFR0 register
164 #define ETHER_TDFFR_TDLF 0x00000001
165 
166 //RDFFR0 register
167 #define ETHER_RDFFR0_RDLF 0x00000001
168 
169 //FDR0 register
170 #define ETHER_FDR0_TFD 0x00000700
171 #define ETHER_FDR0_RFD 0X0000001F
172 
173 #define ETHER_FDR0_TFD_2048 0x00000700
174 #define ETHER_FDR0_RFD_2048 0x00000007
175 
176 //RMCR0 register
177 #define ETHER_RMCR0_RNC 0x00000001
178 
179 //FCFTR register
180 #define ETHER_FCFTR0_RFF 0x001F0000
181 #define ETHER_FCFTR0_RFD 0x000000FF
182 
183 #define ETHER_FCFTR0_RFF_8 0x00070000
184 #define ETHER_FCFTR0_RFD_2048 0x00000007
185 
186 //Transmit DMA descriptor flags
187 #define ETHER_TD0_TACT 0x80000000
188 #define ETHER_TD0_TDLE 0x40000000
189 #define ETHER_TD0_TFP_SOF 0x20000000
190 #define ETHER_TD0_TFP_EOF 0x10000000
191 #define ETHER_TD0_TFE 0x08000000
192 #define ETHER_TD0_TWBI 0x04000000
193 #define ETHER_TD0_TFS_MASK 0x00000300
194 #define ETHER_TD0_TFS_TUC 0x00000200
195 #define ETHER_TD0_TFS_TABT 0x00000100
196 #define ETHER_TD1_TDL 0xFFFF0000
197 #define ETHER_TD2_TBA 0xFFFFFFFF
198 
199 //Receive DMA descriptor flags
200 #define ETHER_RD0_RACT 0x80000000
201 #define ETHER_RD0_RDLE 0x40000000
202 #define ETHER_RD0_RFP_SOF 0x20000000
203 #define ETHER_RD0_RFP_EOF 0x10000000
204 #define ETHER_RD0_RFE 0x08000000
205 #define ETHER_RD0_RCSE 0x04000000
206 #define ETHER_RD0_RFS_MASK 0x02DF0000
207 #define ETHER_RD0_RFS_RFOF 0x02000000
208 #define ETHER_RD0_RFS_RMAF 0x00800000
209 #define ETHER_RD0_RFS_RUAF 0x00400000
210 #define ETHER_RD0_RFS_RRF 0x00100000
211 #define ETHER_RD0_RFS_RTLF 0x00080000
212 #define ETHER_RD0_RFS_RTSF 0x00040000
213 #define ETHER_RD0_RFS_PRE 0x00020000
214 #define ETHER_RD0_RFS_CERF 0x00010000
215 #define ETHER_RD0_RCS 0x0000FFFF
216 #define ETHER_RD1_RBL 0xFFFF0000
217 #define ETHER_RD1_RDL 0x0000FFFF
218 #define ETHER_RD2_RBA 0xFFFFFFFF
219 
220 //C++ guard
221 #ifdef __cplusplus
222 extern "C" {
223 #endif
224 
225 
226 /**
227  * @brief Transmit DMA descriptor
228  **/
229 
230 typedef struct
231 {
232  uint32_t td0;
233  uint32_t td1;
234  uint32_t td2;
235  uint32_t padding;
236 } Rza1TxDmaDesc;
237 
238 
239 /**
240  * @brief Receive DMA descriptor
241  **/
242 
243 typedef struct
244 {
245  uint32_t rd0;
246  uint32_t rd1;
247  uint32_t rd2;
248  uint32_t padding;
249 } Rza1RxDmaDesc;
250 
251 
252 //RZ/A1 Ethernet MAC driver
253 extern const NicDriver rza1EthDriver;
254 
255 //RZ/A1 Ethernet MAC related functions
256 error_t rza1EthInit(NetInterface *interface);
257 void rza1EthInitGpio(NetInterface *interface);
258 void rza1EthInitDmaDesc(NetInterface *interface);
259 
260 void rza1EthTick(NetInterface *interface);
261 
262 void rza1EthEnableIrq(NetInterface *interface);
263 void rza1EthDisableIrq(NetInterface *interface);
264 void rza1EthIrqHandler(uint32_t intSense);
265 void rza1EthEventHandler(NetInterface *interface);
266 
268  const NetBuffer *buffer, size_t offset);
269 
271 
274 
275 void rza1EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
276  uint8_t regAddr, uint16_t data);
277 
278 uint16_t rza1EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
279  uint8_t regAddr);
280 
281 void rza1EthWriteSmi(uint32_t data, uint_t length);
282 uint32_t rza1EthReadSmi(uint_t length);
283 
284 //C++ guard
285 #ifdef __cplusplus
286 }
287 #endif
288 
289 #endif
uint8_t length
Definition: dtls_misc.h:149
void rza1EthDisableIrq(NetInterface *interface)
Disable interrupts.
Transmit DMA descriptor.
uint8_t opcode
Definition: dns_common.h:172
void rza1EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
uint16_t rza1EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
uint32_t rza1EthReadSmi(uint_t length)
SMI read operation.
error_t rza1EthInit(NetInterface *interface)
RZ/A1 Ethernet MAC initialization.
error_t rza1EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
const NicDriver rza1EthDriver
RZ/A1 Ethernet MAC driver.
error_t
Error codes.
Definition: error.h:42
void rza1EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t rza1EthReceivePacket(NetInterface *interface)
Receive a packet.
void rza1EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define NetInterface
Definition: net.h:36
void rza1EthTick(NetInterface *interface)
RZ/A1 Ethernet MAC timer handler.
uint16_t regAddr
void rza1EthEventHandler(NetInterface *interface)
RZ/A1 Ethernet MAC event handler.
Network interface controller abstraction layer.
error_t rza1EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void rza1EthIrqHandler(uint32_t intSense)
RZ/A1 Ethernet MAC interrupt service routine.
error_t rza1EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Receive DMA descriptor.
void rza1EthInitGpio(NetInterface *interface)
unsigned int uint_t
Definition: compiler_port.h:45
void rza1EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179