rza1_eth_driver.c
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1 /**
2  * @file rza1_eth_driver.c
3  * @brief Renesas RZ/A1 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "iodefine.h"
36 #include "cpg_iobitmask.h"
37 #include "intc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //Transmit buffer
49 #pragma data_alignment = 32
51 //Receive buffer
52 #pragma data_alignment = 32
54 //Transmit DMA descriptors
55 #pragma data_alignment = 32
57 //Receive DMA descriptors
58 #pragma data_alignment = 32
60 
61 //ARM or GCC compiler?
62 #else
63 
64 //Transmit buffer
66  __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32)));
67 //Receive buffer
69  __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32)));
70 //Transmit DMA descriptors
72  __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32)));
73 //Receive DMA descriptors
75  __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32)));
76 
77 #endif
78 
79 //Current transmit descriptor
80 static uint_t txIndex;
81 //Current receive descriptor
82 static uint_t rxIndex;
83 
84 
85 /**
86  * @brief RZ/A1 Ethernet MAC driver
87  **/
88 
90 {
92  ETH_MTU,
103  TRUE,
104  TRUE,
105  TRUE,
106  TRUE
107 };
108 
109 
110 /**
111  * @brief RZ/A1 Ethernet MAC initialization
112  * @param[in] interface Underlying network interface
113  * @return Error code
114  **/
115 
117 {
118  error_t error;
119 
120  //Debug message
121  TRACE_INFO("Initializing RZ/A1 Ethernet MAC...\r\n");
122 
123  //Save underlying network interface
124  nicDriverInterface = interface;
125 
126  //Enable Ethernet peripheral clock
127  CPG.STBCR7 &= ~CPG_STBCR7_MSTP74;
128 
129  //GPIO configuration
130  rza1EthInitGpio(interface);
131 
132  //Perform software reset
133  ETHER.ARSTR = ETHER_ARSTR_ARST;
134  //Wait for the reset to complete
135  sleep(10);
136 
137  //Start EDMAC transmitting and receiving units
138  ETHER.EDSR0 = ETHER_EDSR0_ENT | ETHER_EDSR0_ENR;
139 
140  //To execute a software reset with this register, 1 must be
141  //written to both the SWRT and SWRR bits simultaneously
142  ETHER.EDMR0 = ETHER_EDMR0_SWRT | ETHER_EDMR0_SWRR;
143  //Wait for the reset to complete
144  while(ETHER.EDMR0 & (ETHER_EDMR0_SWRT | ETHER_EDMR0_SWRR))
145  {
146  }
147 
148  //PHY transceiver initialization
149  error = interface->phyDriver->init(interface);
150  //Failed to initialize PHY transceiver?
151  if(error)
152  return error;
153 
154  //Initialize DMA descriptor lists
155  rza1EthInitDmaDesc(interface);
156 
157  //Select little endian mode and set descriptor length (16 bytes)
158  ETHER.EDMR0 = ETHER_EDMR0_DE | ETHER_EDMR0_DL_16;
159 
160  //Error masks
161  ETHER.TRSCER0 = 0;
162  //Use store and forward mode
163  ETHER.TFTR0 = 0;
164 
165  //Set transmit FIFO size and receive FIFO size (2048 bytes)
167 
168  //Enable continuous reception of multiple frames
169  ETHER.RMCR0 = ETHER_RMCR0_RNC;
170  //No padding insertion into receive data
171  ETHER.RPADIR0 = 0;
172 
173  //Receive FIFO threshold (8 frames or 2048-64 bytes)
174  ETHER.FCFTR0 = ETHER_FCFTR0_RFF_8 | ETHER_FCFTR0_RFD_2048;
175 
176  //Intelligent checksum operation mode
177  ETHER.CSMR = 0;
178 
179  //Enable multicast address filtering
180  ETHER.ECMR0 |= ETH_ECMR0_MCT;
181 
182  //Set the upper 32 bits of the MAC address
183  ETHER.MAHR0 = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
184  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
185 
186  //Set the lower 16 bits of the MAC address
187  ETHER.MALR0 = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
188 
189  //Disable all CAM entries
190  ETHER.TSU_TEN = 0;
191 
192  //Maximum frame length that can be accepted
193  ETHER.RFLR0 = RZA1_ETH_RX_BUFFER_SIZE;
194  //Automatic pause frame
195  ETHER.APR0 = 0;
196  //Manual pause frame
197  ETHER.MPR0 = 0;
198  //Automatic pause frame retransmit count
199  ETHER.TPAUSER0 = 0;
200 
201  //Disable all EMAC interrupts
202  ETHER.ECSIPR0 = 0;
203 
204  //Enable the desired EDMAC interrupts
205  ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP;
206 
207  //Register interrupt handler
208  R_INTC_Regist_Int_Func(INTC_ID_ETHERI, rza1EthIrqHandler);
209  //Configure interrupt priority
210  R_INTC_Set_Priority(INTC_ID_ETHERI, RZA1_ETH_IRQ_PRIORITY);
211 
212  //Enable EDMAC transmission and reception
213  ETHER.ECMR0 |= ETH_ECMR0_RE | ETH_ECMR0_TE;
214 
215  //Instruct the DMA to poll the receive descriptor list
216  ETHER.EDRRR0 = ETHER_EDRRR0_RR;
217 
218  //Accept any packets from the upper layer
219  osSetEvent(&interface->nicTxEvent);
220 
221  //Successful initialization
222  return NO_ERROR;
223 }
224 
225 
226 //RSK RZ/A1H, Stream it! RZ, Hachiko or VK-RZ/A1H evaluation board?
227 #if defined(USE_RSK_RZA1H) || defined(USE_STREAM_IT_RZ) || \
228  defined(USE_HACHIKO) || defined(USE_VK_RZA1H)
229 
230 /**
231  * @brief GPIO configuration
232  * @param[in] interface Underlying network interface
233  **/
234 
235 void rza1EthInitGpio(NetInterface *interface)
236 {
237 //RSK RZ/A1H or Hachiko evaluation board?
238 #if defined(USE_RSK_RZA1H) || defined(USE_HACHIKO)
239  //Configure ET_COL (P1_14)
240  PORT1.PMCn.BIT.PMCn14 = 1;
241  PORT1.PFCn.BIT.PFCn14 = 1;
242  PORT1.PFCEn.BIT.PFCEn14 = 1;
243  PORT1.PFCAEn.BIT.PFCAEn14 = 0;
244  PORT1.PIPCn.BIT.PIPCn14 = 1;
245 
246  //Configure ET_TXCLK (P2_0)
247  PORT2.PMCn.BIT.PMCn0 = 1;
248  PORT2.PFCn.BIT.PFCn0 = 1;
249  PORT2.PFCEn.BIT.PFCEn0 = 0;
250  PORT2.PFCAEn.BIT.PFCAEn0 = 0;
251  PORT2.PIPCn.BIT.PIPCn0 = 1;
252 
253  //Configure ET_TXER (P2_1)
254  PORT2.PMCn.BIT.PMCn1 = 1;
255  PORT2.PFCn.BIT.PFCn1 = 1;
256  PORT2.PFCEn.BIT.PFCEn1 = 0;
257  PORT2.PFCAEn.BIT.PFCAEn1 = 0;
258  PORT2.PIPCn.BIT.PIPCn1 = 1;
259 
260  //Configure ET_TXEN (P2_2)
261  PORT2.PMCn.BIT.PMCn2 = 1;
262  PORT2.PFCn.BIT.PFCn2 = 1;
263  PORT2.PFCEn.BIT.PFCEn2 = 0;
264  PORT2.PFCAEn.BIT.PFCAEn2 = 0;
265  PORT2.PIPCn.BIT.PIPCn2 = 1;
266 
267  //Configure ET_CRS (P2_3)
268  PORT2.PMCn.BIT.PMCn3 = 1;
269  PORT2.PFCn.BIT.PFCn3 = 1;
270  PORT2.PFCEn.BIT.PFCEn3 = 0;
271  PORT2.PFCAEn.BIT.PFCAEn3 = 0;
272  PORT2.PIPCn.BIT.PIPCn3 = 1;
273 
274  //Configure ET_TXD0 (P2_4)
275  PORT2.PMCn.BIT.PMCn4 = 1;
276  PORT2.PFCn.BIT.PFCn4 = 1;
277  PORT2.PFCEn.BIT.PFCEn4 = 0;
278  PORT2.PFCAEn.BIT.PFCAEn4 = 0;
279  PORT2.PIPCn.BIT.PIPCn4 = 1;
280 
281  //Configure ET_TXD1 (P2_5)
282  PORT2.PMCn.BIT.PMCn5 = 1;
283  PORT2.PFCn.BIT.PFCn5 = 1;
284  PORT2.PFCEn.BIT.PFCEn5 = 0;
285  PORT2.PFCAEn.BIT.PFCAEn5 = 0;
286  PORT2.PIPCn.BIT.PIPCn5 = 1;
287 
288  //Configure ET_TXD2 (P2_6)
289  PORT2.PMCn.BIT.PMCn6 = 1;
290  PORT2.PFCn.BIT.PFCn6 = 1;
291  PORT2.PFCEn.BIT.PFCEn6 = 0;
292  PORT2.PFCAEn.BIT.PFCAEn6 = 0;
293  PORT2.PIPCn.BIT.PIPCn6 = 1;
294 
295  //Configure ET_TXD3 (P2_7)
296  PORT2.PMCn.BIT.PMCn7 = 1;
297  PORT2.PFCn.BIT.PFCn7 = 1;
298  PORT2.PFCEn.BIT.PFCEn7 = 0;
299  PORT2.PFCAEn.BIT.PFCAEn7 = 0;
300  PORT2.PIPCn.BIT.PIPCn7 = 1;
301 
302  //Configure ET_RXD0 (P2_8)
303  PORT2.PMCn.BIT.PMCn8 = 1;
304  PORT2.PFCn.BIT.PFCn8 = 1;
305  PORT2.PFCEn.BIT.PFCEn8 = 0;
306  PORT2.PFCAEn.BIT.PFCAEn8 = 0;
307  PORT2.PIPCn.BIT.PIPCn8 = 1;
308 
309  //Configure ET_RXD1 (P2_9)
310  PORT2.PMCn.BIT.PMCn9 = 1;
311  PORT2.PFCn.BIT.PFCn9 = 1;
312  PORT2.PFCEn.BIT.PFCEn9 = 0;
313  PORT2.PFCAEn.BIT.PFCAEn9 = 0;
314  PORT2.PIPCn.BIT.PIPCn9 = 1;
315 
316  //Configure ET_RXD2 (P2_10)
317  PORT2.PMCn.BIT.PMCn10 = 1;
318  PORT2.PFCn.BIT.PFCn10 = 1;
319  PORT2.PFCEn.BIT.PFCEn10 = 0;
320  PORT2.PFCAEn.BIT.PFCAEn10 = 0;
321  PORT2.PIPCn.BIT.PIPCn10 = 1;
322 
323  //Configure ET_RXD3 (P2_11)
324  PORT2.PMCn.BIT.PMCn11 = 1;
325  PORT2.PFCn.BIT.PFCn11 = 1;
326  PORT2.PFCEn.BIT.PFCEn11 = 0;
327  PORT2.PFCAEn.BIT.PFCAEn11 = 0;
328  PORT2.PIPCn.BIT.PIPCn11 = 1;
329 
330  //Configure ET_MDIO (P3_3)
331  PORT3.PMCn.BIT.PMCn3 = 1;
332  PORT3.PFCn.BIT.PFCn3 = 1;
333  PORT3.PFCEn.BIT.PFCEn3 = 0;
334  PORT3.PFCAEn.BIT.PFCAEn3 = 0;
335  PORT3.PIPCn.BIT.PIPCn3 = 1;
336 
337  //Configure ET_RXCLK (P3_4)
338  PORT3.PMCn.BIT.PMCn4 = 1;
339  PORT3.PFCn.BIT.PFCn4 = 1;
340  PORT3.PFCEn.BIT.PFCEn4 = 0;
341  PORT3.PFCAEn.BIT.PFCAEn4 = 0;
342  PORT3.PIPCn.BIT.PIPCn4 = 1;
343 
344  //Configure ET_RXER (P3_5)
345  PORT3.PMCn.BIT.PMCn5 = 1;
346  PORT3.PFCn.BIT.PFCn5 = 1;
347  PORT3.PFCEn.BIT.PFCEn5 = 0;
348  PORT3.PFCAEn.BIT.PFCAEn5 = 0;
349  PORT3.PIPCn.BIT.PIPCn5 = 1;
350 
351  //Configure ET_RXDV (P3_6)
352  PORT3.PMCn.BIT.PMCn6 = 1;
353  PORT3.PFCn.BIT.PFCn6 = 1;
354  PORT3.PFCEn.BIT.PFCEn6 = 0;
355  PORT3.PFCAEn.BIT.PFCAEn6 = 0;
356  PORT3.PIPCn.BIT.PIPCn6 = 1;
357 
358  //Configure ET_MDC (P5_9)
359  PORT5.PMCn.BIT.PMCn9 = 1;
360  PORT5.PFCn.BIT.PFCn9 = 1;
361  PORT5.PFCEn.BIT.PFCEn9 = 0;
362  PORT5.PFCAEn.BIT.PFCAEn9 = 0;
363  PORT5.PIPCn.BIT.PIPCn9 = 1;
364 
365 //VK-RZ/A1H evaluation board?
366 #elif defined(USE_VK_RZA1H)
367  //Configure ET_COL (P1_14)
368  PORT1.PMCn.BIT.PMCn14 = 1;
369  PORT1.PFCn.BIT.PFCn14 = 1;
370  PORT1.PFCEn.BIT.PFCEn14 = 1;
371  PORT1.PFCAEn.BIT.PFCAEn14 = 0;
372  PORT1.PIPCn.BIT.PIPCn14 = 1;
373 
374  //Configure ET_TXCLK (P2_0)
375  PORT2.PMCn.BIT.PMCn0 = 1;
376  PORT2.PFCn.BIT.PFCn0 = 1;
377  PORT2.PFCEn.BIT.PFCEn0 = 0;
378  PORT2.PFCAEn.BIT.PFCAEn0 = 0;
379  PORT2.PIPCn.BIT.PIPCn0 = 1;
380 
381  //Configure ET_TXER (P2_1)
382  PORT2.PMCn.BIT.PMCn1 = 1;
383  PORT2.PFCn.BIT.PFCn1 = 1;
384  PORT2.PFCEn.BIT.PFCEn1 = 0;
385  PORT2.PFCAEn.BIT.PFCAEn1 = 0;
386  PORT2.PIPCn.BIT.PIPCn1 = 1;
387 
388  //Configure ET_TXEN (P2_2)
389  PORT2.PMCn.BIT.PMCn2 = 1;
390  PORT2.PFCn.BIT.PFCn2 = 1;
391  PORT2.PFCEn.BIT.PFCEn2 = 0;
392  PORT2.PFCAEn.BIT.PFCAEn2 = 0;
393  PORT2.PIPCn.BIT.PIPCn2 = 1;
394 
395  //Configure ET_CRS (P2_3)
396  PORT2.PMCn.BIT.PMCn3 = 1;
397  PORT2.PFCn.BIT.PFCn3 = 1;
398  PORT2.PFCEn.BIT.PFCEn3 = 0;
399  PORT2.PFCAEn.BIT.PFCAEn3 = 0;
400  PORT2.PIPCn.BIT.PIPCn3 = 1;
401 
402  //Configure ET_TXD0 (P2_4)
403  PORT2.PMCn.BIT.PMCn4 = 1;
404  PORT2.PFCn.BIT.PFCn4 = 1;
405  PORT2.PFCEn.BIT.PFCEn4 = 0;
406  PORT2.PFCAEn.BIT.PFCAEn4 = 0;
407  PORT2.PIPCn.BIT.PIPCn4 = 1;
408 
409  //Configure ET_TXD1 (P2_5)
410  PORT2.PMCn.BIT.PMCn5 = 1;
411  PORT2.PFCn.BIT.PFCn5 = 1;
412  PORT2.PFCEn.BIT.PFCEn5 = 0;
413  PORT2.PFCAEn.BIT.PFCAEn5 = 0;
414  PORT2.PIPCn.BIT.PIPCn5 = 1;
415 
416  //Configure ET_TXD2 (P2_6)
417  PORT2.PMCn.BIT.PMCn6 = 1;
418  PORT2.PFCn.BIT.PFCn6 = 1;
419  PORT2.PFCEn.BIT.PFCEn6 = 0;
420  PORT2.PFCAEn.BIT.PFCAEn6 = 0;
421  PORT2.PIPCn.BIT.PIPCn6 = 1;
422 
423  //Configure ET_TXD3 (P2_7)
424  PORT2.PMCn.BIT.PMCn7 = 1;
425  PORT2.PFCn.BIT.PFCn7 = 1;
426  PORT2.PFCEn.BIT.PFCEn7 = 0;
427  PORT2.PFCAEn.BIT.PFCAEn7 = 0;
428  PORT2.PIPCn.BIT.PIPCn7 = 1;
429 
430  //Configure ET_RXD0 (P2_8)
431  PORT2.PMCn.BIT.PMCn8 = 1;
432  PORT2.PFCn.BIT.PFCn8 = 1;
433  PORT2.PFCEn.BIT.PFCEn8 = 0;
434  PORT2.PFCAEn.BIT.PFCAEn8 = 0;
435  PORT2.PIPCn.BIT.PIPCn8 = 1;
436 
437  //Configure ET_RXD1 (P2_9)
438  PORT2.PMCn.BIT.PMCn9 = 1;
439  PORT2.PFCn.BIT.PFCn9 = 1;
440  PORT2.PFCEn.BIT.PFCEn9 = 0;
441  PORT2.PFCAEn.BIT.PFCAEn9 = 0;
442  PORT2.PIPCn.BIT.PIPCn9 = 1;
443 
444  //Configure ET_RXD2 (P2_10)
445  PORT2.PMCn.BIT.PMCn10 = 1;
446  PORT2.PFCn.BIT.PFCn10 = 1;
447  PORT2.PFCEn.BIT.PFCEn10 = 0;
448  PORT2.PFCAEn.BIT.PFCAEn10 = 0;
449  PORT2.PIPCn.BIT.PIPCn10 = 1;
450 
451  //Configure ET_RXD3 (P2_11)
452  PORT2.PMCn.BIT.PMCn11 = 1;
453  PORT2.PFCn.BIT.PFCn11 = 1;
454  PORT2.PFCEn.BIT.PFCEn11 = 0;
455  PORT2.PFCAEn.BIT.PFCAEn11 = 0;
456  PORT2.PIPCn.BIT.PIPCn11 = 1;
457 
458  //Configure ET_MDIO (P3_3)
459  PORT3.PMCn.BIT.PMCn3 = 1;
460  PORT3.PFCn.BIT.PFCn3 = 1;
461  PORT3.PFCEn.BIT.PFCEn3 = 0;
462  PORT3.PFCAEn.BIT.PFCAEn3 = 0;
463  PORT3.PIPCn.BIT.PIPCn3 = 1;
464 
465  //Configure ET_RXCLK (P3_4)
466  PORT3.PMCn.BIT.PMCn4 = 1;
467  PORT3.PFCn.BIT.PFCn4 = 1;
468  PORT3.PFCEn.BIT.PFCEn4 = 0;
469  PORT3.PFCAEn.BIT.PFCAEn4 = 0;
470  PORT3.PIPCn.BIT.PIPCn4 = 1;
471 
472  //Configure ET_RXER (P3_5)
473  PORT3.PMCn.BIT.PMCn5 = 1;
474  PORT3.PFCn.BIT.PFCn5 = 1;
475  PORT3.PFCEn.BIT.PFCEn5 = 0;
476  PORT3.PFCAEn.BIT.PFCAEn5 = 0;
477  PORT3.PIPCn.BIT.PIPCn5 = 1;
478 
479  //Configure ET_RXDV (P3_6)
480  PORT3.PMCn.BIT.PMCn6 = 1;
481  PORT3.PFCn.BIT.PFCn6 = 1;
482  PORT3.PFCEn.BIT.PFCEn6 = 0;
483  PORT3.PFCAEn.BIT.PFCAEn6 = 0;
484  PORT3.PIPCn.BIT.PIPCn6 = 1;
485 
486  //Configure ET_MDC (P7_0)
487  PORT7.PMCn.BIT.PMCn0 = 1;
488  PORT7.PFCn.BIT.PFCn0 = 0;
489  PORT7.PFCEn.BIT.PFCEn0 = 1;
490  PORT7.PFCAEn.BIT.PFCAEn0 = 0;
491  PORT7.PIPCn.BIT.PIPCn0 = 1;
492 
493 //Stream it! RZ evaluation board?
494 #elif defined(USE_STREAM_IT_RZ)
495  //Configure ET_TXD0 (P8_0)
496  PORT8.PMCn.BIT.PMCn0 = 1;
497  PORT8.PFCn.BIT.PFCn0 = 1;
498  PORT8.PFCEn.BIT.PFCEn0 = 0;
499  PORT8.PFCAEn.BIT.PFCAEn0 = 0;
500  PORT8.PIPCn.BIT.PIPCn0 = 1;
501 
502  //Configure ET_TXD1 (P8_1)
503  PORT8.PMCn.BIT.PMCn1 = 1;
504  PORT8.PFCn.BIT.PFCn1 = 1;
505  PORT8.PFCEn.BIT.PFCEn1 = 0;
506  PORT8.PFCAEn.BIT.PFCAEn1 = 0;
507  PORT8.PIPCn.BIT.PIPCn1 = 1;
508 
509  //Configure ET_TXD2 (P8_2)
510  PORT8.PMCn.BIT.PMCn2 = 1;
511  PORT8.PFCn.BIT.PFCn2 = 1;
512  PORT8.PFCEn.BIT.PFCEn2 = 0;
513  PORT8.PFCAEn.BIT.PFCAEn2 = 0;
514  PORT8.PIPCn.BIT.PIPCn2 = 1;
515 
516  //Configure ET_TXD3 (P8_3)
517  PORT8.PMCn.BIT.PMCn3 = 1;
518  PORT8.PFCn.BIT.PFCn3 = 1;
519  PORT8.PFCEn.BIT.PFCEn3 = 0;
520  PORT8.PFCAEn.BIT.PFCAEn3 = 0;
521  PORT8.PIPCn.BIT.PIPCn3 = 1;
522 
523  //Configure ET_TXCLK (P8_4)
524  PORT8.PMCn.BIT.PMCn4 = 1;
525  PORT8.PFCn.BIT.PFCn4 = 1;
526  PORT8.PFCEn.BIT.PFCEn4 = 0;
527  PORT8.PFCAEn.BIT.PFCAEn4 = 0;
528  PORT8.PIPCn.BIT.PIPCn4 = 1;
529 
530  //Configure ET_TXER (P8_5)
531  PORT8.PMCn.BIT.PMCn5 = 1;
532  PORT8.PFCn.BIT.PFCn5 = 1;
533  PORT8.PFCEn.BIT.PFCEn5 = 0;
534  PORT8.PFCAEn.BIT.PFCAEn5 = 0;
535  PORT8.PIPCn.BIT.PIPCn5 = 1;
536 
537  //Configure ET_TXEN (P8_6)
538  PORT8.PMCn.BIT.PMCn6 = 1;
539  PORT8.PFCn.BIT.PFCn6 = 1;
540  PORT8.PFCEn.BIT.PFCEn6 = 0;
541  PORT8.PFCAEn.BIT.PFCAEn6 = 0;
542  PORT8.PIPCn.BIT.PIPCn6 = 1;
543 
544  //Configure ET_RXD0 (P8_7)
545  PORT8.PMCn.BIT.PMCn7 = 1;
546  PORT8.PFCn.BIT.PFCn7 = 1;
547  PORT8.PFCEn.BIT.PFCEn7 = 0;
548  PORT8.PFCAEn.BIT.PFCAEn7 = 0;
549  PORT8.PIPCn.BIT.PIPCn7 = 1;
550 
551  //Configure ET_RXD1 (P8_8)
552  PORT8.PMCn.BIT.PMCn8 = 1;
553  PORT8.PFCn.BIT.PFCn8 = 1;
554  PORT8.PFCEn.BIT.PFCEn8 = 0;
555  PORT8.PFCAEn.BIT.PFCAEn8 = 0;
556  PORT8.PIPCn.BIT.PIPCn8 = 1;
557 
558  //Configure ET_RXD2 (P8_9)
559  PORT8.PMCn.BIT.PMCn9 = 1;
560  PORT8.PFCn.BIT.PFCn9 = 1;
561  PORT8.PFCEn.BIT.PFCEn9 = 0;
562  PORT8.PFCAEn.BIT.PFCAEn9 = 0;
563  PORT8.PIPCn.BIT.PIPCn9 = 1;
564 
565  //Configure ET_RXD3 (P8_10)
566  PORT8.PMCn.BIT.PMCn10 = 1;
567  PORT8.PFCn.BIT.PFCn10 = 1;
568  PORT8.PFCEn.BIT.PFCEn10 = 0;
569  PORT8.PFCAEn.BIT.PFCAEn10 = 0;
570  PORT8.PIPCn.BIT.PIPCn10 = 1;
571 
572  //Configure ET_COL (P8_14)
573  PORT8.PMCn.BIT.PMCn14 = 1;
574  PORT8.PFCn.BIT.PFCn14 = 1;
575  PORT8.PFCEn.BIT.PFCEn14 = 0;
576  PORT8.PFCAEn.BIT.PFCAEn14 = 0;
577  PORT8.PIPCn.BIT.PIPCn14 = 1;
578 
579  //Configure ET_CRS (P8_15)
580  PORT8.PMCn.BIT.PMCn15 = 1;
581  PORT8.PFCn.BIT.PFCn15 = 1;
582  PORT8.PFCEn.BIT.PFCEn15 = 0;
583  PORT8.PFCAEn.BIT.PFCAEn15 = 0;
584  PORT8.PIPCn.BIT.PIPCn15 = 1;
585 
586  //Configure ET_MDC (P9_0)
587  PORT9.PMCn.BIT.PMCn0 = 1;
588  PORT9.PFCn.BIT.PFCn0 = 1;
589  PORT9.PFCEn.BIT.PFCEn0 = 0;
590  PORT9.PFCAEn.BIT.PFCAEn0 = 0;
591  PORT9.PIPCn.BIT.PIPCn0 = 1;
592 
593  //Configure ET_MDIO (P9_1)
594  PORT9.PMCn.BIT.PMCn1 = 1;
595  PORT9.PFCn.BIT.PFCn1 = 1;
596  PORT9.PFCEn.BIT.PFCEn1 = 0;
597  PORT9.PFCAEn.BIT.PFCAEn1 = 0;
598  PORT9.PIPCn.BIT.PIPCn1 = 1;
599 
600  //Configure ET_RXCLK (P9_2)
601  PORT9.PMCn.BIT.PMCn2 = 1;
602  PORT9.PFCn.BIT.PFCn2 = 1;
603  PORT9.PFCEn.BIT.PFCEn2 = 0;
604  PORT9.PFCAEn.BIT.PFCAEn2 = 0;
605  PORT9.PIPCn.BIT.PIPCn2 = 1;
606 
607  //Configure ET_RXER (P9_3)
608  PORT9.PMCn.BIT.PMCn3 = 1;
609  PORT9.PFCn.BIT.PFCn3 = 1;
610  PORT9.PFCEn.BIT.PFCEn3 = 0;
611  PORT9.PFCAEn.BIT.PFCAEn3 = 0;
612  PORT9.PIPCn.BIT.PIPCn3 = 1;
613 
614  //Configure ET_RXDV (P9_4)
615  PORT9.PMCn.BIT.PMCn4 = 1;
616  PORT9.PFCn.BIT.PFCn4 = 1;
617  PORT9.PFCEn.BIT.PFCEn4 = 0;
618  PORT9.PFCAEn.BIT.PFCAEn4 = 0;
619  PORT9.PIPCn.BIT.PIPCn4 = 1;
620 
621  //Configure PHY_RST (P2_7)
622  PORT2.PMCn.BIT.PMCn7 = 0;
623  PORT2.PIPCn.BIT.PIPCn7 = 0;
624  PORT2.PMn.BIT.PMn7 = 0;
625 
626  //Reset the PHY transceiver
627  PORT2.Pn.BIT.Pn7 = 0;
628  sleep(10);
629  PORT2.Pn.BIT.Pn7 = 1;
630  sleep(10);
631 #endif
632 }
633 
634 #endif
635 
636 
637 /**
638  * @brief Initialize DMA descriptor lists
639  * @param[in] interface Underlying network interface
640  **/
641 
643 {
644  uint_t i;
645 
646  //Initialize TX descriptors
647  for(i = 0; i < RZA1_ETH_TX_BUFFER_COUNT; i++)
648  {
649  //The descriptor is initially owned by the application
650  txDmaDesc[i].td0 = 0;
651  //Transmit buffer length
652  txDmaDesc[i].td1 = 0;
653  //Transmit buffer address
654  txDmaDesc[i].td2 = (uint32_t) txBuffer[i];
655  //Clear padding field
656  txDmaDesc[i].padding = 0;
657  }
658 
659  //Mark the last descriptor entry with the TDLE flag
660  txDmaDesc[i - 1].td0 |= ETHER_TD0_TDLE;
661  //Initialize TX descriptor index
662  txIndex = 0;
663 
664  //Initialize RX descriptors
665  for(i = 0; i < RZA1_ETH_RX_BUFFER_COUNT; i++)
666  {
667  //The descriptor is initially owned by the DMA
668  rxDmaDesc[i].rd0 = ETHER_RD0_RACT;
669  //Receive buffer length
671  //Receive buffer address
672  rxDmaDesc[i].rd2 = (uint32_t) rxBuffer[i];
673  //Clear padding field
674  rxDmaDesc[i].padding = 0;
675  }
676 
677  //Mark the last descriptor entry with the RDLE flag
678  rxDmaDesc[i - 1].rd0 |= ETHER_RD0_RDLE;
679  //Initialize RX descriptor index
680  rxIndex = 0;
681 
682  //Address of the first TX descriptor
683  ETHER.TDLAR0 = (uint32_t) &txDmaDesc[0];
684  ETHER.TDFAR0 = (uint32_t) &txDmaDesc[0];
685  //Address of the last TX descriptor
686  ETHER.TDFXR0 = (uint32_t) &txDmaDesc[RZA1_ETH_TX_BUFFER_COUNT - 1];
687  //Set TDLF flag
688  ETHER.TDFFR0 = ETHER_TDFFR_TDLF;
689 
690  //Address of the first RX descriptor
691  ETHER.RDLAR0 = (uint32_t) &rxDmaDesc[0];
692  ETHER.RDFAR0 = (uint32_t) &rxDmaDesc[0];
693  //Address of the last RX descriptor
694  ETHER.RDFXR0 = (uint32_t) &rxDmaDesc[RZA1_ETH_RX_BUFFER_COUNT - 1];
695  //Set RDLF flag
696  ETHER.RDFFR0 = ETHER_RDFFR0_RDLF;
697 }
698 
699 
700 /**
701  * @brief RZ/A1 Ethernet MAC timer handler
702  *
703  * This routine is periodically called by the TCP/IP stack to
704  * handle periodic operations such as polling the link state
705  *
706  * @param[in] interface Underlying network interface
707  **/
708 
709 void rza1EthTick(NetInterface *interface)
710 {
711  //Handle periodic operations
712  interface->phyDriver->tick(interface);
713 }
714 
715 
716 /**
717  * @brief Enable interrupts
718  * @param[in] interface Underlying network interface
719  **/
720 
722 {
723  //Enable Ethernet MAC interrupts
724  R_INTC_Enable(INTC_ID_ETHERI);
725  //Enable Ethernet PHY interrupts
726  interface->phyDriver->enableIrq(interface);
727 }
728 
729 
730 /**
731  * @brief Disable interrupts
732  * @param[in] interface Underlying network interface
733  **/
734 
736 {
737  //Disable Ethernet MAC interrupts
738  R_INTC_Disable(INTC_ID_ETHERI);
739  //Disable Ethernet PHY interrupts
740  interface->phyDriver->disableIrq(interface);
741 }
742 
743 
744 /**
745  * @brief RZ/A1 Ethernet MAC interrupt service routine
746  * @param[in] intSense Unused parameter
747  **/
748 
749 void rza1EthIrqHandler(uint32_t intSense)
750 {
751  bool_t flag;
752  uint32_t status;
753 
754  //Interrupt service routine prologue
755  osEnterIsr();
756 
757  //This flag will be set if a higher priority task must be woken
758  flag = FALSE;
759 
760  //Read interrupt status register
761  status = ETHER.EESR0;
762 
763  //A packet has been transmitted?
764  if(status & ETHER_EESR0_TWB)
765  {
766  //Clear TWB interrupt flag
767  ETHER.EESR0 = ETHER_EESR0_TWB;
768 
769  //Check whether the TX buffer is available for writing
770  if(!(txDmaDesc[txIndex].td0 & ETHER_TD0_TACT))
771  {
772  //Notify the TCP/IP stack that the transmitter is ready to send
773  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
774  }
775  }
776 
777  //A packet has been received?
778  if(status & ETHER_EESR0_FR)
779  {
780  //Disable FR interrupts
781  ETHER.EESIPR0 &= ~ETHER_EESIPR0_FRIP;
782 
783  //Set event flag
784  nicDriverInterface->nicEvent = TRUE;
785  //Notify the TCP/IP stack of the event
786  flag |= osSetEventFromIsr(&netEvent);
787  }
788 
789  //Interrupt service routine epilogue
790  osExitIsr(flag);
791 }
792 
793 
794 /**
795  * @brief RZ/A1 Ethernet MAC event handler
796  * @param[in] interface Underlying network interface
797  **/
798 
800 {
801  error_t error;
802 
803  //Packet received?
804  if(ETHER.EESR0 & ETHER_EESR0_FR)
805  {
806  //Clear FR interrupt flag
807  ETHER.EESR0 = ETHER_EESR0_FR;
808 
809  //Process all pending packets
810  do
811  {
812  //Read incoming packet
813  error = rza1EthReceivePacket(interface);
814 
815  //No more data in the receive buffer?
816  } while(error != ERROR_BUFFER_EMPTY);
817  }
818 
819  //Re-enable EDMAC interrupts
820  ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP;
821 }
822 
823 
824 /**
825  * @brief Send a packet
826  * @param[in] interface Underlying network interface
827  * @param[in] buffer Multi-part buffer containing the data to send
828  * @param[in] offset Offset to the first data byte
829  * @return Error code
830  **/
831 
833  const NetBuffer *buffer, size_t offset)
834 {
835  //Retrieve the length of the packet
836  size_t length = netBufferGetLength(buffer) - offset;
837 
838  //Check the frame length
840  {
841  //The transmitter can accept another packet
842  osSetEvent(&interface->nicTxEvent);
843  //Report an error
844  return ERROR_INVALID_LENGTH;
845  }
846 
847  //Make sure the current buffer is available for writing
848  if(txDmaDesc[txIndex].td0 & ETHER_TD0_TACT)
849  return ERROR_FAILURE;
850 
851  //Copy user data to the transmit buffer
852  netBufferRead(txBuffer[txIndex], buffer, offset, length);
853 
854  //Write the number of bytes to send
855  txDmaDesc[txIndex].td1 = (length << 16) & ETHER_TD1_TDL;
856 
857  //Check current index
858  if(txIndex < (RZA1_ETH_TX_BUFFER_COUNT - 1))
859  {
860  //Give the ownership of the descriptor to the DMA engine
861  txDmaDesc[txIndex].td0 = ETHER_TD0_TACT | ETHER_TD0_TFP_SOF |
863 
864  //Point to the next descriptor
865  txIndex++;
866  }
867  else
868  {
869  //Give the ownership of the descriptor to the DMA engine
870  txDmaDesc[txIndex].td0 = ETHER_TD0_TACT | ETHER_TD0_TDLE |
872 
873  //Wrap around
874  txIndex = 0;
875  }
876 
877  //Instruct the DMA to poll the transmit descriptor list
878  ETHER.EDTRR0 = ETHER_EDTRR0_TR;
879 
880  //Check whether the next buffer is available for writing
881  if(!(txDmaDesc[txIndex].td0 & ETHER_TD0_TACT))
882  {
883  //The transmitter can accept another packet
884  osSetEvent(&interface->nicTxEvent);
885  }
886 
887  //Successful write operation
888  return NO_ERROR;
889 }
890 
891 
892 /**
893  * @brief Receive a packet
894  * @param[in] interface Underlying network interface
895  * @return Error code
896  **/
898 {
899  static uint8_t temp[RZA1_ETH_RX_BUFFER_SIZE];
900  error_t error;
901  size_t n;
902 
903  //The current buffer is available for reading?
904  if(!(rxDmaDesc[rxIndex].rd0 & ETHER_RD0_RACT))
905  {
906  //SOF and EOF flags should be set
907  if((rxDmaDesc[rxIndex].rd0 & ETHER_RD0_RFP_SOF) &&
908  (rxDmaDesc[rxIndex].rd0 & ETHER_RD0_RFP_EOF))
909  {
910  //Make sure no error occurred
911  if(!(rxDmaDesc[rxIndex].rd0 & (ETHER_RD0_RFS_MASK & ~ETHER_RD0_RFS_RMAF)))
912  {
913  //Retrieve the length of the frame
914  n = rxDmaDesc[rxIndex].rd1 & ETHER_RD1_RDL;
915  //Limit the number of data to read
917 
918  //Copy data from the receive buffer
919  memcpy(temp, rxBuffer[rxIndex], n);
920 
921  //Pass the packet to the upper layer
922  nicProcessPacket(interface, temp, n);
923 
924  //Valid packet received
925  error = NO_ERROR;
926  }
927  else
928  {
929  //The received packet contains an error
930  error = ERROR_INVALID_PACKET;
931  }
932  }
933  else
934  {
935  //The packet is not valid
936  error = ERROR_INVALID_PACKET;
937  }
938 
939  //Check current index
940  if(rxIndex < (RZA1_ETH_RX_BUFFER_COUNT - 1))
941  {
942  //Give the ownership of the descriptor back to the DMA
943  rxDmaDesc[rxIndex].rd0 = ETHER_RD0_RACT;
944  //Point to the next descriptor
945  rxIndex++;
946  }
947  else
948  {
949  //Give the ownership of the descriptor back to the DMA
950  rxDmaDesc[rxIndex].rd0 = ETHER_RD0_RACT | ETHER_RD0_RDLE;
951  //Wrap around
952  rxIndex = 0;
953  }
954 
955  //Instruct the DMA to poll the receive descriptor list
956  ETHER.EDRRR0 = ETHER_EDRRR0_RR;
957  }
958  else
959  {
960  //No more data in the receive buffer
961  error = ERROR_BUFFER_EMPTY;
962  }
963 
964  //Return status code
965  return error;
966 }
967 
968 
969 /**
970  * @brief Configure MAC address filtering
971  * @param[in] interface Underlying network interface
972  * @return Error code
973  **/
974 
976 {
977  uint_t i;
978  volatile uint32_t *addrHigh;
979  volatile uint32_t *addrLow;
980  MacFilterEntry *entry;
981 
982  //Debug message
983  TRACE_DEBUG("Updating MAC filter...\r\n");
984 
985  //Set the upper 32 bits of the MAC address
986  ETHER.MAHR0 = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
987  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
988 
989  //Set the lower 16 bits of the MAC address
990  ETHER.MALR0 = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
991 
992  //The MAC address filter contains the list of MAC addresses to accept
993  //when receiving an Ethernet frame
994  for(i = 0; i < MAC_ADDR_FILTER_SIZE && i < 32; i++)
995  {
996  //Point to the current entry
997  entry = &interface->macAddrFilter[i];
998 
999  //Valid entry?
1000  if(entry->refCount > 0)
1001  {
1002  //Debug message
1003  TRACE_DEBUG(" %s\r\n", macAddrToString(&entry->addr, NULL));
1004 
1005  //Point to the CAM entry registers
1006  addrHigh = &ETHER.TSU_ADRH0 + 2 * i;
1007  addrLow = &ETHER.TSU_ADRL0 + 2 * i;
1008 
1009  //The contents of the CAM entry table registers cannot be
1010  //modified while the ADSBSY flag is set
1011  while(ETHER.TSU_ADSBSY & ETHER_TSU_ADSBSY_ADSBSY)
1012  {
1013  }
1014 
1015  //Set the upper 32 bits of the MAC address
1016  *addrHigh = (entry->addr.b[0] << 24) | (entry->addr.b[1] << 16) |
1017  (entry->addr.b[2] << 8) |entry->addr.b[3];
1018 
1019  //Wait for the ADSBSY flag to be cleared
1020  while(ETHER.TSU_ADSBSY & ETHER_TSU_ADSBSY_ADSBSY)
1021  {
1022  }
1023 
1024  //Set the lower 16 bits of the MAC address
1025  *addrLow = (entry->addr.b[4] << 8) | entry->addr.b[5];
1026 
1027  //Enable the CAM entry
1028  ETHER.TSU_TEN |= 1 << (31 - i);
1029  }
1030  else
1031  {
1032  //Disable the CAM entry
1033  ETHER.TSU_TEN &= ~(1 << (31 - i));
1034  }
1035  }
1036 
1037  //Successful processing
1038  return NO_ERROR;
1039 }
1040 
1041 
1042 /**
1043  * @brief Adjust MAC configuration parameters for proper operation
1044  * @param[in] interface Underlying network interface
1045  * @return Error code
1046  **/
1047 
1049 {
1050  //Half-duplex or full-duplex mode?
1051  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
1052  ETHER.ECMR0 |= ETH_ECMR0_DM;
1053  else
1054  ETHER.ECMR0 &= ~ETH_ECMR0_DM;
1055 
1056  //Successful processing
1057  return NO_ERROR;
1058 }
1059 
1060 
1061 /**
1062  * @brief Write PHY register
1063  * @param[in] opcode Access type (2 bits)
1064  * @param[in] phyAddr PHY address (5 bits)
1065  * @param[in] regAddr Register address (5 bits)
1066  * @param[in] data Register value
1067  **/
1068 
1069 void rza1EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
1070  uint8_t regAddr, uint16_t data)
1071 {
1072  //Synchronization pattern
1074  //Start of frame
1076  //Set up a write operation
1077  rza1EthWriteSmi(opcode, 2);
1078  //Write PHY address
1079  rza1EthWriteSmi(phyAddr, 5);
1080  //Write register address
1082  //Turnaround
1083  rza1EthWriteSmi(SMI_TA, 2);
1084  //Write register value
1085  rza1EthWriteSmi(data, 16);
1086  //Release MDIO
1087  rza1EthReadSmi(1);
1088 }
1089 
1090 
1091 /**
1092  * @brief Read PHY register
1093  * @param[in] opcode Access type (2 bits)
1094  * @param[in] phyAddr PHY address (5 bits)
1095  * @param[in] regAddr Register address (5 bits)
1096  * @return Register value
1097  **/
1098 
1099 uint16_t rza1EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
1100  uint8_t regAddr)
1101 {
1102  uint16_t data;
1103 
1104  //Synchronization pattern
1106  //Start of frame
1108  //Set up a read operation
1109  rza1EthWriteSmi(opcode, 2);
1110  //Write PHY address
1111  rza1EthWriteSmi(phyAddr, 5);
1112  //Write register address
1114  //Turnaround to avoid contention
1115  rza1EthReadSmi(1);
1116  //Read register value
1117  data = rza1EthReadSmi(16);
1118  //Force the PHY to release the MDIO pin
1119  rza1EthReadSmi(1);
1120 
1121  //Return PHY register contents
1122  return data;
1123 }
1124 
1125 
1126 /**
1127  * @brief SMI write operation
1128  * @param[in] data Raw data to be written
1129  * @param[in] length Number of bits to be written
1130  **/
1131 
1133 {
1134  //Skip the most significant bits since they are meaningless
1135  data <<= 32 - length;
1136 
1137  //Configure MDIO as an output
1138  ETHER.PIR0 |= ETHER_PIR0_MMD;
1139 
1140  //Write the specified number of bits
1141  while(length--)
1142  {
1143  //Write MDIO
1144  if(data & 0x80000000)
1145  ETHER.PIR0 |= ETHER_PIR0_MDO;
1146  else
1147  ETHER.PIR0 &= ~ETHER_PIR0_MDO;
1148 
1149  //Assert MDC
1150  usleep(1);
1151  ETHER.PIR0 |= ETHER_PIR0_MDC;
1152  //Deassert MDC
1153  usleep(1);
1154  ETHER.PIR0 &= ~ETHER_PIR0_MDC;
1155 
1156  //Rotate data
1157  data <<= 1;
1158  }
1159 }
1160 
1161 
1162 /**
1163  * @brief SMI read operation
1164  * @param[in] length Number of bits to be read
1165  * @return Data resulting from the MDIO read operation
1166  **/
1167 
1169 {
1170  uint32_t data = 0;
1171 
1172  //Configure MDIO as an input
1173  ETHER.PIR0 &= ~ETHER_PIR0_MMD;
1174 
1175  //Read the specified number of bits
1176  while(length--)
1177  {
1178  //Rotate data
1179  data <<= 1;
1180 
1181  //Assert MDC
1182  ETHER.PIR0 |= ETHER_PIR0_MDC;
1183  usleep(1);
1184  //Deassert MDC
1185  ETHER.PIR0 &= ~ETHER_PIR0_MDC;
1186  usleep(1);
1187 
1188  //Check MDIO state
1189  if(ETHER.PIR0 & ETHER_PIR0_MDI)
1190  data |= 0x00000001;
1191  }
1192 
1193  //Return the received data
1194  return data;
1195 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define ETH_ECMR0_MCT
void rza1EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
#define usleep(delay)
Definition: os_port.h:127
#define ETHER_EESR0_FR
uint8_t length
Definition: dtls_misc.h:149
Transmit DMA descriptor.
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define ETHER_EDRRR0_RR
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:119
#define ETHER_PIR0_MDC
#define ETHER_TDFFR_TDLF
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
#define ETHER_TSU_ADSBSY_ADSBSY
#define sleep(delay)
Definition: os_port.h:131
#define ETHER_RD0_RFP_EOF
#define ETHER_FDR0_TFD_2048
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define ETHER_RDFFR0_RDLF
#define ETHER_RD0_RFP_SOF
#define ETH_ECMR0_RE
error_t rza1EthInit(NetInterface *interface)
RZ/A1 Ethernet MAC initialization.
error_t rza1EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define ETHER_RD0_RACT
#define SMI_TA
Definition: nic.h:64
#define ETHER_TD0_TFP_EOF
#define ETHER_RMCR0_RNC
#define ETHER_EDTRR0_TR
void rza1EthEventHandler(NetInterface *interface)
RZ/A1 Ethernet MAC event handler.
#define SMI_START
Definition: nic.h:60
#define ETHER_EDSR0_ENT
#define ETHER_ARSTR_ARST
#define ETHER_TD0_TACT
#define osExitIsr(flag)
#define ETHER_PIR0_MDO
error_t rza1EthReceivePacket(NetInterface *interface)
Receive a packet.
#define ETHER_FCFTR0_RFD_2048
error_t rza1EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define RZA1_ETH_TX_BUFFER_SIZE
#define FALSE
Definition: os_port.h:46
error_t
Error codes.
Definition: error.h:42
void rza1EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define ETH_ECMR0_TE
#define ETHER_FDR0_RFD_2048
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
char_t * macAddrToString(const MacAddr *macAddr, char_t *str)
Convert a MAC address to a dash delimited string.
Definition: ethernet.c:777
error_t rza1EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define txBuffer
@ ERROR_INVALID_PACKET
Definition: error.h:138
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:222
@ ERROR_INVALID_LENGTH
Definition: error.h:109
@ ERROR_BUFFER_EMPTY
Definition: error.h:139
#define ETHER_EESIPR0_TWBIP
#define ETHER_TD0_TWBI
#define ETHER_EDMR0_SWRR
#define ETHER_RD0_RFS_MASK
OsEvent netEvent
Definition: net.c:77
void rza1EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define ETHER_TD0_TDLE
#define ETHER_TD0_TFP_SOF
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define ETHER_FCFTR0_RFF_8
#define ETHER_RD0_RDLE
#define MIN(a, b)
Definition: os_port.h:62
Renesas RZ/A1 Ethernet MAC controller.
uint16_t rza1EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define rxBuffer
void rza1EthTick(NetInterface *interface)
RZ/A1 Ethernet MAC timer handler.
#define ETHER_PIR0_MDI
#define TRACE_DEBUG(...)
Definition: debug.h:106
#define ETHER_EDMR0_DE
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
MAC filter table entry.
Definition: ethernet.h:220
#define ETHER_EDMR0_DL_16
void rza1EthIrqHandler(uint32_t intSense)
RZ/A1 Ethernet MAC interrupt service routine.
#define ETH_ECMR0_DM
#define osEnterIsr()
#define RZA1_ETH_RX_BUFFER_COUNT
#define RZA1_ETH_TX_BUFFER_COUNT
#define RZA1_ETH_RX_BUFFER_SIZE
#define ETHER_EESR0_TWB
#define rxDmaDesc
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define ETHER_RD1_RDL
const NicDriver rza1EthDriver
RZ/A1 Ethernet MAC driver.
#define ETHER_TD1_TDL
#define txDmaDesc
Receive DMA descriptor.
void rza1EthInitGpio(NetInterface *interface)
uint32_t rza1EthReadSmi(uint_t length)
SMI read operation.
#define ETHER_EDSR0_ENR
#define SMI_SYNC
Definition: nic.h:59
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
#define ETHER_PIR0_MMD
NIC driver.
Definition: nic.h:179
#define ETHER_RD1_RBL
void rza1EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define ETHER_RD0_RFS_RMAF
void rza1EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define ETHER_EESIPR0_FRIP
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:79
#define ETHER_EDMR0_SWRT
#define RZA1_ETH_IRQ_PRIORITY