rza1_eth_driver.c
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1 /**
2  * @file rza1_eth_driver.c
3  * @brief Renesas RZ/A1 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "iodefine.h"
34 #include "cpg_iobitmask.h"
35 #include "intc.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //Transmit buffer
47 #pragma data_alignment = 32
49 //Receive buffer
50 #pragma data_alignment = 32
52 //Transmit DMA descriptors
53 #pragma data_alignment = 32
55 //Receive DMA descriptors
56 #pragma data_alignment = 32
58 
59 //ARM or GCC compiler?
60 #else
61 
62 //Transmit buffer
64  __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32)));
65 //Receive buffer
67  __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32)));
68 //Transmit DMA descriptors
70  __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32)));
71 //Receive DMA descriptors
73  __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32)));
74 
75 #endif
76 
77 //Current transmit descriptor
78 static uint_t txIndex;
79 //Current receive descriptor
80 static uint_t rxIndex;
81 
82 
83 /**
84  * @brief RZ/A1 Ethernet MAC driver
85  **/
86 
88 {
90  ETH_MTU,
101  TRUE,
102  TRUE,
103  TRUE,
104  TRUE
105 };
106 
107 
108 /**
109  * @brief RZ/A1 Ethernet MAC initialization
110  * @param[in] interface Underlying network interface
111  * @return Error code
112  **/
113 
115 {
116  error_t error;
117 
118  //Debug message
119  TRACE_INFO("Initializing RZ/A1 Ethernet MAC...\r\n");
120 
121  //Save underlying network interface
122  nicDriverInterface = interface;
123 
124  //Enable Ethernet peripheral clock
125  CPG.STBCR7 &= ~CPG_STBCR7_MSTP74;
126 
127  //GPIO configuration
128  rza1EthInitGpio(interface);
129 
130  //Perform software reset
131  ETHER.ARSTR = ETHER_ARSTR_ARST;
132  //Wait for the reset to complete
133  sleep(10);
134 
135  //Start EDMAC transmitting and receiving units
136  ETHER.EDSR0 = ETHER_EDSR0_ENT | ETHER_EDSR0_ENR;
137 
138  //To execute a software reset with this register, 1 must be
139  //written to both the SWRT and SWRR bits simultaneously
140  ETHER.EDMR0 = ETHER_EDMR0_SWRT | ETHER_EDMR0_SWRR;
141  //Wait for the reset to complete
142  while(ETHER.EDMR0 & (ETHER_EDMR0_SWRT | ETHER_EDMR0_SWRR));
143 
144  //PHY transceiver initialization
145  error = interface->phyDriver->init(interface);
146  //Failed to initialize PHY transceiver?
147  if(error)
148  return error;
149 
150  //Initialize DMA descriptor lists
151  rza1EthInitDmaDesc(interface);
152 
153  //Select little endian mode and set descriptor length (16 bytes)
154  ETHER.EDMR0 = ETHER_EDMR0_DE | ETHER_EDMR0_DL_16;
155 
156  //Error masks
157  ETHER.TRSCER0 = 0;
158  //Use store and forward mode
159  ETHER.TFTR0 = 0;
160 
161  //Set transmit FIFO size and receive FIFO size (2048 bytes)
163 
164  //Enable continuous reception of multiple frames
165  ETHER.RMCR0 = ETHER_RMCR0_RNC;
166  //No padding insertion into receive data
167  ETHER.RPADIR0 = 0;
168 
169  //Receive FIFO threshold (8 frames or 2048-64 bytes)
170  ETHER.FCFTR0 = ETHER_FCFTR0_RFF_8 | ETHER_FCFTR0_RFD_2048;
171 
172  //Intelligent checksum operation mode
173  ETHER.CSMR = 0;
174 
175  //Enable multicast address filtering
176  ETHER.ECMR0 |= ETH_ECMR0_MCT;
177 
178  //Set the upper 32 bits of the MAC address
179  ETHER.MAHR0 = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
180  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
181 
182  //Set the lower 16 bits of the MAC address
183  ETHER.MALR0 = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
184 
185  //Disable all CAM entries
186  ETHER.TSU_TEN = 0;
187 
188  //Maximum frame length that can be accepted
189  ETHER.RFLR0 = 1518;
190  //Automatic pause frame
191  ETHER.APR0 = 0;
192  //Manual pause frame
193  ETHER.MPR0 = 0;
194  //Automatic pause frame retransmit count
195  ETHER.TPAUSER0 = 0;
196 
197  //Disable all EMAC interrupts
198  ETHER.ECSIPR0 = 0;
199 
200  //Enable the desired EDMAC interrupts
201  ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP;
202 
203  //Register interrupt handler
204  R_INTC_Regist_Int_Func(INTC_ID_ETHERI, rza1EthIrqHandler);
205  //Configure interrupt priority
206  R_INTC_Set_Priority(INTC_ID_ETHERI, RZA1_ETH_IRQ_PRIORITY);
207 
208  //Enable EDMAC transmission and reception
209  ETHER.ECMR0 |= ETH_ECMR0_RE | ETH_ECMR0_TE;
210 
211  //Instruct the DMA to poll the receive descriptor list
212  ETHER.EDRRR0 = ETHER_EDRRR0_RR;
213 
214  //Accept any packets from the upper layer
215  osSetEvent(&interface->nicTxEvent);
216 
217  //Successful initialization
218  return NO_ERROR;
219 }
220 
221 
222 //RSK RZ/A1H, Stream it! RZ, Hachiko or VK-RZ/A1H evaluation board?
223 #if defined(USE_RSK_RZA1H) || defined(USE_STREAM_IT_RZ) || \
224  defined(USE_HACHIKO) || defined(USE_VK_RZA1H)
225 
226 /**
227  * @brief GPIO configuration
228  * @param[in] interface Underlying network interface
229  **/
230 
231 void rza1EthInitGpio(NetInterface *interface)
232 {
233 //RSK RZ/A1H or Hachiko evaluation board?
234 #if defined(USE_RSK_RZA1H) || defined(USE_HACHIKO)
235  //Configure ET_COL (P1_14)
236  PORT1.PMCn.BIT.PMCn14 = 1;
237  PORT1.PFCn.BIT.PFCn14 = 1;
238  PORT1.PFCEn.BIT.PFCEn14 = 1;
239  PORT1.PFCAEn.BIT.PFCAEn14 = 0;
240  PORT1.PIPCn.BIT.PIPCn14 = 1;
241 
242  //Configure ET_TXCLK (P2_0)
243  PORT2.PMCn.BIT.PMCn0 = 1;
244  PORT2.PFCn.BIT.PFCn0 = 1;
245  PORT2.PFCEn.BIT.PFCEn0 = 0;
246  PORT2.PFCAEn.BIT.PFCAEn0 = 0;
247  PORT2.PIPCn.BIT.PIPCn0 = 1;
248 
249  //Configure ET_TXER (P2_1)
250  PORT2.PMCn.BIT.PMCn1 = 1;
251  PORT2.PFCn.BIT.PFCn1 = 1;
252  PORT2.PFCEn.BIT.PFCEn1 = 0;
253  PORT2.PFCAEn.BIT.PFCAEn1 = 0;
254  PORT2.PIPCn.BIT.PIPCn1 = 1;
255 
256  //Configure ET_TXEN (P2_2)
257  PORT2.PMCn.BIT.PMCn2 = 1;
258  PORT2.PFCn.BIT.PFCn2 = 1;
259  PORT2.PFCEn.BIT.PFCEn2 = 0;
260  PORT2.PFCAEn.BIT.PFCAEn2 = 0;
261  PORT2.PIPCn.BIT.PIPCn2 = 1;
262 
263  //Configure ET_CRS (P2_3)
264  PORT2.PMCn.BIT.PMCn3 = 1;
265  PORT2.PFCn.BIT.PFCn3 = 1;
266  PORT2.PFCEn.BIT.PFCEn3 = 0;
267  PORT2.PFCAEn.BIT.PFCAEn3 = 0;
268  PORT2.PIPCn.BIT.PIPCn3 = 1;
269 
270  //Configure ET_TXD0 (P2_4)
271  PORT2.PMCn.BIT.PMCn4 = 1;
272  PORT2.PFCn.BIT.PFCn4 = 1;
273  PORT2.PFCEn.BIT.PFCEn4 = 0;
274  PORT2.PFCAEn.BIT.PFCAEn4 = 0;
275  PORT2.PIPCn.BIT.PIPCn4 = 1;
276 
277  //Configure ET_TXD1 (P2_5)
278  PORT2.PMCn.BIT.PMCn5 = 1;
279  PORT2.PFCn.BIT.PFCn5 = 1;
280  PORT2.PFCEn.BIT.PFCEn5 = 0;
281  PORT2.PFCAEn.BIT.PFCAEn5 = 0;
282  PORT2.PIPCn.BIT.PIPCn5 = 1;
283 
284  //Configure ET_TXD2 (P2_6)
285  PORT2.PMCn.BIT.PMCn6 = 1;
286  PORT2.PFCn.BIT.PFCn6 = 1;
287  PORT2.PFCEn.BIT.PFCEn6 = 0;
288  PORT2.PFCAEn.BIT.PFCAEn6 = 0;
289  PORT2.PIPCn.BIT.PIPCn6 = 1;
290 
291  //Configure ET_TXD3 (P2_7)
292  PORT2.PMCn.BIT.PMCn7 = 1;
293  PORT2.PFCn.BIT.PFCn7 = 1;
294  PORT2.PFCEn.BIT.PFCEn7 = 0;
295  PORT2.PFCAEn.BIT.PFCAEn7 = 0;
296  PORT2.PIPCn.BIT.PIPCn7 = 1;
297 
298  //Configure ET_RXD0 (P2_8)
299  PORT2.PMCn.BIT.PMCn8 = 1;
300  PORT2.PFCn.BIT.PFCn8 = 1;
301  PORT2.PFCEn.BIT.PFCEn8 = 0;
302  PORT2.PFCAEn.BIT.PFCAEn8 = 0;
303  PORT2.PIPCn.BIT.PIPCn8 = 1;
304 
305  //Configure ET_RXD1 (P2_9)
306  PORT2.PMCn.BIT.PMCn9 = 1;
307  PORT2.PFCn.BIT.PFCn9 = 1;
308  PORT2.PFCEn.BIT.PFCEn9 = 0;
309  PORT2.PFCAEn.BIT.PFCAEn9 = 0;
310  PORT2.PIPCn.BIT.PIPCn9 = 1;
311 
312  //Configure ET_RXD2 (P2_10)
313  PORT2.PMCn.BIT.PMCn10 = 1;
314  PORT2.PFCn.BIT.PFCn10 = 1;
315  PORT2.PFCEn.BIT.PFCEn10 = 0;
316  PORT2.PFCAEn.BIT.PFCAEn10 = 0;
317  PORT2.PIPCn.BIT.PIPCn10 = 1;
318 
319  //Configure ET_RXD3 (P2_11)
320  PORT2.PMCn.BIT.PMCn11 = 1;
321  PORT2.PFCn.BIT.PFCn11 = 1;
322  PORT2.PFCEn.BIT.PFCEn11 = 0;
323  PORT2.PFCAEn.BIT.PFCAEn11 = 0;
324  PORT2.PIPCn.BIT.PIPCn11 = 1;
325 
326  //Configure ET_MDIO (P3_3)
327  PORT3.PMCn.BIT.PMCn3 = 1;
328  PORT3.PFCn.BIT.PFCn3 = 1;
329  PORT3.PFCEn.BIT.PFCEn3 = 0;
330  PORT3.PFCAEn.BIT.PFCAEn3 = 0;
331  PORT3.PIPCn.BIT.PIPCn3 = 1;
332 
333  //Configure ET_RXCLK (P3_4)
334  PORT3.PMCn.BIT.PMCn4 = 1;
335  PORT3.PFCn.BIT.PFCn4 = 1;
336  PORT3.PFCEn.BIT.PFCEn4 = 0;
337  PORT3.PFCAEn.BIT.PFCAEn4 = 0;
338  PORT3.PIPCn.BIT.PIPCn4 = 1;
339 
340  //Configure ET_RXER (P3_5)
341  PORT3.PMCn.BIT.PMCn5 = 1;
342  PORT3.PFCn.BIT.PFCn5 = 1;
343  PORT3.PFCEn.BIT.PFCEn5 = 0;
344  PORT3.PFCAEn.BIT.PFCAEn5 = 0;
345  PORT3.PIPCn.BIT.PIPCn5 = 1;
346 
347  //Configure ET_RXDV (P3_6)
348  PORT3.PMCn.BIT.PMCn6 = 1;
349  PORT3.PFCn.BIT.PFCn6 = 1;
350  PORT3.PFCEn.BIT.PFCEn6 = 0;
351  PORT3.PFCAEn.BIT.PFCAEn6 = 0;
352  PORT3.PIPCn.BIT.PIPCn6 = 1;
353 
354  //Configure ET_MDC (P5_9)
355  PORT5.PMCn.BIT.PMCn9 = 1;
356  PORT5.PFCn.BIT.PFCn9 = 1;
357  PORT5.PFCEn.BIT.PFCEn9 = 0;
358  PORT5.PFCAEn.BIT.PFCAEn9 = 0;
359  PORT5.PIPCn.BIT.PIPCn9 = 1;
360 
361 //VK-RZ/A1H evaluation board?
362 #elif defined(USE_VK_RZA1H)
363  //Configure ET_COL (P1_14)
364  PORT1.PMCn.BIT.PMCn14 = 1;
365  PORT1.PFCn.BIT.PFCn14 = 1;
366  PORT1.PFCEn.BIT.PFCEn14 = 1;
367  PORT1.PFCAEn.BIT.PFCAEn14 = 0;
368  PORT1.PIPCn.BIT.PIPCn14 = 1;
369 
370  //Configure ET_TXCLK (P2_0)
371  PORT2.PMCn.BIT.PMCn0 = 1;
372  PORT2.PFCn.BIT.PFCn0 = 1;
373  PORT2.PFCEn.BIT.PFCEn0 = 0;
374  PORT2.PFCAEn.BIT.PFCAEn0 = 0;
375  PORT2.PIPCn.BIT.PIPCn0 = 1;
376 
377  //Configure ET_TXER (P2_1)
378  PORT2.PMCn.BIT.PMCn1 = 1;
379  PORT2.PFCn.BIT.PFCn1 = 1;
380  PORT2.PFCEn.BIT.PFCEn1 = 0;
381  PORT2.PFCAEn.BIT.PFCAEn1 = 0;
382  PORT2.PIPCn.BIT.PIPCn1 = 1;
383 
384  //Configure ET_TXEN (P2_2)
385  PORT2.PMCn.BIT.PMCn2 = 1;
386  PORT2.PFCn.BIT.PFCn2 = 1;
387  PORT2.PFCEn.BIT.PFCEn2 = 0;
388  PORT2.PFCAEn.BIT.PFCAEn2 = 0;
389  PORT2.PIPCn.BIT.PIPCn2 = 1;
390 
391  //Configure ET_CRS (P2_3)
392  PORT2.PMCn.BIT.PMCn3 = 1;
393  PORT2.PFCn.BIT.PFCn3 = 1;
394  PORT2.PFCEn.BIT.PFCEn3 = 0;
395  PORT2.PFCAEn.BIT.PFCAEn3 = 0;
396  PORT2.PIPCn.BIT.PIPCn3 = 1;
397 
398  //Configure ET_TXD0 (P2_4)
399  PORT2.PMCn.BIT.PMCn4 = 1;
400  PORT2.PFCn.BIT.PFCn4 = 1;
401  PORT2.PFCEn.BIT.PFCEn4 = 0;
402  PORT2.PFCAEn.BIT.PFCAEn4 = 0;
403  PORT2.PIPCn.BIT.PIPCn4 = 1;
404 
405  //Configure ET_TXD1 (P2_5)
406  PORT2.PMCn.BIT.PMCn5 = 1;
407  PORT2.PFCn.BIT.PFCn5 = 1;
408  PORT2.PFCEn.BIT.PFCEn5 = 0;
409  PORT2.PFCAEn.BIT.PFCAEn5 = 0;
410  PORT2.PIPCn.BIT.PIPCn5 = 1;
411 
412  //Configure ET_TXD2 (P2_6)
413  PORT2.PMCn.BIT.PMCn6 = 1;
414  PORT2.PFCn.BIT.PFCn6 = 1;
415  PORT2.PFCEn.BIT.PFCEn6 = 0;
416  PORT2.PFCAEn.BIT.PFCAEn6 = 0;
417  PORT2.PIPCn.BIT.PIPCn6 = 1;
418 
419  //Configure ET_TXD3 (P2_7)
420  PORT2.PMCn.BIT.PMCn7 = 1;
421  PORT2.PFCn.BIT.PFCn7 = 1;
422  PORT2.PFCEn.BIT.PFCEn7 = 0;
423  PORT2.PFCAEn.BIT.PFCAEn7 = 0;
424  PORT2.PIPCn.BIT.PIPCn7 = 1;
425 
426  //Configure ET_RXD0 (P2_8)
427  PORT2.PMCn.BIT.PMCn8 = 1;
428  PORT2.PFCn.BIT.PFCn8 = 1;
429  PORT2.PFCEn.BIT.PFCEn8 = 0;
430  PORT2.PFCAEn.BIT.PFCAEn8 = 0;
431  PORT2.PIPCn.BIT.PIPCn8 = 1;
432 
433  //Configure ET_RXD1 (P2_9)
434  PORT2.PMCn.BIT.PMCn9 = 1;
435  PORT2.PFCn.BIT.PFCn9 = 1;
436  PORT2.PFCEn.BIT.PFCEn9 = 0;
437  PORT2.PFCAEn.BIT.PFCAEn9 = 0;
438  PORT2.PIPCn.BIT.PIPCn9 = 1;
439 
440  //Configure ET_RXD2 (P2_10)
441  PORT2.PMCn.BIT.PMCn10 = 1;
442  PORT2.PFCn.BIT.PFCn10 = 1;
443  PORT2.PFCEn.BIT.PFCEn10 = 0;
444  PORT2.PFCAEn.BIT.PFCAEn10 = 0;
445  PORT2.PIPCn.BIT.PIPCn10 = 1;
446 
447  //Configure ET_RXD3 (P2_11)
448  PORT2.PMCn.BIT.PMCn11 = 1;
449  PORT2.PFCn.BIT.PFCn11 = 1;
450  PORT2.PFCEn.BIT.PFCEn11 = 0;
451  PORT2.PFCAEn.BIT.PFCAEn11 = 0;
452  PORT2.PIPCn.BIT.PIPCn11 = 1;
453 
454  //Configure ET_MDIO (P3_3)
455  PORT3.PMCn.BIT.PMCn3 = 1;
456  PORT3.PFCn.BIT.PFCn3 = 1;
457  PORT3.PFCEn.BIT.PFCEn3 = 0;
458  PORT3.PFCAEn.BIT.PFCAEn3 = 0;
459  PORT3.PIPCn.BIT.PIPCn3 = 1;
460 
461  //Configure ET_RXCLK (P3_4)
462  PORT3.PMCn.BIT.PMCn4 = 1;
463  PORT3.PFCn.BIT.PFCn4 = 1;
464  PORT3.PFCEn.BIT.PFCEn4 = 0;
465  PORT3.PFCAEn.BIT.PFCAEn4 = 0;
466  PORT3.PIPCn.BIT.PIPCn4 = 1;
467 
468  //Configure ET_RXER (P3_5)
469  PORT3.PMCn.BIT.PMCn5 = 1;
470  PORT3.PFCn.BIT.PFCn5 = 1;
471  PORT3.PFCEn.BIT.PFCEn5 = 0;
472  PORT3.PFCAEn.BIT.PFCAEn5 = 0;
473  PORT3.PIPCn.BIT.PIPCn5 = 1;
474 
475  //Configure ET_RXDV (P3_6)
476  PORT3.PMCn.BIT.PMCn6 = 1;
477  PORT3.PFCn.BIT.PFCn6 = 1;
478  PORT3.PFCEn.BIT.PFCEn6 = 0;
479  PORT3.PFCAEn.BIT.PFCAEn6 = 0;
480  PORT3.PIPCn.BIT.PIPCn6 = 1;
481 
482  //Configure ET_MDC (P7_0)
483  PORT7.PMCn.BIT.PMCn0 = 1;
484  PORT7.PFCn.BIT.PFCn0 = 0;
485  PORT7.PFCEn.BIT.PFCEn0 = 1;
486  PORT7.PFCAEn.BIT.PFCAEn0 = 0;
487  PORT7.PIPCn.BIT.PIPCn0 = 1;
488 
489 //Stream it! RZ evaluation board?
490 #elif defined(USE_STREAM_IT_RZ)
491  //Configure ET_TXD0 (P8_0)
492  PORT8.PMCn.BIT.PMCn0 = 1;
493  PORT8.PFCn.BIT.PFCn0 = 1;
494  PORT8.PFCEn.BIT.PFCEn0 = 0;
495  PORT8.PFCAEn.BIT.PFCAEn0 = 0;
496  PORT8.PIPCn.BIT.PIPCn0 = 1;
497 
498  //Configure ET_TXD1 (P8_1)
499  PORT8.PMCn.BIT.PMCn1 = 1;
500  PORT8.PFCn.BIT.PFCn1 = 1;
501  PORT8.PFCEn.BIT.PFCEn1 = 0;
502  PORT8.PFCAEn.BIT.PFCAEn1 = 0;
503  PORT8.PIPCn.BIT.PIPCn1 = 1;
504 
505  //Configure ET_TXD2 (P8_2)
506  PORT8.PMCn.BIT.PMCn2 = 1;
507  PORT8.PFCn.BIT.PFCn2 = 1;
508  PORT8.PFCEn.BIT.PFCEn2 = 0;
509  PORT8.PFCAEn.BIT.PFCAEn2 = 0;
510  PORT8.PIPCn.BIT.PIPCn2 = 1;
511 
512  //Configure ET_TXD3 (P8_3)
513  PORT8.PMCn.BIT.PMCn3 = 1;
514  PORT8.PFCn.BIT.PFCn3 = 1;
515  PORT8.PFCEn.BIT.PFCEn3 = 0;
516  PORT8.PFCAEn.BIT.PFCAEn3 = 0;
517  PORT8.PIPCn.BIT.PIPCn3 = 1;
518 
519  //Configure ET_TXCLK (P8_4)
520  PORT8.PMCn.BIT.PMCn4 = 1;
521  PORT8.PFCn.BIT.PFCn4 = 1;
522  PORT8.PFCEn.BIT.PFCEn4 = 0;
523  PORT8.PFCAEn.BIT.PFCAEn4 = 0;
524  PORT8.PIPCn.BIT.PIPCn4 = 1;
525 
526  //Configure ET_TXER (P8_5)
527  PORT8.PMCn.BIT.PMCn5 = 1;
528  PORT8.PFCn.BIT.PFCn5 = 1;
529  PORT8.PFCEn.BIT.PFCEn5 = 0;
530  PORT8.PFCAEn.BIT.PFCAEn5 = 0;
531  PORT8.PIPCn.BIT.PIPCn5 = 1;
532 
533  //Configure ET_TXEN (P8_6)
534  PORT8.PMCn.BIT.PMCn6 = 1;
535  PORT8.PFCn.BIT.PFCn6 = 1;
536  PORT8.PFCEn.BIT.PFCEn6 = 0;
537  PORT8.PFCAEn.BIT.PFCAEn6 = 0;
538  PORT8.PIPCn.BIT.PIPCn6 = 1;
539 
540  //Configure ET_RXD0 (P8_7)
541  PORT8.PMCn.BIT.PMCn7 = 1;
542  PORT8.PFCn.BIT.PFCn7 = 1;
543  PORT8.PFCEn.BIT.PFCEn7 = 0;
544  PORT8.PFCAEn.BIT.PFCAEn7 = 0;
545  PORT8.PIPCn.BIT.PIPCn7 = 1;
546 
547  //Configure ET_RXD1 (P8_8)
548  PORT8.PMCn.BIT.PMCn8 = 1;
549  PORT8.PFCn.BIT.PFCn8 = 1;
550  PORT8.PFCEn.BIT.PFCEn8 = 0;
551  PORT8.PFCAEn.BIT.PFCAEn8 = 0;
552  PORT8.PIPCn.BIT.PIPCn8 = 1;
553 
554  //Configure ET_RXD2 (P8_9)
555  PORT8.PMCn.BIT.PMCn9 = 1;
556  PORT8.PFCn.BIT.PFCn9 = 1;
557  PORT8.PFCEn.BIT.PFCEn9 = 0;
558  PORT8.PFCAEn.BIT.PFCAEn9 = 0;
559  PORT8.PIPCn.BIT.PIPCn9 = 1;
560 
561  //Configure ET_RXD3 (P8_10)
562  PORT8.PMCn.BIT.PMCn10 = 1;
563  PORT8.PFCn.BIT.PFCn10 = 1;
564  PORT8.PFCEn.BIT.PFCEn10 = 0;
565  PORT8.PFCAEn.BIT.PFCAEn10 = 0;
566  PORT8.PIPCn.BIT.PIPCn10 = 1;
567 
568  //Configure ET_COL (P8_14)
569  PORT8.PMCn.BIT.PMCn14 = 1;
570  PORT8.PFCn.BIT.PFCn14 = 1;
571  PORT8.PFCEn.BIT.PFCEn14 = 0;
572  PORT8.PFCAEn.BIT.PFCAEn14 = 0;
573  PORT8.PIPCn.BIT.PIPCn14 = 1;
574 
575  //Configure ET_CRS (P8_15)
576  PORT8.PMCn.BIT.PMCn15 = 1;
577  PORT8.PFCn.BIT.PFCn15 = 1;
578  PORT8.PFCEn.BIT.PFCEn15 = 0;
579  PORT8.PFCAEn.BIT.PFCAEn15 = 0;
580  PORT8.PIPCn.BIT.PIPCn15 = 1;
581 
582  //Configure ET_MDC (P9_0)
583  PORT9.PMCn.BIT.PMCn0 = 1;
584  PORT9.PFCn.BIT.PFCn0 = 1;
585  PORT9.PFCEn.BIT.PFCEn0 = 0;
586  PORT9.PFCAEn.BIT.PFCAEn0 = 0;
587  PORT9.PIPCn.BIT.PIPCn0 = 1;
588 
589  //Configure ET_MDIO (P9_1)
590  PORT9.PMCn.BIT.PMCn1 = 1;
591  PORT9.PFCn.BIT.PFCn1 = 1;
592  PORT9.PFCEn.BIT.PFCEn1 = 0;
593  PORT9.PFCAEn.BIT.PFCAEn1 = 0;
594  PORT9.PIPCn.BIT.PIPCn1 = 1;
595 
596  //Configure ET_RXCLK (P9_2)
597  PORT9.PMCn.BIT.PMCn2 = 1;
598  PORT9.PFCn.BIT.PFCn2 = 1;
599  PORT9.PFCEn.BIT.PFCEn2 = 0;
600  PORT9.PFCAEn.BIT.PFCAEn2 = 0;
601  PORT9.PIPCn.BIT.PIPCn2 = 1;
602 
603  //Configure ET_RXER (P9_3)
604  PORT9.PMCn.BIT.PMCn3 = 1;
605  PORT9.PFCn.BIT.PFCn3 = 1;
606  PORT9.PFCEn.BIT.PFCEn3 = 0;
607  PORT9.PFCAEn.BIT.PFCAEn3 = 0;
608  PORT9.PIPCn.BIT.PIPCn3 = 1;
609 
610  //Configure ET_RXDV (P9_4)
611  PORT9.PMCn.BIT.PMCn4 = 1;
612  PORT9.PFCn.BIT.PFCn4 = 1;
613  PORT9.PFCEn.BIT.PFCEn4 = 0;
614  PORT9.PFCAEn.BIT.PFCAEn4 = 0;
615  PORT9.PIPCn.BIT.PIPCn4 = 1;
616 
617  //Configure PHY_RST (P2_7)
618  PORT2.PMCn.BIT.PMCn7 = 0;
619  PORT2.PIPCn.BIT.PIPCn7 = 0;
620  PORT2.PMn.BIT.PMn7 = 0;
621 
622  //Reset the PHY transceiver
623  PORT2.Pn.BIT.Pn7 = 0;
624  sleep(10);
625 
626  //Take the PHY transceiver out of reset
627  PORT2.Pn.BIT.Pn7 = 1;
628  sleep(10);
629 #endif
630 }
631 
632 #endif
633 
634 
635 /**
636  * @brief Initialize DMA descriptor lists
637  * @param[in] interface Underlying network interface
638  **/
639 
641 {
642  uint_t i;
643 
644  //Initialize TX descriptors
645  for(i = 0; i < RZA1_ETH_TX_BUFFER_COUNT; i++)
646  {
647  //The descriptor is initially owned by the application
648  txDmaDesc[i].td0 = 0;
649  //Transmit buffer length
650  txDmaDesc[i].td1 = 0;
651  //Transmit buffer address
652  txDmaDesc[i].td2 = (uint32_t) txBuffer[i];
653  //Clear padding field
654  txDmaDesc[i].padding = 0;
655  }
656 
657  //Mark the last descriptor entry with the TDLE flag
658  txDmaDesc[i - 1].td0 |= ETHER_TD0_TDLE;
659  //Initialize TX descriptor index
660  txIndex = 0;
661 
662  //Initialize RX descriptors
663  for(i = 0; i < RZA1_ETH_RX_BUFFER_COUNT; i++)
664  {
665  //The descriptor is initially owned by the DMA
666  rxDmaDesc[i].rd0 = ETHER_RD0_RACT;
667  //Receive buffer length
669  //Receive buffer address
670  rxDmaDesc[i].rd2 = (uint32_t) rxBuffer[i];
671  //Clear padding field
672  rxDmaDesc[i].padding = 0;
673  }
674 
675  //Mark the last descriptor entry with the RDLE flag
676  rxDmaDesc[i - 1].rd0 |= ETHER_RD0_RDLE;
677  //Initialize RX descriptor index
678  rxIndex = 0;
679 
680  //Address of the first TX descriptor
681  ETHER.TDLAR0 = (uint32_t) &txDmaDesc[0];
682  ETHER.TDFAR0 = (uint32_t) &txDmaDesc[0];
683  //Address of the last TX descriptor
684  ETHER.TDFXR0 = (uint32_t) &txDmaDesc[RZA1_ETH_TX_BUFFER_COUNT - 1];
685  //Set TDLF flag
686  ETHER.TDFFR0 = ETHER_TDFFR_TDLF;
687 
688  //Address of the first RX descriptor
689  ETHER.RDLAR0 = (uint32_t) &rxDmaDesc[0];
690  ETHER.RDFAR0 = (uint32_t) &rxDmaDesc[0];
691  //Address of the last RX descriptor
692  ETHER.RDFXR0 = (uint32_t) &rxDmaDesc[RZA1_ETH_RX_BUFFER_COUNT - 1];
693  //Set RDLF flag
694  ETHER.RDFFR0 = ETHER_RDFFR0_RDLF;
695 }
696 
697 
698 /**
699  * @brief RZ/A1 Ethernet MAC timer handler
700  *
701  * This routine is periodically called by the TCP/IP stack to
702  * handle periodic operations such as polling the link state
703  *
704  * @param[in] interface Underlying network interface
705  **/
706 
707 void rza1EthTick(NetInterface *interface)
708 {
709  //Handle periodic operations
710  interface->phyDriver->tick(interface);
711 }
712 
713 
714 /**
715  * @brief Enable interrupts
716  * @param[in] interface Underlying network interface
717  **/
718 
720 {
721  //Enable Ethernet MAC interrupts
722  R_INTC_Enable(INTC_ID_ETHERI);
723  //Enable Ethernet PHY interrupts
724  interface->phyDriver->enableIrq(interface);
725 }
726 
727 
728 /**
729  * @brief Disable interrupts
730  * @param[in] interface Underlying network interface
731  **/
732 
734 {
735  //Disable Ethernet MAC interrupts
736  R_INTC_Disable(INTC_ID_ETHERI);
737  //Disable Ethernet PHY interrupts
738  interface->phyDriver->disableIrq(interface);
739 }
740 
741 
742 /**
743  * @brief RZ/A1 Ethernet MAC interrupt service routine
744  * @param[in] intSense Unused parameter
745  **/
746 
747 void rza1EthIrqHandler(uint32_t intSense)
748 {
749  bool_t flag;
750  uint32_t status;
751 
752  //Enter interrupt service routine
753  osEnterIsr();
754 
755  //This flag will be set if a higher priority task must be woken
756  flag = FALSE;
757 
758  //Read interrupt status register
759  status = ETHER.EESR0;
760 
761  //A packet has been transmitted?
762  if(status & ETHER_EESR0_TWB)
763  {
764  //Clear TWB interrupt flag
765  ETHER.EESR0 = ETHER_EESR0_TWB;
766 
767  //Check whether the TX buffer is available for writing
768  if(!(txDmaDesc[txIndex].td0 & ETHER_TD0_TACT))
769  {
770  //Notify the TCP/IP stack that the transmitter is ready to send
771  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
772  }
773  }
774 
775  //A packet has been received?
776  if(status & ETHER_EESR0_FR)
777  {
778  //Disable FR interrupts
779  ETHER.EESIPR0 &= ~ETHER_EESIPR0_FRIP;
780 
781  //Set event flag
782  nicDriverInterface->nicEvent = TRUE;
783  //Notify the TCP/IP stack of the event
784  flag |= osSetEventFromIsr(&netEvent);
785  }
786 
787  //Leave interrupt service routine
788  osExitIsr(flag);
789 }
790 
791 
792 /**
793  * @brief RZ/A1 Ethernet MAC event handler
794  * @param[in] interface Underlying network interface
795  **/
796 
798 {
799  error_t error;
800 
801  //Packet received?
802  if(ETHER.EESR0 & ETHER_EESR0_FR)
803  {
804  //Clear FR interrupt flag
805  ETHER.EESR0 = ETHER_EESR0_FR;
806 
807  //Process all pending packets
808  do
809  {
810  //Read incoming packet
811  error = rza1EthReceivePacket(interface);
812 
813  //No more data in the receive buffer?
814  } while(error != ERROR_BUFFER_EMPTY);
815  }
816 
817  //Re-enable EDMAC interrupts
818  ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP;
819 }
820 
821 
822 /**
823  * @brief Send a packet
824  * @param[in] interface Underlying network interface
825  * @param[in] buffer Multi-part buffer containing the data to send
826  * @param[in] offset Offset to the first data byte
827  * @return Error code
828  **/
829 
831  const NetBuffer *buffer, size_t offset)
832 {
833  //Retrieve the length of the packet
834  size_t length = netBufferGetLength(buffer) - offset;
835 
836  //Check the frame length
838  {
839  //The transmitter can accept another packet
840  osSetEvent(&interface->nicTxEvent);
841  //Report an error
842  return ERROR_INVALID_LENGTH;
843  }
844 
845  //Make sure the current buffer is available for writing
846  if(txDmaDesc[txIndex].td0 & ETHER_TD0_TACT)
847  return ERROR_FAILURE;
848 
849  //Copy user data to the transmit buffer
850  netBufferRead(txBuffer[txIndex], buffer, offset, length);
851 
852  //Write the number of bytes to send
853  txDmaDesc[txIndex].td1 = (length << 16) & ETHER_TD1_TDL;
854 
855  //Check current index
856  if(txIndex < (RZA1_ETH_TX_BUFFER_COUNT - 1))
857  {
858  //Give the ownership of the descriptor to the DMA engine
859  txDmaDesc[txIndex].td0 = ETHER_TD0_TACT | ETHER_TD0_TFP_SOF |
861 
862  //Point to the next descriptor
863  txIndex++;
864  }
865  else
866  {
867  //Give the ownership of the descriptor to the DMA engine
868  txDmaDesc[txIndex].td0 = ETHER_TD0_TACT | ETHER_TD0_TDLE |
870 
871  //Wrap around
872  txIndex = 0;
873  }
874 
875  //Instruct the DMA to poll the transmit descriptor list
876  ETHER.EDTRR0 = ETHER_EDTRR0_TR;
877 
878  //Check whether the next buffer is available for writing
879  if(!(txDmaDesc[txIndex].td0 & ETHER_TD0_TACT))
880  {
881  //The transmitter can accept another packet
882  osSetEvent(&interface->nicTxEvent);
883  }
884 
885  //Successful write operation
886  return NO_ERROR;
887 }
888 
889 
890 /**
891  * @brief Receive a packet
892  * @param[in] interface Underlying network interface
893  * @return Error code
894  **/
896 {
897  static uint8_t temp[RZA1_ETH_RX_BUFFER_SIZE];
898  error_t error;
899  size_t n;
900 
901  //The current buffer is available for reading?
902  if(!(rxDmaDesc[rxIndex].rd0 & ETHER_RD0_RACT))
903  {
904  //SOF and EOF flags should be set
905  if((rxDmaDesc[rxIndex].rd0 & ETHER_RD0_RFP_SOF) &&
906  (rxDmaDesc[rxIndex].rd0 & ETHER_RD0_RFP_EOF))
907  {
908  //Make sure no error occurred
909  if(!(rxDmaDesc[rxIndex].rd0 & (ETHER_RD0_RFS_MASK & ~ETHER_RD0_RFS_RMAF)))
910  {
911  //Retrieve the length of the frame
912  n = rxDmaDesc[rxIndex].rd1 & ETHER_RD1_RDL;
913  //Limit the number of data to read
915 
916  //Copy data from the receive buffer
917  memcpy(temp, rxBuffer[rxIndex], n);
918 
919  //Pass the packet to the upper layer
920  nicProcessPacket(interface, temp, n);
921 
922  //Valid packet received
923  error = NO_ERROR;
924  }
925  else
926  {
927  //The received packet contains an error
928  error = ERROR_INVALID_PACKET;
929  }
930  }
931  else
932  {
933  //The packet is not valid
934  error = ERROR_INVALID_PACKET;
935  }
936 
937  //Check current index
938  if(rxIndex < (RZA1_ETH_RX_BUFFER_COUNT - 1))
939  {
940  //Give the ownership of the descriptor back to the DMA
941  rxDmaDesc[rxIndex].rd0 = ETHER_RD0_RACT;
942  //Point to the next descriptor
943  rxIndex++;
944  }
945  else
946  {
947  //Give the ownership of the descriptor back to the DMA
948  rxDmaDesc[rxIndex].rd0 = ETHER_RD0_RACT | ETHER_RD0_RDLE;
949  //Wrap around
950  rxIndex = 0;
951  }
952 
953  //Instruct the DMA to poll the receive descriptor list
954  ETHER.EDRRR0 = ETHER_EDRRR0_RR;
955  }
956  else
957  {
958  //No more data in the receive buffer
959  error = ERROR_BUFFER_EMPTY;
960  }
961 
962  //Return status code
963  return error;
964 }
965 
966 
967 /**
968  * @brief Configure MAC address filtering
969  * @param[in] interface Underlying network interface
970  * @return Error code
971  **/
972 
974 {
975  uint_t i;
976  volatile uint32_t *addrHigh;
977  volatile uint32_t *addrLow;
978  MacFilterEntry *entry;
979 
980  //Debug message
981  TRACE_DEBUG("Updating RZ/A1 multicast filter...\r\n");
982 
983  //The MAC address filter contains the list of MAC addresses to accept
984  //when receiving an Ethernet frame
985  for(i = 0; i < MAC_ADDR_FILTER_SIZE && i < 32; i++)
986  {
987  //Point to the current entry
988  entry = &interface->macAddrFilter[i];
989 
990  //Valid entry?
991  if(entry->refCount > 0)
992  {
993  //Debug message
994  TRACE_DEBUG(" %s\r\n", macAddrToString(&entry->addr, NULL));
995 
996  //Point to the CAM entry registers
997  addrHigh = &ETHER.TSU_ADRH0 + 2 * i;
998  addrLow = &ETHER.TSU_ADRL0 + 2 * i;
999 
1000  //The contents of the CAM entry table registers cannot be
1001  //modified while the ADSBSY flag is set
1002  while(ETHER.TSU_ADSBSY & ETHER_TSU_ADSBSY_ADSBSY);
1003 
1004  //Set the upper 32 bits of the MAC address
1005  *addrHigh = (entry->addr.b[0] << 24) | (entry->addr.b[1] << 16) |
1006  (entry->addr.b[2] << 8) |entry->addr.b[3];
1007 
1008  //Wait for the ADSBSY flag to be cleared
1009  while(ETHER.TSU_ADSBSY & ETHER_TSU_ADSBSY_ADSBSY);
1010 
1011  //Set the lower 16 bits of the MAC address
1012  *addrLow = (entry->addr.b[4] << 8) | entry->addr.b[5];
1013 
1014  //Enable the CAM entry
1015  ETHER.TSU_TEN |= 1 << (31 - i);
1016  }
1017  else
1018  {
1019  //Disable the CAM entry
1020  ETHER.TSU_TEN &= ~(1 << (31 - i));
1021  }
1022  }
1023 
1024  //Successful processing
1025  return NO_ERROR;
1026 }
1027 
1028 
1029 /**
1030  * @brief Adjust MAC configuration parameters for proper operation
1031  * @param[in] interface Underlying network interface
1032  * @return Error code
1033  **/
1034 
1036 {
1037  //Half-duplex or full-duplex mode?
1038  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
1039  ETHER.ECMR0 |= ETH_ECMR0_DM;
1040  else
1041  ETHER.ECMR0 &= ~ETH_ECMR0_DM;
1042 
1043  //Successful processing
1044  return NO_ERROR;
1045 }
1046 
1047 
1048 /**
1049  * @brief Write PHY register
1050  * @param[in] phyAddr PHY address
1051  * @param[in] regAddr Register address
1052  * @param[in] data Register value
1053  **/
1054 
1055 void rza1EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
1056 {
1057  //Synchronization pattern
1059  //Start of frame
1061  //Set up a write operation
1063  //Write PHY address
1064  rza1EthWriteSmi(phyAddr, 5);
1065  //Write register address
1067  //Turnaround
1068  rza1EthWriteSmi(SMI_TA, 2);
1069  //Write register value
1070  rza1EthWriteSmi(data, 16);
1071  //Release MDIO
1072  rza1EthReadSmi(1);
1073 }
1074 
1075 
1076 /**
1077  * @brief Read PHY register
1078  * @param[in] phyAddr PHY address
1079  * @param[in] regAddr Register address
1080  * @return Register value
1081  **/
1082 
1083 uint16_t rza1EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
1084 {
1085  uint16_t data;
1086 
1087  //Synchronization pattern
1089  //Start of frame
1091  //Set up a read operation
1093  //Write PHY address
1094  rza1EthWriteSmi(phyAddr, 5);
1095  //Write register address
1097  //Turnaround to avoid contention
1098  rza1EthReadSmi(1);
1099  //Read register value
1100  data = rza1EthReadSmi(16);
1101  //Force the PHY to release the MDIO pin
1102  rza1EthReadSmi(1);
1103 
1104  //Return PHY register contents
1105  return data;
1106 }
1107 
1108 
1109 /**
1110  * @brief SMI write operation
1111  * @param[in] data Raw data to be written
1112  * @param[in] length Number of bits to be written
1113  **/
1114 
1116 {
1117  //Skip the most significant bits since they are meaningless
1118  data <<= 32 - length;
1119 
1120  //Configure MDIO as an output
1121  ETHER.PIR0 |= ETHER_PIR0_MMD;
1122 
1123  //Write the specified number of bits
1124  while(length--)
1125  {
1126  //Write MDIO
1127  if(data & 0x80000000)
1128  ETHER.PIR0 |= ETHER_PIR0_MDO;
1129  else
1130  ETHER.PIR0 &= ~ETHER_PIR0_MDO;
1131 
1132  //Assert MDC
1133  usleep(1);
1134  ETHER.PIR0 |= ETHER_PIR0_MDC;
1135  //Deassert MDC
1136  usleep(1);
1137  ETHER.PIR0 &= ~ETHER_PIR0_MDC;
1138 
1139  //Rotate data
1140  data <<= 1;
1141  }
1142 }
1143 
1144 
1145 /**
1146  * @brief SMI read operation
1147  * @param[in] length Number of bits to be read
1148  * @return Data resulting from the MDIO read operation
1149  **/
1150 
1152 {
1153  uint32_t data = 0;
1154 
1155  //Configure MDIO as an input
1156  ETHER.PIR0 &= ~ETHER_PIR0_MMD;
1157 
1158  //Read the specified number of bits
1159  while(length--)
1160  {
1161  //Rotate data
1162  data <<= 1;
1163 
1164  //Assert MDC
1165  ETHER.PIR0 |= ETHER_PIR0_MDC;
1166  usleep(1);
1167  //Deassert MDC
1168  ETHER.PIR0 &= ~ETHER_PIR0_MDC;
1169  usleep(1);
1170 
1171  //Check MDIO state
1172  if(ETHER.PIR0 & ETHER_PIR0_MDI)
1173  data |= 0x00000001;
1174  }
1175 
1176  //Return the received data
1177  return data;
1178 }
#define ETHER_EDRRR0_RR
#define ETHER_PIR0_MDO
#define txDmaDesc
#define ETHER_TDFFR_TDLF
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define RZA1_ETH_RX_BUFFER_SIZE
#define ETHER_RD0_RDLE
void rza1EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
#define ETH_ECMR0_TE
TCP/IP stack core.
const NicDriver rza1EthDriver
RZ/A1 Ethernet MAC driver.
Debugging facilities.
error_t rza1EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define ETHER_EDSR0_ENR
Generic error code.
Definition: error.h:43
void rza1EthEventHandler(NetInterface *interface)
RZ/A1 Ethernet MAC event handler.
void rza1EthInitGpio(NetInterface *interface)
#define ETHER_PIR0_MDC
#define rxDmaDesc
#define txBuffer
#define ETHER_EDMR0_SWRR
#define ETHER_TD0_TDLE
void rza1EthIrqHandler(uint32_t intSense)
RZ/A1 Ethernet MAC interrupt service routine.
#define ETHER_FCFTR0_RFD_2048
#define RZA1_ETH_TX_BUFFER_COUNT
#define sleep(delay)
Definition: os_port.h:126
error_t rza1EthInit(NetInterface *interface)
RZ/A1 Ethernet MAC initialization.
void rza1EthTick(NetInterface *interface)
RZ/A1 Ethernet MAC timer handler.
#define ETHER_EESR0_FR
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define ETHER_FDR0_RFD_2048
uint32_t rza1EthReadSmi(uint_t length)
SMI read operation.
#define ETHER_TSU_ADSBSY_ADSBSY
#define ETHER_RD1_RBL
#define ETHER_EDMR0_DL_16
#define ETHER_RD0_RFS_RMAF
Renesas RZ/A1 Ethernet MAC controller.
#define ETHER_FDR0_TFD_2048
#define RZA1_ETH_RX_BUFFER_COUNT
#define ETHER_RD0_RFS_MASK
error_t rza1EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define ETHER_TD0_TFP_SOF
#define SMI_START
#define ETHER_RD0_RFP_SOF
#define RZA1_ETH_IRQ_PRIORITY
#define SMI_SYNC
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define ETHER_RMCR0_RNC
#define usleep(delay)
Definition: os_port.h:122
uint16_t rza1EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
NIC driver.
Definition: nic.h:161
void rza1EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define ETHER_TD1_TDL
#define ETHER_ARSTR_ARST
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
error_t rza1EthReceivePacket(NetInterface *interface)
Receive a packet.
#define MIN(a, b)
Definition: os_port.h:60
#define ETHER_EESIPR0_TWBIP
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void rza1EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
#define ETHER_RD0_RFP_EOF
Success.
Definition: error.h:42
#define ETHER_EESIPR0_FRIP
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define ETHER_RD0_RACT
unsigned int uint_t
Definition: compiler_port.h:43
#define ETHER_EDMR0_DE
#define ETHER_EDMR0_SWRT
#define ETHER_EESR0_TWB
uint8_t data[]
Definition: dtls_misc.h:167
#define ETH_ECMR0_MCT
#define NetInterface
Definition: net.h:34
#define ETHER_TD0_TWBI
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define SMI_TA
void rza1EthDisableIrq(NetInterface *interface)
Disable interrupts.
Receive DMA descriptor.
#define SMI_READ
#define ETH_ECMR0_DM
char_t * macAddrToString(const MacAddr *macAddr, char_t *str)
Convert a MAC address to a dash delimited string.
Definition: ethernet.c:1243
error_t rza1EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define ETHER_FCFTR0_RFF_8
#define SMI_WRITE
#define ETHER_PIR0_MMD
#define RZA1_ETH_TX_BUFFER_SIZE
#define osExitIsr(flag)
#define osEnterIsr()
#define ETHER_PIR0_MDI
void rza1EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
uint8_t length
Definition: dtls_misc.h:140
#define ETHER_RD1_RDL
uint8_t n
#define ETHER_RDFFR0_RDLF
#define ETHER_EDTRR0_TR
#define ETH_ECMR0_RE
#define FALSE
Definition: os_port.h:44
#define ETHER_TD0_TFP_EOF
int bool_t
Definition: compiler_port.h:47
Transmit DMA descriptor.
#define ETHER_EDSR0_ENT
#define ETHER_TD0_TACT
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98